arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ep108 development board
   4  *
   5  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 /dts-v1/;
  16
  17 #include "zynqmp.dtsi"
  18 #include "zynqmp-ep108-clk.dtsi"
  19
  20 / {
  21         model = "ZynqMP EP108";
  22
  23         aliases {
  24                 mmc0 = &sdhci0;
  25                 mmc1 = &sdhci1;
  26                 serial0 = &uart0;
  27         };
  28
  29         chosen {
  30                 stdout-path = "serial0:115200n8";
  31         };
  32
  33         memory@0 {
  34                 device_type = "memory";
  35                 reg = <0x0 0x0 0x0 0x40000000>;
  36         };
  37 };
  38
  39 &can0 {
  40         status = "okay";
  41 };
  42
  43 &can1 {
  44         status = "okay";
  45 };
  46
  47 &gem0 {
  48         status = "okay";
  49         phy-handle = <&phy0>;
  50         phy-mode = "rgmii-id";
  51         phy0: phy@0 {
  52                 reg = <0>;
  53                 max-speed = <100>;
  54         };
  55 };
  56
  57 &gpio {
  58         status = "okay";
  59 };
  60
  61 &i2c0 {
  62         status = "okay";
  63         clock-frequency = <400000>;
  64         eeprom@54 {
  65                 compatible = "atmel,24c64";
  66                 reg = <0x54>;
  67         };
  68 };
  69
  70 &i2c1 {
  71         status = "okay";
  72         clock-frequency = <400000>;
  73         eeprom@55 {
  74                 compatible = "atmel,24c64";
  75                 reg = <0x55>;
  76         };
  77 };
  78
  79 &sata {
  80         status = "okay";
  81         ceva,broken-gen2;
  82         /* SATA Phy OOB timing settings */
  83         ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
  84         ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
  85         ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
  86         ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
  87         ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
  88         ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
  89         ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
  90         ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
  91 };
  92
  93 &sdhci0 {
  94         status = "okay";
  95 };
  96
  97 &sdhci1 {
  98         status = "okay";
  99 };
 100
 101 &spi0 {
 102         status = "okay";
 103         num-cs = <1>;
 104         spi0_flash0: spi0_flash0@0 {
 105                 compatible = "m25p80";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 spi-max-frequency = <50000000>;
 109                 reg = <0>;
 110
 111                 spi0_flash0@0 {
 112                         label = "spi0_flash0";
 113                         reg = <0x0 0x100000>;
 114                 };
 115         };
 116 };
 117
 118 &spi1 {
 119         status = "okay";
 120         num-cs = <1>;
 121         spi1_flash0: spi1_flash0@0 {
 122                 compatible = "m25p80";
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 spi-max-frequency = <50000000>;
 126                 reg = <0>;
 127
 128                 spi1_flash0@0 {
 129                         label = "spi1_flash0";
 130                         reg = <0x0 0x100000>;
 131                 };
 132         };
 133 };
 134
 135 &uart0 {
 136         status = "okay";
 137 };
 138
 139 &usb0 {
 140         status = "okay";
 141         dr_mode = "peripheral";
 142         maximum-speed = "high-speed";
 143 };
 144
 145 &usb1 {
 146         status = "okay";
 147         dr_mode = "host";
 148         maximum-speed = "high-speed";
 149 };
 150
 151 &watchdog0 {
 152         status = "okay";
 153 };