Documentation/devicetree/bindings/soc/xilinx/xlnx,ai_engine.txt

   1 Xilinx AI Engine
   2 ----------------
   3
   4 The Xilinx AI Engine is a tile processor with many cores (up to 400) that
   5 can run in parallel. The data routing between cores is configured through
   6 internal switches, and shim tiles interface with external interconnect, such
   7 as memory or PL.
   8
   9 Required properties:
  10
  11 - compatible: Must be "xlnx,ai_engine".
  12 - reg: Physical base address and length of the registers set for the device.
  13 - interrupt-parent: the phandle to the interrupt controller.
  14 - interrupts: the interrupt numbers.
  15 - interrupt-names: Should be "interrupt0", "interrupt1", "interrupt2" or
  16   "interrupt3".
  17
  18 Example:
  19
  20         ai_engine@80000000 {
  21                 compatible = "xlnx,ai_engine";
  22                 reg = <0x0 0x80000000 0x0 0x20000000>;
  23                 interrupt-parent = <&gic>;
  24                 interrupts = <0x0 0x94 0x1>,
  25                              <0x0 0x95 0x1>,
  26                              <0x0 0x96 0x1>;
  27                 interrupt-names = "interrupt1", "interrupt2", "interrupt3";
  28         };