arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ZCU111
   3  *
   4  * (C) Copyright 2017, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk-ccf.dtsi"
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU111 RevA";
  21         compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 gpio0 = &gpio;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 mmc0 = &sdhci1;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44                 /* Another 4GB connected to PL */
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51                 autorepeat;
  52                 sw19 {
  53                         label = "sw19";
  54                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  55                         linux,code = <108>; /* down */
  56                         gpio-key,wakeup;
  57                         autorepeat;
  58                 };
  59         };
  60
  61         leds {
  62                 compatible = "gpio-leds";
  63                 heartbeat_led {
  64                         label = "heartbeat";
  65                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  66                         linux,default-trigger = "heartbeat";
  67                 };
  68         };
  69 };
  70
  71 &dcc {
  72         status = "okay";
  73 };
  74
  75 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  76 &fpd_dma_chan1 {
  77         status = "okay";
  78 };
  79
  80 &fpd_dma_chan2 {
  81         status = "okay";
  82 };
  83
  84 &fpd_dma_chan3 {
  85         status = "okay";
  86 };
  87
  88 &fpd_dma_chan4 {
  89         status = "okay";
  90 };
  91
  92 &fpd_dma_chan5 {
  93         status = "okay";
  94 };
  95
  96 &fpd_dma_chan6 {
  97         status = "okay";
  98 };
  99
 100 &fpd_dma_chan7 {
 101         status = "okay";
 102 };
 103
 104 &fpd_dma_chan8 {
 105         status = "okay";
 106 };
 107
 108 &gem3 {
 109         status = "okay";
 110         phy-handle = <&phy0>;
 111         phy-mode = "rgmii-id";
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_gem3_default>;
 114         phy0: phy@c {
 115                 reg = <0xc>;
 116                 ti,rx-internal-delay = <0x8>;
 117                 ti,tx-internal-delay = <0xa>;
 118                 ti,fifo-depth = <0x1>;
 119                 ti,rxctrl-strap-worka;
 120         };
 121 };
 122
 123 &gpio {
 124         status = "okay";
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_gpio_default>;
 127 };
 128
 129 &gpu {
 130         status = "okay";
 131 };
 132
 133 &i2c0 {
 134         status = "okay";
 135         clock-frequency = <400000>;
 136         pinctrl-names = "default", "gpio";
 137         pinctrl-0 = <&pinctrl_i2c0_default>;
 138         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 139         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 140         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 141
 142         tca6416_u22: gpio@20 {
 143                 compatible = "ti,tca6416";
 144                 reg = <0x20>;
 145                 gpio-controller; /* interrupt not connected */
 146                 #gpio-cells = <2>;
 147                 /*
 148                  * IRQ not connected
 149                  * Lines:
 150                  * 0 - MAX6643_OT_B
 151                  * 1 - MAX6643_FANFAIL_B
 152                  * 2 - MIO26_PMU_INPUT_LS
 153                  * 4 - SFP_SI5382_INT_ALM
 154                  * 5 - IIC_MUX_RESET_B
 155                  * 6 - GEM3_EXP_RESET_B
 156                  * 10 - FMCP_HSPC_PRSNT_M2C_B
 157                  * 11 - CLK_SPI_MUX_SEL0
 158                  * 12 - CLK_SPI_MUX_SEL1
 159                  * 16 - IRPS5401_ALERT_B
 160                  * 17 - INA226_PMBUS_ALERT
 161                  * 3, 7, 13-15 - not connected
 162                  */
 163         };
 164
 165         i2cswitch@75 { /* u23 */
 166                 compatible = "nxp,pca9544";
 167                 #address-cells = <1>;
 168                 #size-cells = <0>;
 169                 reg = <0x75>;
 170                 i2c@0 { /* i2c mw 75 0 1 */
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         reg = <0>;
 174                         /* PS_PMBUS */
 175                         /* PMBUS_ALERT done via pca9544 */
 176                         ina226@40 { /* u67 */
 177                                 compatible = "ti,ina226";
 178                                 reg = <0x40>;
 179                                 shunt-resistor = <2000>;
 180                         };
 181                         ina226@41 { /* u59 */
 182                                 compatible = "ti,ina226";
 183                                 reg = <0x41>;
 184                                 shunt-resistor = <5000>;
 185                         };
 186                         ina226@42 { /* u61 */
 187                                 compatible = "ti,ina226";
 188                                 reg = <0x42>;
 189                                 shunt-resistor = <5000>;
 190                         };
 191                         ina226@43 { /* u60 */
 192                                 compatible = "ti,ina226";
 193                                 reg = <0x43>;
 194                                 shunt-resistor = <5000>;
 195                         };
 196                         ina226@45 { /* u64 */
 197                                 compatible = "ti,ina226";
 198                                 reg = <0x45>;
 199                                 shunt-resistor = <5000>;
 200                         };
 201                         ina226@46 { /* u69 */
 202                                 compatible = "ti,ina226";
 203                                 reg = <0x46>;
 204                                 shunt-resistor = <2000>;
 205                         };
 206                         ina226@47 { /* u66 */
 207                                 compatible = "ti,ina226";
 208                                 reg = <0x47>;
 209                                 shunt-resistor = <5000>;
 210                         };
 211                         ina226@48 { /* u65 */
 212                                 compatible = "ti,ina226";
 213                                 reg = <0x48>;
 214                                 shunt-resistor = <5000>;
 215                         };
 216                         ina226@49 { /* u63 */
 217                                 compatible = "ti,ina226";
 218                                 reg = <0x49>;
 219                                 shunt-resistor = <5000>;
 220                         };
 221                         ina226@4a { /* u3 */
 222                                 compatible = "ti,ina226";
 223                                 reg = <0x4a>;
 224                                 shunt-resistor = <5000>;
 225                         };
 226                         ina226@4b { /* u71 */
 227                                 compatible = "ti,ina226";
 228                                 reg = <0x4b>;
 229                                 shunt-resistor = <5000>;
 230                         };
 231                         ina226@4c { /* u77 */
 232                                 compatible = "ti,ina226";
 233                                 reg = <0x4c>;
 234                                 shunt-resistor = <5000>;
 235                         };
 236                         ina226@4d { /* u73 */
 237                                 compatible = "ti,ina226";
 238                                 reg = <0x4d>;
 239                                 shunt-resistor = <5000>;
 240                         };
 241                         ina226@4e { /* u79 */
 242                                 compatible = "ti,ina226";
 243                                 reg = <0x4e>;
 244                                 shunt-resistor = <5000>;
 245                         };
 246                 };
 247                 i2c@1 {
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         reg = <1>;
 251                         /* NC */
 252                 };
 253                 i2c@2 { /* i2c mw 75 0 4 */
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         reg = <2>;
 257                         irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these   */
 258                                 #clock-cells = <0>;
 259                                 compatible = "infineon,irps5401";
 260                                 reg = <0x43>;
 261                         };
 262                         irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
 263                                 #clock-cells = <0>;
 264                                 compatible = "infineon,irps5401";
 265                                 reg = <0x44>;
 266                         };
 267                         irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
 268                                 #clock-cells = <0>;
 269                                 compatible = "infineon,irps5401";
 270                                 reg = <0x45>;
 271                         };
 272                         /* u68 IR38064 +0 */
 273                         /* u70 IR38060 +1 */
 274                         /* u74 IR38060 +2 */
 275                         /* u75 IR38060 +6 */
 276                         /* J19 header too */
 277
 278                 };
 279                 i2c@3 { /* i2c mw 75 0 8 */
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                         reg = <3>;
 283                         /* SYSMON */
 284                 };
 285         };
 286 };
 287
 288 &i2c1 {
 289         status = "okay";
 290         clock-frequency = <400000>;
 291         pinctrl-names = "default", "gpio";
 292         pinctrl-0 = <&pinctrl_i2c1_default>;
 293         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 294         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 295         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 296
 297         i2cswitch@74 { /* u26 */
 298                 compatible = "nxp,pca9548";
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 reg = <0x74>;
 302                 i2c@0 { /* i2c mw 74 0 1 */
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         reg = <0>;
 306                         /*
 307                          * IIC_EEPROM 1kB memory which uses 256B blocks
 308                          * where every block has different address.
 309                          *    0 - 256B address 0x54
 310                          * 256B - 512B address 0x55
 311                          * 512B - 768B address 0x56
 312                          * 768B - 1024B address 0x57
 313                          */
 314                         eeprom: eeprom@54 { /* u88 */
 315                                 compatible = "at,24c08";
 316                                 reg = <0x54>;
 317                         };
 318                 };
 319                 i2c@1 { /* i2c mw 74 0 2 */
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         reg = <1>;
 323                         si5341: clock-generator1@36 { /* SI5341 - u46 */
 324                                 compatible = "si5341";
 325                                 reg = <0x36>;
 326                         };
 327
 328                 };
 329                 i2c@2 { /* i2c mw 74 0 4 */
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         reg = <2>;
 333                         si570_1: clock-generator2@5d { /* USER SI570 - u47 */
 334                                 #clock-cells = <0>;
 335                                 compatible = "silabs,si570";
 336                                 reg = <0x5d>;
 337                                 temperature-stability = <50>;
 338                                 factory-fout = <300000000>;
 339                                 clock-frequency = <300000000>;
 340                         };
 341                 };
 342                 i2c@3 { /* i2c mw 74 0 8 */
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         reg = <3>;
 346                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u49 */
 347                                 #clock-cells = <0>;
 348                                 compatible = "silabs,si570";
 349                                 reg = <0x5d>;
 350                                 temperature-stability = <50>;
 351                                 factory-fout = <156250000>;
 352                                 clock-frequency = <148500000>;
 353                         };
 354                 };
 355                 i2c@4 { /* i2c mw 74 0 10 */
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         reg = <4>;
 359                         si5328: clock-generator4@69 { /* SI5328 - u48 */
 360                                 compatible = "silabs,si5328";
 361                                 reg = <0x69>;
 362                         };
 363                 };
 364                 i2c@5 { /* i2c mw 74 0 11 */
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         reg = <5>;
 368                                 sc18is603@2f { /* sc18is602 - u93 */
 369                                         compatible = "nxp,sc18is603";
 370                                         reg = <0x2f>;
 371                                         /* 4 gpios for CS not handled by driver */
 372                                         /*
 373                                          * USB2ANY cable or
 374                                          * LMK04208 - u90 or
 375                                          * LMX2594 - u102 or
 376                                          * LMX2594 - u103 or
 377                                          * LMX2594 - u104
 378                                          */
 379                                 };
 380                 };
 381                 i2c@6 { /* i2c mw 74 0 11 */
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         reg = <6>;
 385                         /* FMC connector */
 386                 };
 387                 /* 7 NC */
 388         };
 389
 390         i2cswitch@75 {
 391                 compatible = "nxp,pca9548"; /* u27 */
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 reg = <0x75>;
 395
 396                 i2c@0 {
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         reg = <0>;
 400                         /* FMCP_HSPC_IIC */
 401                 };
 402                 i2c@1 {
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         reg = <1>;
 406                         /* NC */
 407                 };
 408                 i2c@2 {
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         reg = <2>;
 412                         /* SYSMON */
 413                 };
 414                 i2c@3 { /* i2c mw 75 0 8 */
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         reg = <3>;
 418                         /* DDR4 SODIMM */
 419                         dev@19 { /* u-boot detection FIXME */
 420                                 compatible = "xxx";
 421                                 reg = <0x19>;
 422                         };
 423                         dev@30 { /* u-boot detection */
 424                                 compatible = "xxx";
 425                                 reg = <0x30>;
 426                         };
 427                         dev@35 { /* u-boot detection */
 428                                 compatible = "xxx";
 429                                 reg = <0x35>;
 430                         };
 431                         dev@36 { /* u-boot detection */
 432                                 compatible = "xxx";
 433                                 reg = <0x36>;
 434                         };
 435                         dev@51 { /* u-boot detection - maybe SPD */
 436                                 compatible = "xxx";
 437                                 reg = <0x51>;
 438                         };
 439                 };
 440                 i2c@4 {
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         reg = <4>;
 444                         /* SFP3 */
 445                 };
 446                 i2c@5 {
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <5>;
 450                         /* SFP2 */
 451                 };
 452                 i2c@6 {
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         reg = <6>;
 456                         /* SFP1 */
 457                 };
 458                 i2c@7 {
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         reg = <7>;
 462                         /* SFP0 */
 463                 };
 464         };
 465 };
 466
 467 &pinctrl0 {
 468         status = "okay";
 469         pinctrl_i2c0_default: i2c0-default {
 470                 mux {
 471                         groups = "i2c0_3_grp";
 472                         function = "i2c0";
 473                 };
 474
 475                 conf {
 476                         groups = "i2c0_3_grp";
 477                         bias-pull-up;
 478                         slew-rate = <SLEW_RATE_SLOW>;
 479                         io-standard = <IO_STANDARD_LVCMOS18>;
 480                 };
 481         };
 482
 483         pinctrl_i2c0_gpio: i2c0-gpio {
 484                 mux {
 485                         groups = "gpio0_14_grp", "gpio0_15_grp";
 486                         function = "gpio0";
 487                 };
 488
 489                 conf {
 490                         groups = "gpio0_14_grp", "gpio0_15_grp";
 491                         slew-rate = <SLEW_RATE_SLOW>;
 492                         io-standard = <IO_STANDARD_LVCMOS18>;
 493                 };
 494         };
 495
 496         pinctrl_i2c1_default: i2c1-default {
 497                 mux {
 498                         groups = "i2c1_4_grp";
 499                         function = "i2c1";
 500                 };
 501
 502                 conf {
 503                         groups = "i2c1_4_grp";
 504                         bias-pull-up;
 505                         slew-rate = <SLEW_RATE_SLOW>;
 506                         io-standard = <IO_STANDARD_LVCMOS18>;
 507                 };
 508         };
 509
 510         pinctrl_i2c1_gpio: i2c1-gpio {
 511                 mux {
 512                         groups = "gpio0_16_grp", "gpio0_17_grp";
 513                         function = "gpio0";
 514                 };
 515
 516                 conf {
 517                         groups = "gpio0_16_grp", "gpio0_17_grp";
 518                         slew-rate = <SLEW_RATE_SLOW>;
 519                         io-standard = <IO_STANDARD_LVCMOS18>;
 520                 };
 521         };
 522
 523         pinctrl_uart0_default: uart0-default {
 524                 mux {
 525                         groups = "uart0_4_grp";
 526                         function = "uart0";
 527                 };
 528
 529                 conf {
 530                         groups = "uart0_4_grp";
 531                         slew-rate = <SLEW_RATE_SLOW>;
 532                         io-standard = <IO_STANDARD_LVCMOS18>;
 533                 };
 534
 535                 conf-rx {
 536                         pins = "MIO18";
 537                         bias-high-impedance;
 538                 };
 539
 540                 conf-tx {
 541                         pins = "MIO19";
 542                         bias-disable;
 543                 };
 544         };
 545
 546         pinctrl_usb0_default: usb0-default {
 547                 mux {
 548                         groups = "usb0_0_grp";
 549                         function = "usb0";
 550                 };
 551
 552                 conf {
 553                         groups = "usb0_0_grp";
 554                         slew-rate = <SLEW_RATE_SLOW>;
 555                         io-standard = <IO_STANDARD_LVCMOS18>;
 556                 };
 557
 558                 conf-rx {
 559                         pins = "MIO52", "MIO53", "MIO55";
 560                         bias-high-impedance;
 561                 };
 562
 563                 conf-tx {
 564                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 565                                "MIO60", "MIO61", "MIO62", "MIO63";
 566                         bias-disable;
 567                 };
 568         };
 569
 570         pinctrl_gem3_default: gem3-default {
 571                 mux {
 572                         function = "ethernet3";
 573                         groups = "ethernet3_0_grp";
 574                 };
 575
 576                 conf {
 577                         groups = "ethernet3_0_grp";
 578                         slew-rate = <SLEW_RATE_SLOW>;
 579                         io-standard = <IO_STANDARD_LVCMOS18>;
 580                 };
 581
 582                 conf-rx {
 583                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 584                                                                         "MIO75";
 585                         bias-high-impedance;
 586                         low-power-disable;
 587                 };
 588
 589                 conf-tx {
 590                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 591                                                                         "MIO69";
 592                         bias-disable;
 593                         low-power-enable;
 594                 };
 595
 596                 mux-mdio {
 597                         function = "mdio3";
 598                         groups = "mdio3_0_grp";
 599                 };
 600
 601                 conf-mdio {
 602                         groups = "mdio3_0_grp";
 603                         slew-rate = <SLEW_RATE_SLOW>;
 604                         io-standard = <IO_STANDARD_LVCMOS18>;
 605                         bias-disable;
 606                 };
 607         };
 608
 609         pinctrl_sdhci1_default: sdhci1-default {
 610                 mux {
 611                         groups = "sdio1_0_grp";
 612                         function = "sdio1";
 613                 };
 614
 615                 conf {
 616                         groups = "sdio1_0_grp";
 617                         slew-rate = <SLEW_RATE_SLOW>;
 618                         io-standard = <IO_STANDARD_LVCMOS18>;
 619                         bias-disable;
 620                 };
 621
 622                 mux-cd {
 623                         groups = "sdio1_cd_0_grp";
 624                         function = "sdio1_cd";
 625                 };
 626
 627                 conf-cd {
 628                         groups = "sdio1_cd_0_grp";
 629                         bias-high-impedance;
 630                         bias-pull-up;
 631                         slew-rate = <SLEW_RATE_SLOW>;
 632                         io-standard = <IO_STANDARD_LVCMOS18>;
 633                 };
 634         };
 635
 636         pinctrl_gpio_default: gpio-default {
 637                 mux {
 638                         function = "gpio0";
 639                         groups = "gpio0_22_grp", "gpio0_23_grp";
 640                 };
 641
 642                 conf {
 643                         groups = "gpio0_22_grp", "gpio0_23_grp";
 644                         slew-rate = <SLEW_RATE_SLOW>;
 645                         io-standard = <IO_STANDARD_LVCMOS18>;
 646                 };
 647
 648                 mux-msp {
 649                         function = "gpio0";
 650                         groups = "gpio0_13_grp", "gpio0_38_grp";
 651                 };
 652
 653                 conf-msp {
 654                         groups = "gpio0_13_grp", "gpio0_38_grp";
 655                         slew-rate = <SLEW_RATE_SLOW>;
 656                         io-standard = <IO_STANDARD_LVCMOS18>;
 657                 };
 658
 659                 conf-pull-up {
 660                         pins = "MIO22";
 661                         bias-pull-up;
 662                 };
 663
 664                 conf-pull-none {
 665                         pins = "MIO13", "MIO23", "MIO38";
 666                         bias-disable;
 667                 };
 668         };
 669 };
 670
 671 &qspi {
 672         status = "okay";
 673         is-dual = <1>;
 674         flash@0 {
 675                 compatible = "m25p80"; /* 32MB */
 676                 #address-cells = <1>;
 677                 #size-cells = <1>;
 678                 reg = <0x0>;
 679                 spi-tx-bus-width = <1>;
 680                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 681                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 682                 partition@qspi-fsbl-uboot { /* for testing purpose */
 683                         label = "qspi-fsbl-uboot";
 684                         reg = <0x0 0x100000>;
 685                 };
 686                 partition@qspi-linux { /* for testing purpose */
 687                         label = "qspi-linux";
 688                         reg = <0x100000 0x500000>;
 689                 };
 690                 partition@qspi-device-tree { /* for testing purpose */
 691                         label = "qspi-device-tree";
 692                         reg = <0x600000 0x20000>;
 693                 };
 694                 partition@qspi-rootfs { /* for testing purpose */
 695                         label = "qspi-rootfs";
 696                         reg = <0x620000 0x5E0000>;
 697                 };
 698         };
 699 };
 700
 701 &rtc {
 702         status = "okay";
 703 };
 704
 705 &sata {
 706         status = "okay";
 707         /* SATA OOB timing settings */
 708         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 709         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 710         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 711         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 712         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 713         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 714         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 715         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 716         phy-names = "sata-phy";
 717         phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
 718 };
 719
 720 /* SD1 with level shifter */
 721 &sdhci1 {
 722         status = "okay";
 723         pinctrl-names = "default";
 724         pinctrl-0 = <&pinctrl_sdhci1_default>;
 725         no-1-8-v;
 726         disable-wp;
 727         xlnx,mio_bank = <1>;
 728 };
 729
 730 &serdes {
 731         status = "okay";
 732 };
 733
 734 &uart0 {
 735         status = "okay";
 736         pinctrl-names = "default";
 737         pinctrl-0 = <&pinctrl_uart0_default>;
 738 };
 739
 740 /* ULPI SMSC USB3320 */
 741 &usb0 {
 742         status = "okay";
 743         pinctrl-names = "default";
 744         pinctrl-0 = <&pinctrl_usb0_default>;
 745 };
 746
 747 &dwc3_0 {
 748         status = "okay";
 749         dr_mode = "host";
 750         snps,usb3_lpm_capable;
 751         phy-names = "usb3-phy";
 752         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 753 };
 754
 755 &zynqmp_dpsub {
 756         status = "okay";
 757         phy-names = "dp-phy0", "dp-phy1";
 758         phys = <&lane1 PHY_TYPE_DP 0 1 27000000>, <&lane0 PHY_TYPE_DP 1 1 27000000>;
 759 };
 760
 761 &zynqmp_dp_snd_pcm0 {
 762         status = "okay";
 763 };
 764
 765 &zynqmp_dp_snd_pcm1 {
 766         status = "okay";
 767 };
 768
 769 &zynqmp_dp_snd_card0 {
 770         status = "okay";
 771 };
 772
 773 &zynqmp_dp_snd_codec0 {
 774         status = "okay";
 775 };
 776
 777 &xlnx_dpdma {
 778         status = "okay";
 779 };