arch/arm/boot/dts/zynq-zc702.dts

   1 /*
   2  * Xilinx ZC702 board DTS
   3  *
   4  *  Copyright (C) 2011 - 2015 Xilinx
   5  *  Copyright (C) 2012 National Instruments Corp.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /dts-v1/;
  10 #include "zynq-7000.dtsi"
  11
  12 / {
  13         model = "Zynq ZC702 Development Board";
  14         compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  15
  16         aliases {
  17                 ethernet0 = &gem0;
  18                 i2c0 = &i2c0;
  19                 serial0 = &uart1;
  20                 spi0 = &qspi;
  21                 mmc0 = &sdhci0;
  22         };
  23
  24         memory@0 {
  25                 device_type = "memory";
  26                 reg = <0x0 0x40000000>;
  27         };
  28
  29         chosen {
  30                 bootargs = "";
  31                 stdout-path = "serial0:115200n8";
  32         };
  33
  34         gpio-keys {
  35                 compatible = "gpio-keys";
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38                 autorepeat;
  39                 sw14 {
  40                         label = "sw14";
  41                         gpios = <&gpio0 12 0>;
  42                         linux,code = <108>; /* down */
  43                         wakeup-source;
  44                         autorepeat;
  45                 };
  46                 sw13 {
  47                         label = "sw13";
  48                         gpios = <&gpio0 14 0>;
  49                         linux,code = <103>; /* up */
  50                         wakeup-source;
  51                         autorepeat;
  52                 };
  53         };
  54
  55         leds {
  56                 compatible = "gpio-leds";
  57
  58                 ds23 {
  59                         label = "ds23";
  60                         gpios = <&gpio0 10 0>;
  61                         linux,default-trigger = "heartbeat";
  62                 };
  63         };
  64
  65         usb_phy0: phy0@e0002000 {
  66                 compatible = "ulpi-phy";
  67                 #phy-cells = <0>;
  68                 reg = <0xe0002000 0x1000>;
  69                 view-port = <0x0170>;
  70                 drv-vbus;
  71         };
  72 };
  73
  74 &amba {
  75         ocm: sram@fffc0000 {
  76                 compatible = "mmio-sram";
  77                 reg = <0xfffc0000 0x10000>;
  78         };
  79 };
  80
  81 &can0 {
  82         status = "okay";
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_can0_default>;
  85 };
  86
  87 &clkc {
  88         ps-clk-frequency = <33333333>;
  89 };
  90
  91 &gem0 {
  92         status = "okay";
  93         phy-mode = "rgmii-id";
  94         phy-handle = <&ethernet_phy>;
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_gem0_default>;
  97         phy-reset-gpio = <&gpio0 11 0>;
  98         phy-reset-active-low;
  99
 100         ethernet_phy: ethernet-phy@7 {
 101                 reg = <7>;
 102                 device_type = "ethernet-phy";
 103         };
 104 };
 105
 106 &gpio0 {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_gpio0_default>;
 109 };
 110
 111 &i2c0 {
 112         status = "okay";
 113         clock-frequency = <400000>;
 114         pinctrl-names = "default", "gpio";
 115         pinctrl-0 = <&pinctrl_i2c0_default>;
 116         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 117         scl-gpios = <&gpio0 50 0>;
 118         sda-gpios = <&gpio0 51 0>;
 119
 120         i2c-mux@74 {
 121                 compatible = "nxp,pca9548";
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124                 reg = <0x74>;
 125
 126                 i2c@0 {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         reg = <0>;
 130                         si570: clock-generator@5d {
 131                                 #clock-cells = <0>;
 132                                 compatible = "silabs,si570";
 133                                 temperature-stability = <50>;
 134                                 reg = <0x5d>;
 135                                 factory-fout = <156250000>;
 136                                 clock-frequency = <148500000>;
 137                         };
 138                 };
 139
 140                 i2c@1 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         reg = <1>;
 144                         adv7511: hdmi-tx@39 {
 145                                 compatible = "adi,adv7511";
 146                                 reg = <0x39>;
 147                                 adi,input-depth = <8>;
 148                                 adi,input-colorspace = "yuv422";
 149                                 adi,input-clock = "1x";
 150                                 adi,input-style = <3>;
 151                                 adi,input-justification = "right";
 152                         };
 153                 };
 154
 155                 i2c@2 {
 156                         #address-cells = <1>;
 157                         #size-cells = <0>;
 158                         reg = <2>;
 159                         eeprom@54 {
 160                                 compatible = "atmel,24c08";
 161                                 reg = <0x54>;
 162                         };
 163                 };
 164
 165                 i2c@3 {
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         reg = <3>;
 169                         gpio@21 {
 170                                 compatible = "ti,tca6416";
 171                                 reg = <0x21>;
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                         };
 175                 };
 176
 177                 i2c@4 {
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         reg = <4>;
 181                         rtc@51 {
 182                                 compatible = "nxp,pcf8563";
 183                                 reg = <0x51>;
 184                         };
 185                 };
 186
 187                 i2c@7 {
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         reg = <7>;
 191                         hwmon@52 {
 192                                 compatible = "ti,ucd9248";
 193                                 reg = <52>;
 194                         };
 195                         hwmon@53 {
 196                                 compatible = "ti,ucd9248";
 197                                 reg = <53>;
 198                         };
 199                         hwmon@54 {
 200                                 compatible = "ti,ucd9248";
 201                                 reg = <54>;
 202                         };
 203                 };
 204         };
 205 };
 206
 207 &pinctrl0 {
 208         pinctrl_can0_default: can0-default {
 209                 mux {
 210                         function = "can0";
 211                         groups = "can0_9_grp";
 212                 };
 213
 214                 conf {
 215                         groups = "can0_9_grp";
 216                         slew-rate = <0>;
 217                         io-standard = <1>;
 218                 };
 219
 220                 conf-rx {
 221                         pins = "MIO46";
 222                         bias-high-impedance;
 223                 };
 224
 225                 conf-tx {
 226                         pins = "MIO47";
 227                         bias-disable;
 228                 };
 229         };
 230
 231         pinctrl_gem0_default: gem0-default {
 232                 mux {
 233                         function = "ethernet0";
 234                         groups = "ethernet0_0_grp";
 235                 };
 236
 237                 conf {
 238                         groups = "ethernet0_0_grp";
 239                         slew-rate = <0>;
 240                         io-standard = <4>;
 241                 };
 242
 243                 conf-rx {
 244                         pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
 245                         bias-high-impedance;
 246                         low-power-disable;
 247                 };
 248
 249                 conf-tx {
 250                         pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
 251                         bias-disable;
 252                         low-power-enable;
 253                 };
 254
 255                 mux-mdio {
 256                         function = "mdio0";
 257                         groups = "mdio0_0_grp";
 258                 };
 259
 260                 conf-mdio {
 261                         groups = "mdio0_0_grp";
 262                         slew-rate = <0>;
 263                         io-standard = <1>;
 264                         bias-disable;
 265                 };
 266         };
 267
 268         pinctrl_gpio0_default: gpio0-default {
 269                 mux {
 270                         function = "gpio0";
 271                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 272                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 273                                  "gpio0_13_grp", "gpio0_14_grp";
 274                 };
 275
 276                 conf {
 277                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 278                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 279                                  "gpio0_13_grp", "gpio0_14_grp";
 280                         slew-rate = <0>;
 281                         io-standard = <1>;
 282                 };
 283
 284                 conf-pull-up {
 285                         pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
 286                         bias-pull-up;
 287                 };
 288
 289                 conf-pull-none {
 290                         pins = "MIO7", "MIO8";
 291                         bias-disable;
 292                 };
 293         };
 294
 295         pinctrl_i2c0_default: i2c0-default {
 296                 mux {
 297                         groups = "i2c0_10_grp";
 298                         function = "i2c0";
 299                 };
 300
 301                 conf {
 302                         groups = "i2c0_10_grp";
 303                         bias-pull-up;
 304                         slew-rate = <0>;
 305                         io-standard = <1>;
 306                 };
 307         };
 308
 309         pinctrl_i2c0_gpio: i2c0-gpio {
 310                 mux {
 311                         groups = "gpio0_50_grp", "gpio0_51_grp";
 312                         function = "gpio0";
 313                 };
 314
 315                 conf {
 316                         groups = "gpio0_50_grp", "gpio0_51_grp";
 317                         slew-rate = <0>;
 318                         io-standard = <1>;
 319                 };
 320         };
 321
 322         pinctrl_sdhci0_default: sdhci0-default {
 323                 mux {
 324                         groups = "sdio0_2_grp";
 325                         function = "sdio0";
 326                 };
 327
 328                 conf {
 329                         groups = "sdio0_2_grp";
 330                         slew-rate = <0>;
 331                         io-standard = <1>;
 332                         bias-disable;
 333                 };
 334
 335                 mux-cd {
 336                         groups = "gpio0_0_grp";
 337                         function = "sdio0_cd";
 338                 };
 339
 340                 conf-cd {
 341                         groups = "gpio0_0_grp";
 342                         bias-high-impedance;
 343                         bias-pull-up;
 344                         slew-rate = <0>;
 345                         io-standard = <1>;
 346                 };
 347
 348                 mux-wp {
 349                         groups = "gpio0_15_grp";
 350                         function = "sdio0_wp";
 351                 };
 352
 353                 conf-wp {
 354                         groups = "gpio0_15_grp";
 355                         bias-high-impedance;
 356                         bias-pull-up;
 357                         slew-rate = <0>;
 358                         io-standard = <1>;
 359                 };
 360         };
 361
 362         pinctrl_uart1_default: uart1-default {
 363                 mux {
 364                         groups = "uart1_10_grp";
 365                         function = "uart1";
 366                 };
 367
 368                 conf {
 369                         groups = "uart1_10_grp";
 370                         slew-rate = <0>;
 371                         io-standard = <1>;
 372                 };
 373
 374                 conf-rx {
 375                         pins = "MIO49";
 376                         bias-high-impedance;
 377                 };
 378
 379                 conf-tx {
 380                         pins = "MIO48";
 381                         bias-disable;
 382                 };
 383         };
 384
 385         pinctrl_usb0_default: usb0-default {
 386                 mux {
 387                         groups = "usb0_0_grp";
 388                         function = "usb0";
 389                 };
 390
 391                 conf {
 392                         groups = "usb0_0_grp";
 393                         slew-rate = <0>;
 394                         io-standard = <1>;
 395                 };
 396
 397                 conf-rx {
 398                         pins = "MIO29", "MIO31", "MIO36";
 399                         bias-high-impedance;
 400                 };
 401
 402                 conf-tx {
 403                         pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
 404                                "MIO35", "MIO37", "MIO38", "MIO39";
 405                         bias-disable;
 406                 };
 407         };
 408 };
 409
 410 &qspi {
 411         u-boot,dm-pre-reloc;
 412         status = "okay";
 413         is-dual = <0>;
 414         num-cs = <1>;
 415         flash@0 {
 416                 compatible = "n25q128a11";
 417                 reg = <0x0>;
 418                 spi-tx-bus-width = <1>;
 419                 spi-rx-bus-width = <4>;
 420                 spi-max-frequency = <50000000>;
 421                 #address-cells = <1>;
 422                 #size-cells = <1>;
 423                 partition@qspi-fsbl-uboot {
 424                         label = "qspi-fsbl-uboot";
 425                         reg = <0x0 0x100000>;
 426                 };
 427                 partition@qspi-linux {
 428                         label = "qspi-linux";
 429                         reg = <0x100000 0x500000>;
 430                 };
 431                 partition@qspi-device-tree {
 432                         label = "qspi-device-tree";
 433                         reg = <0x600000 0x20000>;
 434                 };
 435                 partition@qspi-rootfs {
 436                         label = "qspi-rootfs";
 437                         reg = <0x620000 0x5E0000>;
 438                 };
 439                 partition@qspi-bitstream {
 440                         label = "qspi-bitstream";
 441                         reg = <0xC00000 0x400000>;
 442                 };
 443         };
 444 };
 445
 446 &sdhci0 {
 447         u-boot,dm-pre-reloc;
 448         status = "okay";
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&pinctrl_sdhci0_default>;
 451 };
 452
 453 &uart1 {
 454         u-boot,dm-pre-reloc;
 455         status = "okay";
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pinctrl_uart1_default>;
 458 };
 459
 460 &usb0 {
 461         status = "okay";
 462         dr_mode = "host";
 463         usb-phy = <&usb_phy0>;
 464         pinctrl-names = "default";
 465         pinctrl-0 = <&pinctrl_usb0_default>;
 466 };