Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt

   1 The Xilinx framebuffer DMA engine supports two soft IP blocks: one IP
   2 block is used for reading video frame data from memory (FB Read) to the device
   3 and the other IP block is used for writing video frame data from the device
   4 to memory (FB Write).  Both the FB Read/Write IP blocks are aware of the
   5 format of the data being written to or read from memory including RGB and
   6 YUV in packed, planar, and semi-planar formats.  Because the FB Read/Write
   7 is format aware, only one buffer pointer is needed by the IP blocks even
   8 when planar or semi-planar format are used.
   9
  10 FB Read Required propertie(s):
  11 - compatible            : Should be "xlnx,axi-frmbuf-rd-v2"
  12
  13 Note: Compatible string "xlnx,axi-frmbuf-rd" and the hardware it
  14 represented is no longer supported.
  15
  16 FB Write Required propertie(s):
  17 - compatible            : Should be "xlnx,axi-frmbuf-wr-v2"
  18
  19 Note: Compatible string "xlnx,axi-frmbuf-wr" and the hardware it
  20 represented is no longer supported.
  21
  22 Required Properties Common to both FB Read and FB Write:
  23 - #dma-cells            : should be 1
  24 - interrupt-parent      : Interrupt controller the interrupt is routed through
  25 - interrupts            : Should contain DMA channel interrupt
  26 - reset-gpios           : Should contain GPIO reset phandle
  27 - reg                   : Memory map for module access
  28 - xlnx,dma-addr-width   : Size of dma address pointer in IP (either 32 or 64)
  29 - xlnx,vid-formats      : A list of strings indicating what video memory
  30                           formats the IP has been configured to support.
  31                           See VIDEO FORMATS table below and examples.
  32
  33 VIDEO FORMATS
  34 The following table describes the legal string values to be used for
  35 the xlnx,vid-formats property.  To the left is the string value and the
  36 two columns to the right describe how this is mapped to an equivalent V4L2
  37 and DRM fourcc code---respectively---by the driver.
  38
  39 IP FORMAT       DTS String      V4L2 Fourcc             DRM Fourcc
  40 -------------|----------------|----------------------|---------------------
  41 RGB8            bgr888          V4L2_PIX_FMT_RGB24      DRM_FORMAT_BGR888
  42 BGR8            rgb888          V4L2_PIX_FMT_BGR24      DRM_FORMAT_RGB888
  43 RGBX8           xbgr8888        V4L2_PIX_FMT_BGRX32     DRM_FORMAT_XBGR8888
  44 RGBA8           <none>          <not supported>         <not supported>
  45 BGRA8           <none>          <not supported>         <not supported>
  46 BGRX8           xrgb8888        V4L2_PIX_FMT_XBGR32     DRM_FORMAT_XRGB8888
  47 RGBX10          xbgr2101010     V4L2_PIX_FMT_XBGR30     DRM_FORMAT_XBGR2101010
  48 YUV8            vuy888          V4L2_PIX_FMT_VUY24      DRM_FORMAT_VUY888
  49 YUVX8           xvuy8888        V4L2_PIX_FMT_XVUY32     DRM_FORMAT_XVUY8888
  50 YUYV8           yuyv            V4L2_PIX_FMT_YUYV       DRM_FORMAT_YUYV
  51 UYVY8           uyvy            V4L2_PIX_FMT_UYVY       DRM_FORMAT_UYVY
  52 YUVA8           <none>          <not supported>         <not supported>
  53 YUVX10          yuvx2101010     V4L2_PIX_FMT_XVUY10     DRM_FORMAT_XVUY2101010
  54 Y8              y8              V4L2_PIX_FMT_GREY       DRM_FORMAT_Y8
  55 Y10             y10             V4L2_PIX_FMT_Y10        DRM_FORMAT_Y10
  56 Y_UV8           nv16            V4L2_PIX_FMT_NV16       DRM_FORMAT_NV16
  57 Y_UV8           nv16            V4L2_PIX_FMT_NV16M      DRM_FORMAT_NV16
  58 Y_UV8_420       nv12            V4L2_PIX_FMT_NV12       DRM_FORMAT_NV12
  59 Y_UV8_420       nv12            V4L2_PIX_FMT_NV12M      DRM_FORMAT_NV12
  60 Y_UV10          xv20            V4L2_PIX_FMT_XV20M      DRM_FORMAT_XV20
  61 Y_UV10          xv20            V4L2_PIX_FMT_XV20       <not supported>
  62 Y_UV10_420      xv15            V4L2_PIX_FMT_XV15M      DRM_FORMAT_XV15
  63 Y_UV10_420      xv15            V4L2_PIX_FMT_XV20       <not supported>
  64
  65 Examples
  66
  67 FB Read Example:
  68 ++++++++
  69 v_frmbuf_rd_0: v_frmbuf_rd@80000000 {
  70         #dma-cells = <1>;
  71         compatible = "xlnx,axi-frmbuf-rd-v2";
  72         interrupt-parent = <&gic>;
  73         interrupts = <0 92 4>;
  74         reset-gpios = <&gpio 80 1>;
  75         reg = <0x0 0x80000000 0x0 0x10000>;
  76         xlnx,dma-addr-width = <32>;
  77         xlnx,vid-formats = "bgr888","xbgr8888";
  78 };
  79
  80 FB Write Example:
  81 ++++++++
  82 v_frmbuf_wr_0: v_frmbuf_wr@80000000 {
  83         #dma-cells = <1>;
  84         compatible = "xlnx,axi-frmbuf-wr-v2";
  85         interrupt-parent = <&gic>;
  86         interrupts = <0 92 4>;
  87         reset-gpios = <&gpio 80 1>;
  88         reg = <0x0 0x80000000 0x0 0x10000>;
  89         xlnx,dma-addr-width = <64>;
  90         xlnx,vid-formats = "bgr888","yuyv","nv16","nv12";
  91 };