arch/arm/boot/dts/zynq-7000.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011 - 2015 Xilinx
   4  */
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         compatible = "xlnx,zynq-7000";
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14
  15                 cpu0: cpu@0 {
  16                         compatible = "arm,cortex-a9";
  17                         device_type = "cpu";
  18                         reg = <0>;
  19                         clocks = <&clkc 3>;
  20                         clock-latency = <1000>;
  21                         cpu0-supply = <&regulator_vccpint>;
  22                         operating-points = <
  23                                 /* kHz    uV */
  24                                 666667  1000000
  25                                 333334  1000000
  26                         >;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a9";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                         clocks = <&clkc 3>;
  34                 };
  35         };
  36
  37         fpga_full: fpga-full {
  38                 compatible = "fpga-region";
  39                 fpga-mgr = <&devcfg>;
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 ranges;
  43         };
  44
  45         pmu@f8891000 {
  46                 compatible = "arm,cortex-a9-pmu";
  47                 interrupts = <0 5 4>, <0 6 4>;
  48                 interrupt-parent = <&intc>;
  49                 reg = <0xf8891000 0x1000>,
  50                       <0xf8893000 0x1000>;
  51         };
  52
  53         regulator_vccpint: fixedregulator {
  54                 compatible = "regulator-fixed";
  55                 regulator-name = "VCCPINT";
  56                 regulator-min-microvolt = <1000000>;
  57                 regulator-max-microvolt = <1000000>;
  58                 regulator-boot-on;
  59                 regulator-always-on;
  60         };
  61
  62         amba: amba {
  63                 u-boot,dm-pre-reloc;
  64                 compatible = "simple-bus";
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 interrupt-parent = <&intc>;
  68                 ranges;
  69
  70                 adc: adc@f8007100 {
  71                         compatible = "xlnx,zynq-xadc-1.00.a";
  72                         reg = <0xf8007100 0x20>;
  73                         interrupts = <0 7 4>;
  74                         interrupt-parent = <&intc>;
  75                         clocks = <&clkc 12>;
  76                 };
  77
  78                 can0: can@e0008000 {
  79                         compatible = "xlnx,zynq-can-1.0";
  80                         status = "disabled";
  81                         clocks = <&clkc 19>, <&clkc 36>;
  82                         clock-names = "can_clk", "pclk";
  83                         reg = <0xe0008000 0x1000>;
  84                         interrupts = <0 28 4>;
  85                         interrupt-parent = <&intc>;
  86                         tx-fifo-depth = <0x40>;
  87                         rx-fifo-depth = <0x40>;
  88                 };
  89
  90                 can1: can@e0009000 {
  91                         compatible = "xlnx,zynq-can-1.0";
  92                         status = "disabled";
  93                         clocks = <&clkc 20>, <&clkc 37>;
  94                         clock-names = "can_clk", "pclk";
  95                         reg = <0xe0009000 0x1000>;
  96                         interrupts = <0 51 4>;
  97                         interrupt-parent = <&intc>;
  98                         tx-fifo-depth = <0x40>;
  99                         rx-fifo-depth = <0x40>;
 100                 };
 101
 102                 gpio0: gpio@e000a000 {
 103                         compatible = "xlnx,zynq-gpio-1.0";
 104                         #gpio-cells = <2>;
 105                         clocks = <&clkc 42>;
 106                         gpio-controller;
 107                         interrupt-controller;
 108                         #interrupt-cells = <2>;
 109                         interrupt-parent = <&intc>;
 110                         interrupts = <0 20 4>;
 111                         reg = <0xe000a000 0x1000>;
 112                 };
 113
 114                 i2c0: i2c@e0004000 {
 115                         compatible = "cdns,i2c-r1p10";
 116                         status = "disabled";
 117                         clocks = <&clkc 38>;
 118                         interrupt-parent = <&intc>;
 119                         interrupts = <0 25 4>;
 120                         reg = <0xe0004000 0x1000>;
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                 };
 124
 125                 i2c1: i2c@e0005000 {
 126                         compatible = "cdns,i2c-r1p10";
 127                         status = "disabled";
 128                         clocks = <&clkc 39>;
 129                         interrupt-parent = <&intc>;
 130                         interrupts = <0 48 4>;
 131                         reg = <0xe0005000 0x1000>;
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134                 };
 135
 136                 intc: interrupt-controller@f8f01000 {
 137                         compatible = "arm,cortex-a9-gic";
 138                         #interrupt-cells = <3>;
 139                         interrupt-controller;
 140                         reg = <0xF8F01000 0x1000>,
 141                               <0xF8F00100 0x100>;
 142                 };
 143
 144                 L2: cache-controller@f8f02000 {
 145                         compatible = "arm,pl310-cache";
 146                         reg = <0xF8F02000 0x1000>;
 147                         interrupts = <0 2 4>;
 148                         arm,data-latency = <3 2 2>;
 149                         arm,tag-latency = <2 2 2>;
 150                         cache-unified;
 151                         cache-level = <2>;
 152                 };
 153
 154                 mc: memory-controller@f8006000 {
 155                         compatible = "xlnx,zynq-ddrc-a05";
 156                         reg = <0xf8006000 0x1000>;
 157                 };
 158
 159                 ocmc: ocmc@f800c000 {
 160                         compatible = "xlnx,zynq-ocmc-1.0";
 161                         interrupt-parent = <&intc>;
 162                         interrupts = <0 3 4>;
 163                         reg = <0xf800c000 0x1000>;
 164                 };
 165
 166                 uart0: serial@e0000000 {
 167                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 168                         status = "disabled";
 169                         clocks = <&clkc 23>, <&clkc 40>;
 170                         clock-names = "uart_clk", "pclk";
 171                         reg = <0xE0000000 0x1000>;
 172                         interrupts = <0 27 4>;
 173                 };
 174
 175                 uart1: serial@e0001000 {
 176                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 177                         status = "disabled";
 178                         clocks = <&clkc 24>, <&clkc 41>;
 179                         clock-names = "uart_clk", "pclk";
 180                         reg = <0xE0001000 0x1000>;
 181                         interrupts = <0 50 4>;
 182                 };
 183
 184                 spi0: spi@e0006000 {
 185                         compatible = "xlnx,zynq-spi-r1p6";
 186                         reg = <0xe0006000 0x1000>;
 187                         status = "disabled";
 188                         interrupt-parent = <&intc>;
 189                         interrupts = <0 26 4>;
 190                         clocks = <&clkc 25>, <&clkc 34>;
 191                         clock-names = "ref_clk", "pclk";
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                 };
 195
 196                 spi1: spi@e0007000 {
 197                         compatible = "xlnx,zynq-spi-r1p6";
 198                         reg = <0xe0007000 0x1000>;
 199                         status = "disabled";
 200                         interrupt-parent = <&intc>;
 201                         interrupts = <0 49 4>;
 202                         clocks = <&clkc 26>, <&clkc 35>;
 203                         clock-names = "ref_clk", "pclk";
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                 };
 207
 208                 qspi: spi@e000d000 {
 209                         clock-names = "ref_clk", "pclk";
 210                         clocks = <&clkc 10>, <&clkc 43>;
 211                         compatible = "xlnx,zynq-qspi-1.0";
 212                         status = "disabled";
 213                         interrupt-parent = <&intc>;
 214                         interrupts = <0 19 4>;
 215                         reg = <0xe000d000 0x1000>;
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                 };
 219
 220                 smcc: memory-controller@e000e000 {
 221                         #address-cells = <1>;
 222                         #size-cells = <1>;
 223                         status = "disabled";
 224                         clock-names = "memclk", "apb_pclk";
 225                         clocks = <&clkc 11>, <&clkc 44>;
 226                         compatible = "arm,pl353-smc-r2p1", "arm,primecell";
 227                         interrupt-parent = <&intc>;
 228                         interrupts = <0 18 4>;
 229                         ranges ;
 230                         reg = <0xe000e000 0x1000>;
 231                         nand0: flash@e1000000 {
 232                                 status = "disabled";
 233                                 compatible = "arm,pl353-nand-r2p1";
 234                                 reg = <0xe1000000 0x1000000>;
 235                                 #address-cells = <0x1>;
 236                                 #size-cells = <0x1>;
 237                         };
 238                         nor0: flash@e2000000 {
 239                                 status = "disabled";
 240                                 compatible = "cfi-flash";
 241                                 reg = <0xe2000000 0x2000000>;
 242                                 #address-cells = <1>;
 243                                 #size-cells = <1>;
 244                         };
 245                 };
 246
 247                 gem0: ethernet@e000b000 {
 248                         compatible = "cdns,zynq-gem", "cdns,gem";
 249                         reg = <0xe000b000 0x1000>;
 250                         status = "disabled";
 251                         interrupts = <0 22 4>;
 252                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 253                         clock-names = "pclk", "hclk", "tx_clk";
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                 };
 257
 258                 gem1: ethernet@e000c000 {
 259                         compatible = "cdns,zynq-gem", "cdns,gem";
 260                         reg = <0xe000c000 0x1000>;
 261                         status = "disabled";
 262                         interrupts = <0 45 4>;
 263                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 264                         clock-names = "pclk", "hclk", "tx_clk";
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                 };
 268
 269                 sdhci0: mmc@e0100000 {
 270                         compatible = "arasan,sdhci-8.9a";
 271                         status = "disabled";
 272                         clock-names = "clk_xin", "clk_ahb";
 273                         clocks = <&clkc 21>, <&clkc 32>;
 274                         interrupt-parent = <&intc>;
 275                         interrupts = <0 24 4>;
 276                         reg = <0xe0100000 0x1000>;
 277                 };
 278
 279                 sdhci1: mmc@e0101000 {
 280                         compatible = "arasan,sdhci-8.9a";
 281                         status = "disabled";
 282                         clock-names = "clk_xin", "clk_ahb";
 283                         clocks = <&clkc 22>, <&clkc 33>;
 284                         interrupt-parent = <&intc>;
 285                         interrupts = <0 47 4>;
 286                         reg = <0xe0101000 0x1000>;
 287                 };
 288
 289                 slcr: slcr@f8000000 {
 290                         u-boot,dm-pre-reloc;
 291                         #address-cells = <1>;
 292                         #size-cells = <1>;
 293                         compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 294                         reg = <0xF8000000 0x1000>;
 295                         ranges;
 296                         clkc: clkc@100 {
 297                                 u-boot,dm-pre-reloc;
 298                                 #clock-cells = <1>;
 299                                 compatible = "xlnx,ps7-clkc";
 300                                 fclk-enable = <0xf>;
 301                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 302                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 303                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 304                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 305                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 306                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 307                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
 308                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 309                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 310                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 311                                                 "dbg_trc", "dbg_apb";
 312                                 reg = <0x100 0x100>;
 313                         };
 314
 315                         rstc: rstc@200 {
 316                                 compatible = "xlnx,zynq-reset";
 317                                 reg = <0x200 0x48>;
 318                                 #reset-cells = <1>;
 319                                 syscon = <&slcr>;
 320                         };
 321
 322                         pinctrl0: pinctrl@700 {
 323                                 compatible = "xlnx,pinctrl-zynq";
 324                                 reg = <0x700 0x200>;
 325                                 syscon = <&slcr>;
 326                         };
 327                 };
 328
 329                 dmac_s: dmac@f8003000 {
 330                         compatible = "arm,pl330", "arm,primecell";
 331                         reg = <0xf8003000 0x1000>;
 332                         interrupt-parent = <&intc>;
 333                         interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
 334                                 "dma4", "dma5", "dma6", "dma7";
 335                         interrupts = <0 13 4>,
 336                                      <0 14 4>, <0 15 4>,
 337                                      <0 16 4>, <0 17 4>,
 338                                      <0 40 4>, <0 41 4>,
 339                                      <0 42 4>, <0 43 4>;
 340                         #dma-cells = <1>;
 341                         #dma-channels = <8>;
 342                         #dma-requests = <4>;
 343                         clocks = <&clkc 27>;
 344                         clock-names = "apb_pclk";
 345                 };
 346
 347                 devcfg: devcfg@f8007000 {
 348                         compatible = "xlnx,zynq-devcfg-1.0";
 349                         interrupt-parent = <&intc>;
 350                         interrupts = <0 8 4>;
 351                         reg = <0xf8007000 0x100>;
 352                         clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
 353                         clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
 354                         syscon = <&slcr>;
 355                 };
 356
 357                 efuse: efuse@f800d000 {
 358                         compatible = "xlnx,zynq-efuse";
 359                         reg = <0xf800d000 0x20>;
 360                 };
 361
 362                 global_timer: timer@f8f00200 {
 363                         compatible = "arm,cortex-a9-global-timer";
 364                         reg = <0xf8f00200 0x20>;
 365                         interrupts = <1 11 0x301>;
 366                         interrupt-parent = <&intc>;
 367                         clocks = <&clkc 4>;
 368                 };
 369
 370                 ttc0: timer@f8001000 {
 371                         interrupt-parent = <&intc>;
 372                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
 373                         compatible = "cdns,ttc";
 374                         clocks = <&clkc 6>;
 375                         reg = <0xF8001000 0x1000>;
 376                 };
 377
 378                 ttc1: timer@f8002000 {
 379                         interrupt-parent = <&intc>;
 380                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
 381                         compatible = "cdns,ttc";
 382                         clocks = <&clkc 6>;
 383                         reg = <0xF8002000 0x1000>;
 384                 };
 385
 386                 scutimer: timer@f8f00600 {
 387                         interrupt-parent = <&intc>;
 388                         interrupts = <1 13 0x301>;
 389                         compatible = "arm,cortex-a9-twd-timer";
 390                         reg = <0xf8f00600 0x20>;
 391                         clocks = <&clkc 4>;
 392                 };
 393
 394                 usb0: usb@e0002000 {
 395                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 396                         status = "disabled";
 397                         clocks = <&clkc 28>;
 398                         interrupt-parent = <&intc>;
 399                         interrupts = <0 21 4>;
 400                         reg = <0xe0002000 0x1000>;
 401                         phy_type = "ulpi";
 402                 };
 403
 404                 usb1: usb@e0003000 {
 405                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 406                         status = "disabled";
 407                         clocks = <&clkc 29>;
 408                         interrupt-parent = <&intc>;
 409                         interrupts = <0 44 4>;
 410                         reg = <0xe0003000 0x1000>;
 411                         phy_type = "ulpi";
 412                 };
 413
 414                 watchdog0: watchdog@f8005000 {
 415                         clocks = <&clkc 45>;
 416                         compatible = "cdns,wdt-r1p2";
 417                         interrupt-parent = <&intc>;
 418                         interrupts = <0 9 1>;
 419                         reg = <0xf8005000 0x1000>;
 420                         timeout-sec = <10>;
 421                 };
 422         };
 423 };