2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/kdb.h>
39 #include <linux/uaccess.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/timer.h>
52 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
54 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
57 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
60 * Here we define the default xmit fifo size used for each type of UART.
62 static const struct serial8250_config uart_config[] = {
87 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
88 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
89 .rxtrig_bytes = {1, 4, 8, 14},
90 .flags = UART_CAP_FIFO,
101 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
107 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
109 .rxtrig_bytes = {8, 16, 24, 28},
110 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
116 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
118 .rxtrig_bytes = {1, 16, 32, 56},
119 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
127 .name = "16C950/954",
130 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
131 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
132 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
138 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
140 .rxtrig_bytes = {8, 16, 56, 60},
141 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
147 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
148 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
154 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
155 .flags = UART_CAP_FIFO,
161 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
162 .flags = UART_CAP_FIFO | UART_NATSEMI,
168 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
169 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
175 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
176 .flags = UART_CAP_FIFO,
182 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
183 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
190 .flags = UART_CAP_FIFO | UART_CAP_AFE,
196 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
198 .rxtrig_bytes = {1, 4, 8, 14},
199 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
205 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
206 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
213 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
215 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
222 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
223 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
224 .flags = UART_CAP_FIFO,
226 [PORT_BRCM_TRUMANAGE] = {
230 .flags = UART_CAP_HFIFO,
235 [PORT_ALTR_16550_F32] = {
236 .name = "Altera 16550 FIFO32",
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_AFE,
242 [PORT_ALTR_16550_F64] = {
243 .name = "Altera 16550 FIFO64",
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO | UART_CAP_AFE,
249 [PORT_ALTR_16550_F128] = {
250 .name = "Altera 16550 FIFO128",
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
257 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
258 * workaround of errata A-008006 which states that tx_loadsz should
259 * be configured less than Maximum supported fifo bytes.
261 [PORT_16550A_FSL64] = {
262 .name = "16550A_FSL64",
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
267 .flags = UART_CAP_FIFO,
270 .name = "Palmchip BK-3103",
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .rxtrig_bytes = {1, 4, 8, 14},
275 .flags = UART_CAP_FIFO,
279 /* Uart divisor latch read */
280 static int default_serial_dl_read(struct uart_8250_port *up)
282 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
285 /* Uart divisor latch write */
286 static void default_serial_dl_write(struct uart_8250_port *up, int value)
288 serial_out(up, UART_DLL, value & 0xff);
289 serial_out(up, UART_DLM, value >> 8 & 0xff);
292 #ifdef CONFIG_SERIAL_8250_RT288X
294 /* Au1x00/RT288x UART hardware has a weird register layout */
295 static const s8 au_io_in_map[8] = {
303 -1, /* UART_SCR (unmapped) */
306 static const s8 au_io_out_map[8] = {
312 -1, /* UART_LSR (unmapped) */
313 -1, /* UART_MSR (unmapped) */
314 -1, /* UART_SCR (unmapped) */
317 static unsigned int au_serial_in(struct uart_port *p, int offset)
319 if (offset >= ARRAY_SIZE(au_io_in_map))
321 offset = au_io_in_map[offset];
324 return __raw_readl(p->membase + (offset << p->regshift));
327 static void au_serial_out(struct uart_port *p, int offset, int value)
329 if (offset >= ARRAY_SIZE(au_io_out_map))
331 offset = au_io_out_map[offset];
334 __raw_writel(value, p->membase + (offset << p->regshift));
337 /* Au1x00 haven't got a standard divisor latch */
338 static int au_serial_dl_read(struct uart_8250_port *up)
340 return __raw_readl(up->port.membase + 0x28);
343 static void au_serial_dl_write(struct uart_8250_port *up, int value)
345 __raw_writel(value, up->port.membase + 0x28);
350 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
352 offset = offset << p->regshift;
353 outb(p->hub6 - 1 + offset, p->iobase);
354 return inb(p->iobase + 1);
357 static void hub6_serial_out(struct uart_port *p, int offset, int value)
359 offset = offset << p->regshift;
360 outb(p->hub6 - 1 + offset, p->iobase);
361 outb(value, p->iobase + 1);
364 static unsigned int mem_serial_in(struct uart_port *p, int offset)
366 offset = offset << p->regshift;
367 return readb(p->membase + offset);
370 static void mem_serial_out(struct uart_port *p, int offset, int value)
372 offset = offset << p->regshift;
373 writeb(value, p->membase + offset);
376 static void mem16_serial_out(struct uart_port *p, int offset, int value)
378 offset = offset << p->regshift;
379 writew(value, p->membase + offset);
382 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
384 offset = offset << p->regshift;
385 return readw(p->membase + offset);
388 static void mem32_serial_out(struct uart_port *p, int offset, int value)
390 offset = offset << p->regshift;
391 writel(value, p->membase + offset);
394 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
396 offset = offset << p->regshift;
397 return readl(p->membase + offset);
400 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
402 offset = offset << p->regshift;
403 iowrite32be(value, p->membase + offset);
406 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
408 offset = offset << p->regshift;
409 return ioread32be(p->membase + offset);
412 static unsigned int io_serial_in(struct uart_port *p, int offset)
414 offset = offset << p->regshift;
415 return inb(p->iobase + offset);
418 static void io_serial_out(struct uart_port *p, int offset, int value)
420 offset = offset << p->regshift;
421 outb(value, p->iobase + offset);
424 static int serial8250_default_handle_irq(struct uart_port *port);
425 static int exar_handle_irq(struct uart_port *port);
427 static void set_io_from_upio(struct uart_port *p)
429 struct uart_8250_port *up = up_to_u8250p(p);
431 up->dl_read = default_serial_dl_read;
432 up->dl_write = default_serial_dl_write;
436 p->serial_in = hub6_serial_in;
437 p->serial_out = hub6_serial_out;
441 p->serial_in = mem_serial_in;
442 p->serial_out = mem_serial_out;
446 p->serial_in = mem16_serial_in;
447 p->serial_out = mem16_serial_out;
451 p->serial_in = mem32_serial_in;
452 p->serial_out = mem32_serial_out;
456 p->serial_in = mem32be_serial_in;
457 p->serial_out = mem32be_serial_out;
460 #ifdef CONFIG_SERIAL_8250_RT288X
462 p->serial_in = au_serial_in;
463 p->serial_out = au_serial_out;
464 up->dl_read = au_serial_dl_read;
465 up->dl_write = au_serial_dl_write;
470 p->serial_in = io_serial_in;
471 p->serial_out = io_serial_out;
474 /* Remember loaded iotype */
475 up->cur_iotype = p->iotype;
476 p->handle_irq = serial8250_default_handle_irq;
480 serial_port_out_sync(struct uart_port *p, int offset, int value)
488 p->serial_out(p, offset, value);
489 p->serial_in(p, UART_LCR); /* safe, no side-effects */
492 p->serial_out(p, offset, value);
499 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
501 serial_out(up, UART_SCR, offset);
502 serial_out(up, UART_ICR, value);
505 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
509 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
510 serial_out(up, UART_SCR, offset);
511 value = serial_in(up, UART_ICR);
512 serial_icr_write(up, UART_ACR, up->acr);
520 static void serial8250_clear_fifos(struct uart_8250_port *p)
522 if (p->capabilities & UART_CAP_FIFO) {
523 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
524 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
525 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
526 serial_out(p, UART_FCR, 0);
530 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
532 unsigned char mcr = serial8250_in_MCR(p);
534 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
537 mcr &= ~UART_MCR_RTS;
538 serial8250_out_MCR(p, mcr);
541 static void serial8250_em485_handle_start_tx(unsigned long arg);
542 static void serial8250_em485_handle_stop_tx(unsigned long arg);
544 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
546 serial8250_clear_fifos(p);
547 serial_out(p, UART_FCR, p->fcr);
549 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
551 void serial8250_rpm_get(struct uart_8250_port *p)
553 if (!(p->capabilities & UART_CAP_RPM))
555 pm_runtime_get_sync(p->port.dev);
557 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
559 void serial8250_rpm_put(struct uart_8250_port *p)
561 if (!(p->capabilities & UART_CAP_RPM))
563 pm_runtime_mark_last_busy(p->port.dev);
564 pm_runtime_put_autosuspend(p->port.dev);
566 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
569 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
570 * @p: uart_8250_port port instance
572 * The function is used to start rs485 software emulating on the
573 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
574 * transmission. The function is idempotent, so it is safe to call it
577 * The caller MUST enable interrupt on empty shift register before
578 * calling serial8250_em485_init(). This interrupt is not a part of
579 * 8250 standard, but implementation defined.
581 * The function is supposed to be called from .rs485_config callback
582 * or from any other callback protected with p->port.lock spinlock.
584 * See also serial8250_em485_destroy()
586 * Return 0 - success, -errno - otherwise
588 int serial8250_em485_init(struct uart_8250_port *p)
593 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
597 setup_timer(&p->em485->stop_tx_timer,
598 serial8250_em485_handle_stop_tx, (unsigned long)p);
599 setup_timer(&p->em485->start_tx_timer,
600 serial8250_em485_handle_start_tx, (unsigned long)p);
601 p->em485->active_timer = NULL;
603 serial8250_em485_rts_after_send(p);
607 EXPORT_SYMBOL_GPL(serial8250_em485_init);
610 * serial8250_em485_destroy() - put uart_8250_port into normal state
611 * @p: uart_8250_port port instance
613 * The function is used to stop rs485 software emulating on the
614 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
615 * call it multiple times.
617 * The function is supposed to be called from .rs485_config callback
618 * or from any other callback protected with p->port.lock spinlock.
620 * See also serial8250_em485_init()
622 void serial8250_em485_destroy(struct uart_8250_port *p)
627 del_timer(&p->em485->start_tx_timer);
628 del_timer(&p->em485->stop_tx_timer);
633 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
636 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
637 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
638 * empty and the HW can idle again.
640 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
642 unsigned char rpm_active;
644 if (!(p->capabilities & UART_CAP_RPM))
647 rpm_active = xchg(&p->rpm_tx_active, 1);
650 pm_runtime_get_sync(p->port.dev);
653 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
655 unsigned char rpm_active;
657 if (!(p->capabilities & UART_CAP_RPM))
660 rpm_active = xchg(&p->rpm_tx_active, 0);
663 pm_runtime_mark_last_busy(p->port.dev);
664 pm_runtime_put_autosuspend(p->port.dev);
668 * IER sleep support. UARTs which have EFRs need the "extended
669 * capability" bit enabled. Note that on XR16C850s, we need to
670 * reset LCR to write to IER.
672 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
674 unsigned char lcr = 0, efr = 0;
676 * Exar UARTs have a SLEEP register that enables or disables
677 * each UART to enter sleep mode separately. On the XR17V35x the
678 * register is accessible to each UART at the UART_EXAR_SLEEP
679 * offset but the UART channel may only write to the corresponding
682 serial8250_rpm_get(p);
683 if ((p->port.type == PORT_XR17V35X) ||
684 (p->port.type == PORT_XR17D15X)) {
685 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
689 if (p->capabilities & UART_CAP_SLEEP) {
690 if (p->capabilities & UART_CAP_EFR) {
691 lcr = serial_in(p, UART_LCR);
692 efr = serial_in(p, UART_EFR);
693 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
694 serial_out(p, UART_EFR, UART_EFR_ECB);
695 serial_out(p, UART_LCR, 0);
697 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
698 if (p->capabilities & UART_CAP_EFR) {
699 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
700 serial_out(p, UART_EFR, efr);
701 serial_out(p, UART_LCR, lcr);
705 serial8250_rpm_put(p);
708 #ifdef CONFIG_SERIAL_8250_RSA
710 * Attempts to turn on the RSA FIFO. Returns zero on failure.
711 * We set the port uart clock rate if we succeed.
713 static int __enable_rsa(struct uart_8250_port *up)
718 mode = serial_in(up, UART_RSA_MSR);
719 result = mode & UART_RSA_MSR_FIFO;
722 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
723 mode = serial_in(up, UART_RSA_MSR);
724 result = mode & UART_RSA_MSR_FIFO;
728 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
733 static void enable_rsa(struct uart_8250_port *up)
735 if (up->port.type == PORT_RSA) {
736 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
737 spin_lock_irq(&up->port.lock);
739 spin_unlock_irq(&up->port.lock);
741 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
742 serial_out(up, UART_RSA_FRR, 0);
747 * Attempts to turn off the RSA FIFO. Returns zero on failure.
748 * It is unknown why interrupts were disabled in here. However,
749 * the caller is expected to preserve this behaviour by grabbing
750 * the spinlock before calling this function.
752 static void disable_rsa(struct uart_8250_port *up)
757 if (up->port.type == PORT_RSA &&
758 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
759 spin_lock_irq(&up->port.lock);
761 mode = serial_in(up, UART_RSA_MSR);
762 result = !(mode & UART_RSA_MSR_FIFO);
765 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
766 mode = serial_in(up, UART_RSA_MSR);
767 result = !(mode & UART_RSA_MSR_FIFO);
771 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
772 spin_unlock_irq(&up->port.lock);
775 #endif /* CONFIG_SERIAL_8250_RSA */
778 * This is a quickie test to see how big the FIFO is.
779 * It doesn't work at all the time, more's the pity.
781 static int size_fifo(struct uart_8250_port *up)
783 unsigned char old_fcr, old_mcr, old_lcr;
784 unsigned short old_dl;
787 old_lcr = serial_in(up, UART_LCR);
788 serial_out(up, UART_LCR, 0);
789 old_fcr = serial_in(up, UART_FCR);
790 old_mcr = serial8250_in_MCR(up);
791 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
792 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
793 serial8250_out_MCR(up, UART_MCR_LOOP);
794 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
795 old_dl = serial_dl_read(up);
796 serial_dl_write(up, 0x0001);
797 serial_out(up, UART_LCR, 0x03);
798 for (count = 0; count < 256; count++)
799 serial_out(up, UART_TX, count);
800 mdelay(20);/* FIXME - schedule_timeout */
801 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
802 (count < 256); count++)
803 serial_in(up, UART_RX);
804 serial_out(up, UART_FCR, old_fcr);
805 serial8250_out_MCR(up, old_mcr);
806 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
807 serial_dl_write(up, old_dl);
808 serial_out(up, UART_LCR, old_lcr);
814 * Read UART ID using the divisor method - set DLL and DLM to zero
815 * and the revision will be in DLL and device type in DLM. We
816 * preserve the device state across this.
818 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
820 unsigned char old_lcr;
821 unsigned int id, old_dl;
823 old_lcr = serial_in(p, UART_LCR);
824 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
825 old_dl = serial_dl_read(p);
826 serial_dl_write(p, 0);
827 id = serial_dl_read(p);
828 serial_dl_write(p, old_dl);
830 serial_out(p, UART_LCR, old_lcr);
836 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
837 * When this function is called we know it is at least a StarTech
838 * 16650 V2, but it might be one of several StarTech UARTs, or one of
839 * its clones. (We treat the broken original StarTech 16650 V1 as a
840 * 16550, and why not? Startech doesn't seem to even acknowledge its
843 * What evil have men's minds wrought...
845 static void autoconfig_has_efr(struct uart_8250_port *up)
847 unsigned int id1, id2, id3, rev;
850 * Everything with an EFR has SLEEP
852 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
855 * First we check to see if it's an Oxford Semiconductor UART.
857 * If we have to do this here because some non-National
858 * Semiconductor clone chips lock up if you try writing to the
859 * LSR register (which serial_icr_read does)
863 * Check for Oxford Semiconductor 16C950.
865 * EFR [4] must be set else this test fails.
867 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
868 * claims that it's needed for 952 dual UART's (which are not
869 * recommended for new designs).
872 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
873 serial_out(up, UART_EFR, UART_EFR_ECB);
874 serial_out(up, UART_LCR, 0x00);
875 id1 = serial_icr_read(up, UART_ID1);
876 id2 = serial_icr_read(up, UART_ID2);
877 id3 = serial_icr_read(up, UART_ID3);
878 rev = serial_icr_read(up, UART_REV);
880 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
882 if (id1 == 0x16 && id2 == 0xC9 &&
883 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
884 up->port.type = PORT_16C950;
887 * Enable work around for the Oxford Semiconductor 952 rev B
888 * chip which causes it to seriously miscalculate baud rates
891 if (id3 == 0x52 && rev == 0x01)
892 up->bugs |= UART_BUG_QUOT;
897 * We check for a XR16C850 by setting DLL and DLM to 0, and then
898 * reading back DLL and DLM. The chip type depends on the DLM
900 * 0x10 - XR16C850 and the DLL contains the chip revision.
904 id1 = autoconfig_read_divisor_id(up);
905 DEBUG_AUTOCONF("850id=%04x ", id1);
908 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
909 up->port.type = PORT_16850;
914 * It wasn't an XR16C850.
916 * We distinguish between the '654 and the '650 by counting
917 * how many bytes are in the FIFO. I'm using this for now,
918 * since that's the technique that was sent to me in the
919 * serial driver update, but I'm not convinced this works.
920 * I've had problems doing this in the past. -TYT
922 if (size_fifo(up) == 64)
923 up->port.type = PORT_16654;
925 up->port.type = PORT_16650V2;
929 * We detected a chip without a FIFO. Only two fall into
930 * this category - the original 8250 and the 16450. The
931 * 16450 has a scratch register (accessible with LCR=0)
933 static void autoconfig_8250(struct uart_8250_port *up)
935 unsigned char scratch, status1, status2;
937 up->port.type = PORT_8250;
939 scratch = serial_in(up, UART_SCR);
940 serial_out(up, UART_SCR, 0xa5);
941 status1 = serial_in(up, UART_SCR);
942 serial_out(up, UART_SCR, 0x5a);
943 status2 = serial_in(up, UART_SCR);
944 serial_out(up, UART_SCR, scratch);
946 if (status1 == 0xa5 && status2 == 0x5a)
947 up->port.type = PORT_16450;
950 static int broken_efr(struct uart_8250_port *up)
953 * Exar ST16C2550 "A2" devices incorrectly detect as
954 * having an EFR, and report an ID of 0x0201. See
955 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
957 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
964 * We know that the chip has FIFOs. Does it have an EFR? The
965 * EFR is located in the same register position as the IIR and
966 * we know the top two bits of the IIR are currently set. The
967 * EFR should contain zero. Try to read the EFR.
969 static void autoconfig_16550a(struct uart_8250_port *up)
971 unsigned char status1, status2;
972 unsigned int iersave;
974 up->port.type = PORT_16550A;
975 up->capabilities |= UART_CAP_FIFO;
978 * XR17V35x UARTs have an extra divisor register, DLD
979 * that gets enabled with when DLAB is set which will
980 * cause the device to incorrectly match and assign
981 * port type to PORT_16650. The EFR for this UART is
982 * found at offset 0x09. Instead check the Deice ID (DVID)
983 * register for a 2, 4 or 8 port UART.
985 if (up->port.flags & UPF_EXAR_EFR) {
986 status1 = serial_in(up, UART_EXAR_DVID);
987 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
988 DEBUG_AUTOCONF("Exar XR17V35x ");
989 up->port.type = PORT_XR17V35X;
990 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
999 * Check for presence of the EFR when DLAB is set.
1000 * Only ST16C650V1 UARTs pass this test.
1002 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1003 if (serial_in(up, UART_EFR) == 0) {
1004 serial_out(up, UART_EFR, 0xA8);
1005 if (serial_in(up, UART_EFR) != 0) {
1006 DEBUG_AUTOCONF("EFRv1 ");
1007 up->port.type = PORT_16650;
1008 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1010 serial_out(up, UART_LCR, 0);
1011 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1013 status1 = serial_in(up, UART_IIR) >> 5;
1014 serial_out(up, UART_FCR, 0);
1015 serial_out(up, UART_LCR, 0);
1018 up->port.type = PORT_16550A_FSL64;
1020 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1022 serial_out(up, UART_EFR, 0);
1027 * Maybe it requires 0xbf to be written to the LCR.
1028 * (other ST16C650V2 UARTs, TI16C752A, etc)
1030 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1031 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1032 DEBUG_AUTOCONF("EFRv2 ");
1033 autoconfig_has_efr(up);
1038 * Check for a National Semiconductor SuperIO chip.
1039 * Attempt to switch to bank 2, read the value of the LOOP bit
1040 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1041 * switch back to bank 2, read it from EXCR1 again and check
1042 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1044 serial_out(up, UART_LCR, 0);
1045 status1 = serial8250_in_MCR(up);
1046 serial_out(up, UART_LCR, 0xE0);
1047 status2 = serial_in(up, 0x02); /* EXCR1 */
1049 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1050 serial_out(up, UART_LCR, 0);
1051 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1052 serial_out(up, UART_LCR, 0xE0);
1053 status2 = serial_in(up, 0x02); /* EXCR1 */
1054 serial_out(up, UART_LCR, 0);
1055 serial8250_out_MCR(up, status1);
1057 if ((status2 ^ status1) & UART_MCR_LOOP) {
1058 unsigned short quot;
1060 serial_out(up, UART_LCR, 0xE0);
1062 quot = serial_dl_read(up);
1065 if (ns16550a_goto_highspeed(up))
1066 serial_dl_write(up, quot);
1068 serial_out(up, UART_LCR, 0);
1070 up->port.uartclk = 921600*16;
1071 up->port.type = PORT_NS16550A;
1072 up->capabilities |= UART_NATSEMI;
1078 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1079 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1080 * Try setting it with and without DLAB set. Cheap clones
1081 * set bit 5 without DLAB set.
1083 serial_out(up, UART_LCR, 0);
1084 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1085 status1 = serial_in(up, UART_IIR) >> 5;
1086 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1087 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1089 status2 = serial_in(up, UART_IIR) >> 5;
1090 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1091 serial_out(up, UART_LCR, 0);
1093 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1095 if (status1 == 6 && status2 == 7) {
1096 up->port.type = PORT_16750;
1097 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1102 * Try writing and reading the UART_IER_UUE bit (b6).
1103 * If it works, this is probably one of the Xscale platform's
1105 * We're going to explicitly set the UUE bit to 0 before
1106 * trying to write and read a 1 just to make sure it's not
1107 * already a 1 and maybe locked there before we even start start.
1109 iersave = serial_in(up, UART_IER);
1110 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1111 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1113 * OK it's in a known zero state, try writing and reading
1114 * without disturbing the current state of the other bits.
1116 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1117 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1120 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1122 DEBUG_AUTOCONF("Xscale ");
1123 up->port.type = PORT_XSCALE;
1124 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1129 * If we got here we couldn't force the IER_UUE bit to 0.
1130 * Log it and continue.
1132 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1134 serial_out(up, UART_IER, iersave);
1137 * Exar uarts have EFR in a weird location
1139 if (up->port.flags & UPF_EXAR_EFR) {
1140 DEBUG_AUTOCONF("Exar XR17D15x ");
1141 up->port.type = PORT_XR17D15X;
1142 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1149 * We distinguish between 16550A and U6 16550A by counting
1150 * how many bytes are in the FIFO.
1152 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1153 up->port.type = PORT_U6_16550A;
1154 up->capabilities |= UART_CAP_AFE;
1159 * This routine is called by rs_init() to initialize a specific serial
1160 * port. It determines what type of UART chip this serial port is
1161 * using: 8250, 16450, 16550, 16550A. The important question is
1162 * whether or not this UART is a 16550A or not, since this will
1163 * determine whether or not we can use its FIFO features or not.
1165 static void autoconfig(struct uart_8250_port *up)
1167 unsigned char status1, scratch, scratch2, scratch3;
1168 unsigned char save_lcr, save_mcr;
1169 struct uart_port *port = &up->port;
1170 unsigned long flags;
1171 unsigned int old_capabilities;
1173 if (!port->iobase && !port->mapbase && !port->membase)
1176 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1177 serial_index(port), port->iobase, port->membase);
1180 * We really do need global IRQs disabled here - we're going to
1181 * be frobbing the chips IRQ enable register to see if it exists.
1183 spin_lock_irqsave(&port->lock, flags);
1185 up->capabilities = 0;
1188 if (!(port->flags & UPF_BUGGY_UART)) {
1190 * Do a simple existence test first; if we fail this,
1191 * there's no point trying anything else.
1193 * 0x80 is used as a nonsense port to prevent against
1194 * false positives due to ISA bus float. The
1195 * assumption is that 0x80 is a non-existent port;
1196 * which should be safe since include/asm/io.h also
1197 * makes this assumption.
1199 * Note: this is safe as long as MCR bit 4 is clear
1200 * and the device is in "PC" mode.
1202 scratch = serial_in(up, UART_IER);
1203 serial_out(up, UART_IER, 0);
1208 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1209 * 16C754B) allow only to modify them if an EFR bit is set.
1211 scratch2 = serial_in(up, UART_IER) & 0x0f;
1212 serial_out(up, UART_IER, 0x0F);
1216 scratch3 = serial_in(up, UART_IER) & 0x0f;
1217 serial_out(up, UART_IER, scratch);
1218 if (scratch2 != 0 || scratch3 != 0x0F) {
1220 * We failed; there's nothing here
1222 spin_unlock_irqrestore(&port->lock, flags);
1223 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1224 scratch2, scratch3);
1229 save_mcr = serial8250_in_MCR(up);
1230 save_lcr = serial_in(up, UART_LCR);
1233 * Check to see if a UART is really there. Certain broken
1234 * internal modems based on the Rockwell chipset fail this
1235 * test, because they apparently don't implement the loopback
1236 * test mode. So this test is skipped on the COM 1 through
1237 * COM 4 ports. This *should* be safe, since no board
1238 * manufacturer would be stupid enough to design a board
1239 * that conflicts with COM 1-4 --- we hope!
1241 if (!(port->flags & UPF_SKIP_TEST)) {
1242 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1243 status1 = serial_in(up, UART_MSR) & 0xF0;
1244 serial8250_out_MCR(up, save_mcr);
1245 if (status1 != 0x90) {
1246 spin_unlock_irqrestore(&port->lock, flags);
1247 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1254 * We're pretty sure there's a port here. Lets find out what
1255 * type of port it is. The IIR top two bits allows us to find
1256 * out if it's 8250 or 16450, 16550, 16550A or later. This
1257 * determines what we test for next.
1259 * We also initialise the EFR (if any) to zero for later. The
1260 * EFR occupies the same register location as the FCR and IIR.
1262 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1263 serial_out(up, UART_EFR, 0);
1264 serial_out(up, UART_LCR, 0);
1266 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1267 scratch = serial_in(up, UART_IIR) >> 6;
1271 autoconfig_8250(up);
1274 port->type = PORT_UNKNOWN;
1277 port->type = PORT_16550;
1280 autoconfig_16550a(up);
1284 #ifdef CONFIG_SERIAL_8250_RSA
1286 * Only probe for RSA ports if we got the region.
1288 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1290 port->type = PORT_RSA;
1293 serial_out(up, UART_LCR, save_lcr);
1295 port->fifosize = uart_config[up->port.type].fifo_size;
1296 old_capabilities = up->capabilities;
1297 up->capabilities = uart_config[port->type].flags;
1298 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1300 if (port->type == PORT_UNKNOWN)
1306 #ifdef CONFIG_SERIAL_8250_RSA
1307 if (port->type == PORT_RSA)
1308 serial_out(up, UART_RSA_FRR, 0);
1310 serial8250_out_MCR(up, save_mcr);
1311 serial8250_clear_fifos(up);
1312 serial_in(up, UART_RX);
1313 if (up->capabilities & UART_CAP_UUE)
1314 serial_out(up, UART_IER, UART_IER_UUE);
1316 serial_out(up, UART_IER, 0);
1319 spin_unlock_irqrestore(&port->lock, flags);
1322 * Check if the device is a Fintek F81216A
1324 if (port->type == PORT_16550A)
1325 fintek_8250_probe(up);
1327 if (up->capabilities != old_capabilities) {
1328 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1329 serial_index(port), old_capabilities,
1333 DEBUG_AUTOCONF("iir=%d ", scratch);
1334 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1337 static void autoconfig_irq(struct uart_8250_port *up)
1339 struct uart_port *port = &up->port;
1340 unsigned char save_mcr, save_ier;
1341 unsigned char save_ICP = 0;
1342 unsigned int ICP = 0;
1346 if (port->flags & UPF_FOURPORT) {
1347 ICP = (port->iobase & 0xfe0) | 0x1f;
1348 save_ICP = inb_p(ICP);
1353 if (uart_console(port))
1356 /* forget possible initially masked and pending IRQ */
1357 probe_irq_off(probe_irq_on());
1358 save_mcr = serial8250_in_MCR(up);
1359 save_ier = serial_in(up, UART_IER);
1360 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1362 irqs = probe_irq_on();
1363 serial8250_out_MCR(up, 0);
1365 if (port->flags & UPF_FOURPORT) {
1366 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1368 serial8250_out_MCR(up,
1369 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1371 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1372 serial_in(up, UART_LSR);
1373 serial_in(up, UART_RX);
1374 serial_in(up, UART_IIR);
1375 serial_in(up, UART_MSR);
1376 serial_out(up, UART_TX, 0xFF);
1378 irq = probe_irq_off(irqs);
1380 serial8250_out_MCR(up, save_mcr);
1381 serial_out(up, UART_IER, save_ier);
1383 if (port->flags & UPF_FOURPORT)
1384 outb_p(save_ICP, ICP);
1386 if (uart_console(port))
1389 port->irq = (irq > 0) ? irq : 0;
1392 static void serial8250_stop_rx(struct uart_port *port)
1394 struct uart_8250_port *up = up_to_u8250p(port);
1396 serial8250_rpm_get(up);
1398 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1399 up->port.read_status_mask &= ~UART_LSR_DR;
1400 serial_port_out(port, UART_IER, up->ier);
1402 serial8250_rpm_put(up);
1405 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1407 serial8250_em485_rts_after_send(p);
1410 * Empty the RX FIFO, we are not interested in anything
1411 * received during the half-duplex transmission.
1412 * Enable previously disabled RX interrupts.
1414 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1415 serial8250_clear_fifos(p);
1417 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1418 serial_port_out(&p->port, UART_IER, p->ier);
1422 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1424 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1425 struct uart_8250_em485 *em485 = p->em485;
1426 unsigned long flags;
1428 serial8250_rpm_get(p);
1429 spin_lock_irqsave(&p->port.lock, flags);
1431 em485->active_timer == &em485->stop_tx_timer) {
1432 __do_stop_tx_rs485(p);
1433 em485->active_timer = NULL;
1435 spin_unlock_irqrestore(&p->port.lock, flags);
1436 serial8250_rpm_put(p);
1439 static void __stop_tx_rs485(struct uart_8250_port *p)
1441 struct uart_8250_em485 *em485 = p->em485;
1444 * __do_stop_tx_rs485 is going to set RTS according to config
1445 * AND flush RX FIFO if required.
1447 if (p->port.rs485.delay_rts_after_send > 0) {
1448 em485->active_timer = &em485->stop_tx_timer;
1449 mod_timer(&em485->stop_tx_timer, jiffies +
1450 p->port.rs485.delay_rts_after_send * HZ / 1000);
1452 __do_stop_tx_rs485(p);
1456 static inline void __do_stop_tx(struct uart_8250_port *p)
1458 if (p->ier & UART_IER_THRI) {
1459 p->ier &= ~UART_IER_THRI;
1460 serial_out(p, UART_IER, p->ier);
1461 serial8250_rpm_put_tx(p);
1465 static inline void __stop_tx(struct uart_8250_port *p)
1467 struct uart_8250_em485 *em485 = p->em485;
1470 unsigned char lsr = serial_in(p, UART_LSR);
1472 * To provide required timeing and allow FIFO transfer,
1473 * __stop_tx_rs485() must be called only when both FIFO and
1474 * shift register are empty. It is for device driver to enable
1475 * interrupt on TEMT.
1477 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1480 del_timer(&em485->start_tx_timer);
1481 em485->active_timer = NULL;
1488 static void serial8250_stop_tx(struct uart_port *port)
1490 struct uart_8250_port *up = up_to_u8250p(port);
1492 serial8250_rpm_get(up);
1496 * We really want to stop the transmitter from sending.
1498 if (port->type == PORT_16C950) {
1499 up->acr |= UART_ACR_TXDIS;
1500 serial_icr_write(up, UART_ACR, up->acr);
1502 serial8250_rpm_put(up);
1505 static inline void __start_tx(struct uart_port *port)
1507 struct uart_8250_port *up = up_to_u8250p(port);
1509 if (up->dma && !up->dma->tx_dma(up))
1512 if (!(up->ier & UART_IER_THRI)) {
1513 up->ier |= UART_IER_THRI;
1514 serial_port_out(port, UART_IER, up->ier);
1516 if (up->bugs & UART_BUG_TXEN) {
1519 lsr = serial_in(up, UART_LSR);
1520 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1521 if (lsr & UART_LSR_THRE)
1522 serial8250_tx_chars(up);
1527 * Re-enable the transmitter if we disabled it.
1529 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1530 up->acr &= ~UART_ACR_TXDIS;
1531 serial_icr_write(up, UART_ACR, up->acr);
1535 static inline void start_tx_rs485(struct uart_port *port)
1537 struct uart_8250_port *up = up_to_u8250p(port);
1538 struct uart_8250_em485 *em485 = up->em485;
1541 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1542 serial8250_stop_rx(&up->port);
1544 del_timer(&em485->stop_tx_timer);
1545 em485->active_timer = NULL;
1547 mcr = serial8250_in_MCR(up);
1548 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1549 !!(mcr & UART_MCR_RTS)) {
1550 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1551 mcr |= UART_MCR_RTS;
1553 mcr &= ~UART_MCR_RTS;
1554 serial8250_out_MCR(up, mcr);
1556 if (up->port.rs485.delay_rts_before_send > 0) {
1557 em485->active_timer = &em485->start_tx_timer;
1558 mod_timer(&em485->start_tx_timer, jiffies +
1559 up->port.rs485.delay_rts_before_send * HZ / 1000);
1567 static void serial8250_em485_handle_start_tx(unsigned long arg)
1569 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1570 struct uart_8250_em485 *em485 = p->em485;
1571 unsigned long flags;
1573 spin_lock_irqsave(&p->port.lock, flags);
1575 em485->active_timer == &em485->start_tx_timer) {
1576 __start_tx(&p->port);
1577 em485->active_timer = NULL;
1579 spin_unlock_irqrestore(&p->port.lock, flags);
1582 static void serial8250_start_tx(struct uart_port *port)
1584 struct uart_8250_port *up = up_to_u8250p(port);
1585 struct uart_8250_em485 *em485 = up->em485;
1587 serial8250_rpm_get_tx(up);
1590 em485->active_timer == &em485->start_tx_timer)
1594 start_tx_rs485(port);
1599 static void serial8250_throttle(struct uart_port *port)
1601 port->throttle(port);
1604 static void serial8250_unthrottle(struct uart_port *port)
1606 port->unthrottle(port);
1609 static void serial8250_disable_ms(struct uart_port *port)
1611 struct uart_8250_port *up = up_to_u8250p(port);
1613 /* no MSR capabilities */
1614 if (up->bugs & UART_BUG_NOMSR)
1617 up->ier &= ~UART_IER_MSI;
1618 serial_port_out(port, UART_IER, up->ier);
1621 static void serial8250_enable_ms(struct uart_port *port)
1623 struct uart_8250_port *up = up_to_u8250p(port);
1625 /* no MSR capabilities */
1626 if (up->bugs & UART_BUG_NOMSR)
1629 up->ier |= UART_IER_MSI;
1631 serial8250_rpm_get(up);
1632 serial_port_out(port, UART_IER, up->ier);
1633 serial8250_rpm_put(up);
1636 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1638 struct uart_port *port = &up->port;
1640 char flag = TTY_NORMAL;
1642 if (likely(lsr & UART_LSR_DR))
1643 ch = serial_in(up, UART_RX);
1646 * Intel 82571 has a Serial Over Lan device that will
1647 * set UART_LSR_BI without setting UART_LSR_DR when
1648 * it receives a break. To avoid reading from the
1649 * receive buffer without UART_LSR_DR bit set, we
1650 * just force the read character to be 0
1656 lsr |= up->lsr_saved_flags;
1657 up->lsr_saved_flags = 0;
1659 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1660 if (lsr & UART_LSR_BI) {
1661 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1664 * We do the SysRQ and SAK checking
1665 * here because otherwise the break
1666 * may get masked by ignore_status_mask
1667 * or read_status_mask.
1669 if (uart_handle_break(port))
1671 } else if (lsr & UART_LSR_PE)
1672 port->icount.parity++;
1673 else if (lsr & UART_LSR_FE)
1674 port->icount.frame++;
1675 if (lsr & UART_LSR_OE)
1676 port->icount.overrun++;
1679 * Mask off conditions which should be ignored.
1681 lsr &= port->read_status_mask;
1683 if (lsr & UART_LSR_BI) {
1684 pr_debug("%s: handling break\n", __func__);
1686 } else if (lsr & UART_LSR_PE)
1688 else if (lsr & UART_LSR_FE)
1691 if (uart_handle_sysrq_char(port, ch))
1694 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1698 * serial8250_rx_chars: processes according to the passed in LSR
1699 * value, and returns the remaining LSR bits not handled
1700 * by this Rx routine.
1702 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1704 struct uart_port *port = &up->port;
1705 int max_count = 256;
1708 serial8250_read_char(up, lsr);
1709 if (--max_count == 0)
1711 lsr = serial_in(up, UART_LSR);
1712 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1714 tty_flip_buffer_push(&port->state->port);
1717 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1719 void serial8250_tx_chars(struct uart_8250_port *up)
1721 struct uart_port *port = &up->port;
1722 struct circ_buf *xmit = &port->state->xmit;
1726 serial_out(up, UART_TX, port->x_char);
1731 if (uart_tx_stopped(port)) {
1732 serial8250_stop_tx(port);
1735 if (uart_circ_empty(xmit)) {
1740 count = up->tx_loadsz;
1742 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1743 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1745 if (uart_circ_empty(xmit))
1747 if ((up->capabilities & UART_CAP_HFIFO) &&
1748 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1750 } while (--count > 0);
1752 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1753 uart_write_wakeup(port);
1755 pr_debug("%s: THRE\n", __func__);
1758 * With RPM enabled, we have to wait until the FIFO is empty before the
1759 * HW can go idle. So we get here once again with empty FIFO and disable
1760 * the interrupt and RPM in __stop_tx()
1762 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1765 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1767 /* Caller holds uart port lock */
1768 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1770 struct uart_port *port = &up->port;
1771 unsigned int status = serial_in(up, UART_MSR);
1773 status |= up->msr_saved_flags;
1774 up->msr_saved_flags = 0;
1775 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1776 port->state != NULL) {
1777 if (status & UART_MSR_TERI)
1779 if (status & UART_MSR_DDSR)
1781 if (status & UART_MSR_DDCD)
1782 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1783 if (status & UART_MSR_DCTS)
1784 uart_handle_cts_change(port, status & UART_MSR_CTS);
1786 wake_up_interruptible(&port->state->port.delta_msr_wait);
1791 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1793 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1795 switch (iir & 0x3f) {
1796 case UART_IIR_RX_TIMEOUT:
1797 serial8250_rx_dma_flush(up);
1802 return up->dma->rx_dma(up);
1806 * This handles the interrupt from one port.
1808 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1810 unsigned char status;
1811 unsigned long flags;
1812 struct uart_8250_port *up = up_to_u8250p(port);
1814 if (iir & UART_IIR_NO_INT)
1817 spin_lock_irqsave(&port->lock, flags);
1819 status = serial_port_in(port, UART_LSR);
1821 pr_debug("%s: status = %x\n", __func__, status);
1823 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1824 if (!up->dma || handle_rx_dma(up, iir))
1825 status = serial8250_rx_chars(up, status);
1827 serial8250_modem_status(up);
1828 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
1829 serial8250_tx_chars(up);
1831 spin_unlock_irqrestore(&port->lock, flags);
1834 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1836 static int serial8250_default_handle_irq(struct uart_port *port)
1838 struct uart_8250_port *up = up_to_u8250p(port);
1842 serial8250_rpm_get(up);
1844 iir = serial_port_in(port, UART_IIR);
1845 ret = serial8250_handle_irq(port, iir);
1847 serial8250_rpm_put(up);
1852 * These Exar UARTs have an extra interrupt indicator that could
1853 * fire for a few unimplemented interrupts. One of which is a
1854 * wakeup event when coming out of sleep. Put this here just
1855 * to be on the safe side that these interrupts don't go unhandled.
1857 static int exar_handle_irq(struct uart_port *port)
1859 unsigned int iir = serial_port_in(port, UART_IIR);
1862 ret = serial8250_handle_irq(port, iir);
1864 if ((port->type == PORT_XR17V35X) ||
1865 (port->type == PORT_XR17D15X)) {
1866 serial_port_in(port, 0x80);
1867 serial_port_in(port, 0x81);
1868 serial_port_in(port, 0x82);
1869 serial_port_in(port, 0x83);
1876 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1877 * have a programmable TX threshold that triggers the THRE interrupt in
1878 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1879 * has space available. Load it up with tx_loadsz bytes.
1881 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1883 unsigned long flags;
1884 unsigned int iir = serial_port_in(port, UART_IIR);
1886 /* TX Threshold IRQ triggered so load up FIFO */
1887 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1888 struct uart_8250_port *up = up_to_u8250p(port);
1890 spin_lock_irqsave(&port->lock, flags);
1891 serial8250_tx_chars(up);
1892 spin_unlock_irqrestore(&port->lock, flags);
1895 iir = serial_port_in(port, UART_IIR);
1896 return serial8250_handle_irq(port, iir);
1899 static unsigned int serial8250_tx_empty(struct uart_port *port)
1901 struct uart_8250_port *up = up_to_u8250p(port);
1902 unsigned long flags;
1905 serial8250_rpm_get(up);
1907 spin_lock_irqsave(&port->lock, flags);
1908 lsr = serial_port_in(port, UART_LSR);
1909 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1910 spin_unlock_irqrestore(&port->lock, flags);
1912 serial8250_rpm_put(up);
1914 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1917 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1919 struct uart_8250_port *up = up_to_u8250p(port);
1920 unsigned int status;
1923 serial8250_rpm_get(up);
1924 status = serial8250_modem_status(up);
1925 serial8250_rpm_put(up);
1928 if (status & UART_MSR_DCD)
1930 if (status & UART_MSR_RI)
1932 if (status & UART_MSR_DSR)
1934 if (status & UART_MSR_CTS)
1938 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1940 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1942 if (port->get_mctrl)
1943 return port->get_mctrl(port);
1944 return serial8250_do_get_mctrl(port);
1947 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1949 struct uart_8250_port *up = up_to_u8250p(port);
1950 unsigned char mcr = 0;
1952 if (mctrl & TIOCM_RTS)
1953 mcr |= UART_MCR_RTS;
1954 if (mctrl & TIOCM_DTR)
1955 mcr |= UART_MCR_DTR;
1956 if (mctrl & TIOCM_OUT1)
1957 mcr |= UART_MCR_OUT1;
1958 if (mctrl & TIOCM_OUT2)
1959 mcr |= UART_MCR_OUT2;
1960 if (mctrl & TIOCM_LOOP)
1961 mcr |= UART_MCR_LOOP;
1963 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1965 serial8250_out_MCR(up, mcr);
1967 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1969 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1971 if (port->set_mctrl)
1972 port->set_mctrl(port, mctrl);
1974 serial8250_do_set_mctrl(port, mctrl);
1977 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1979 struct uart_8250_port *up = up_to_u8250p(port);
1980 unsigned long flags;
1982 serial8250_rpm_get(up);
1983 spin_lock_irqsave(&port->lock, flags);
1984 if (break_state == -1)
1985 up->lcr |= UART_LCR_SBC;
1987 up->lcr &= ~UART_LCR_SBC;
1988 serial_port_out(port, UART_LCR, up->lcr);
1989 spin_unlock_irqrestore(&port->lock, flags);
1990 serial8250_rpm_put(up);
1994 * Wait for transmitter & holding register to empty
1996 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1998 unsigned int status, tmout = 10000;
2000 /* Wait up to 10ms for the character(s) to be sent. */
2002 status = serial_in(up, UART_LSR);
2004 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2006 if ((status & bits) == bits)
2011 touch_nmi_watchdog();
2014 /* Wait up to 1s for flow control if necessary */
2015 if (up->port.flags & UPF_CONS_FLOW) {
2016 for (tmout = 1000000; tmout; tmout--) {
2017 unsigned int msr = serial_in(up, UART_MSR);
2018 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2019 if (msr & UART_MSR_CTS)
2022 touch_nmi_watchdog();
2027 #ifdef CONFIG_CONSOLE_POLL
2029 * Console polling routines for writing and reading from the uart while
2030 * in an interrupt or debug context.
2033 static int serial8250_get_poll_char(struct uart_port *port)
2035 struct uart_8250_port *up = up_to_u8250p(port);
2039 serial8250_rpm_get(up);
2041 lsr = serial_port_in(port, UART_LSR);
2043 if (!(lsr & UART_LSR_DR)) {
2044 status = NO_POLL_CHAR;
2048 status = serial_port_in(port, UART_RX);
2050 serial8250_rpm_put(up);
2055 static void serial8250_put_poll_char(struct uart_port *port,
2059 struct uart_8250_port *up = up_to_u8250p(port);
2061 serial8250_rpm_get(up);
2063 * First save the IER then disable the interrupts
2065 ier = serial_port_in(port, UART_IER);
2066 if (up->capabilities & UART_CAP_UUE)
2067 serial_port_out(port, UART_IER, UART_IER_UUE);
2069 serial_port_out(port, UART_IER, 0);
2071 wait_for_xmitr(up, BOTH_EMPTY);
2073 * Send the character out.
2075 serial_port_out(port, UART_TX, c);
2078 * Finally, wait for transmitter to become empty
2079 * and restore the IER
2081 wait_for_xmitr(up, BOTH_EMPTY);
2082 serial_port_out(port, UART_IER, ier);
2083 serial8250_rpm_put(up);
2086 #endif /* CONFIG_CONSOLE_POLL */
2088 int serial8250_do_startup(struct uart_port *port)
2090 struct uart_8250_port *up = up_to_u8250p(port);
2091 unsigned long flags;
2092 unsigned char lsr, iir;
2095 if (!port->fifosize)
2096 port->fifosize = uart_config[port->type].fifo_size;
2098 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2099 if (!up->capabilities)
2100 up->capabilities = uart_config[port->type].flags;
2103 if (port->iotype != up->cur_iotype)
2104 set_io_from_upio(port);
2106 serial8250_rpm_get(up);
2107 if (port->type == PORT_16C950) {
2108 /* Wake up and initialize UART */
2110 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2111 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2112 serial_port_out(port, UART_IER, 0);
2113 serial_port_out(port, UART_LCR, 0);
2114 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2115 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2116 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2117 serial_port_out(port, UART_LCR, 0);
2120 #ifdef CONFIG_SERIAL_8250_RSA
2122 * If this is an RSA port, see if we can kick it up to the
2123 * higher speed clock.
2128 if (port->type == PORT_XR17V35X) {
2130 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2131 * MCR [7:5] and MSR [7:0]
2133 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2136 * Make sure all interrups are masked until initialization is
2137 * complete and the FIFOs are cleared
2139 serial_port_out(port, UART_IER, 0);
2143 * Clear the FIFO buffers and disable them.
2144 * (they will be reenabled in set_termios())
2146 serial8250_clear_fifos(up);
2149 * Clear the interrupt registers.
2151 serial_port_in(port, UART_LSR);
2152 serial_port_in(port, UART_RX);
2153 serial_port_in(port, UART_IIR);
2154 serial_port_in(port, UART_MSR);
2157 * At this point, there's no way the LSR could still be 0xff;
2158 * if it is, then bail out, because there's likely no UART
2161 if (!(port->flags & UPF_BUGGY_UART) &&
2162 (serial_port_in(port, UART_LSR) == 0xff)) {
2163 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2164 serial_index(port));
2170 * For a XR16C850, we need to set the trigger levels
2172 if (port->type == PORT_16850) {
2175 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2177 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2178 serial_port_out(port, UART_FCTR,
2179 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2180 serial_port_out(port, UART_TRG, UART_TRG_96);
2181 serial_port_out(port, UART_FCTR,
2182 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2183 serial_port_out(port, UART_TRG, UART_TRG_96);
2185 serial_port_out(port, UART_LCR, 0);
2189 * For the Altera 16550 variants, set TX threshold trigger level.
2191 if (((port->type == PORT_ALTR_16550_F32) ||
2192 (port->type == PORT_ALTR_16550_F64) ||
2193 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2194 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2195 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2196 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2197 serial_index(port));
2199 serial_port_out(port, UART_ALTR_AFR,
2200 UART_ALTR_EN_TXFIFO_LW);
2201 serial_port_out(port, UART_ALTR_TX_LOW,
2202 port->fifosize - up->tx_loadsz);
2203 port->handle_irq = serial8250_tx_threshold_handle_irq;
2210 * Test for UARTs that do not reassert THRE when the
2211 * transmitter is idle and the interrupt has already
2212 * been cleared. Real 16550s should always reassert
2213 * this interrupt whenever the transmitter is idle and
2214 * the interrupt is enabled. Delays are necessary to
2215 * allow register changes to become visible.
2217 spin_lock_irqsave(&port->lock, flags);
2218 if (up->port.irqflags & IRQF_SHARED)
2219 disable_irq_nosync(port->irq);
2221 wait_for_xmitr(up, UART_LSR_THRE);
2222 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2223 udelay(1); /* allow THRE to set */
2224 iir1 = serial_port_in(port, UART_IIR);
2225 serial_port_out(port, UART_IER, 0);
2226 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2227 udelay(1); /* allow a working UART time to re-assert THRE */
2228 iir = serial_port_in(port, UART_IIR);
2229 serial_port_out(port, UART_IER, 0);
2231 if (port->irqflags & IRQF_SHARED)
2232 enable_irq(port->irq);
2233 spin_unlock_irqrestore(&port->lock, flags);
2236 * If the interrupt is not reasserted, or we otherwise
2237 * don't trust the iir, setup a timer to kick the UART
2238 * on a regular basis.
2240 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2241 up->port.flags & UPF_BUG_THRE) {
2242 up->bugs |= UART_BUG_THRE;
2246 retval = up->ops->setup_irq(up);
2251 * Now, initialize the UART
2253 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2255 spin_lock_irqsave(&port->lock, flags);
2256 if (up->port.flags & UPF_FOURPORT) {
2258 up->port.mctrl |= TIOCM_OUT1;
2261 * Most PC uarts need OUT2 raised to enable interrupts.
2264 up->port.mctrl |= TIOCM_OUT2;
2266 serial8250_set_mctrl(port, port->mctrl);
2269 * Serial over Lan (SoL) hack:
2270 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2271 * used for Serial Over Lan. Those chips take a longer time than a
2272 * normal serial device to signalize that a transmission data was
2273 * queued. Due to that, the above test generally fails. One solution
2274 * would be to delay the reading of iir. However, this is not
2275 * reliable, since the timeout is variable. So, let's just don't
2276 * test if we receive TX irq. This way, we'll never enable
2279 if (up->port.flags & UPF_NO_TXEN_TEST)
2280 goto dont_test_tx_en;
2283 * Do a quick test to see if we receive an interrupt when we enable
2286 serial_port_out(port, UART_IER, UART_IER_THRI);
2287 lsr = serial_port_in(port, UART_LSR);
2288 iir = serial_port_in(port, UART_IIR);
2289 serial_port_out(port, UART_IER, 0);
2291 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2292 if (!(up->bugs & UART_BUG_TXEN)) {
2293 up->bugs |= UART_BUG_TXEN;
2294 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2295 serial_index(port));
2298 up->bugs &= ~UART_BUG_TXEN;
2302 spin_unlock_irqrestore(&port->lock, flags);
2305 * Clear the interrupt registers again for luck, and clear the
2306 * saved flags to avoid getting false values from polling
2307 * routines or the previous session.
2309 serial_port_in(port, UART_LSR);
2310 serial_port_in(port, UART_RX);
2311 serial_port_in(port, UART_IIR);
2312 serial_port_in(port, UART_MSR);
2313 up->lsr_saved_flags = 0;
2314 up->msr_saved_flags = 0;
2317 * Request DMA channels for both RX and TX.
2320 retval = serial8250_request_dma(up);
2322 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2323 serial_index(port));
2329 * Set the IER shadow for rx interrupts but defer actual interrupt
2330 * enable until after the FIFOs are enabled; otherwise, an already-
2331 * active sender can swamp the interrupt handler with "too much work".
2333 up->ier = UART_IER_RLSI | UART_IER_RDI;
2335 if (port->flags & UPF_FOURPORT) {
2338 * Enable interrupts on the AST Fourport board
2340 icp = (port->iobase & 0xfe0) | 0x01f;
2346 serial8250_rpm_put(up);
2349 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2351 static int serial8250_startup(struct uart_port *port)
2354 return port->startup(port);
2355 return serial8250_do_startup(port);
2358 void serial8250_do_shutdown(struct uart_port *port)
2360 struct uart_8250_port *up = up_to_u8250p(port);
2361 unsigned long flags;
2363 serial8250_rpm_get(up);
2365 * Disable interrupts from this port
2367 spin_lock_irqsave(&port->lock, flags);
2369 serial_port_out(port, UART_IER, 0);
2370 spin_unlock_irqrestore(&port->lock, flags);
2372 synchronize_irq(port->irq);
2375 serial8250_release_dma(up);
2377 spin_lock_irqsave(&port->lock, flags);
2378 if (port->flags & UPF_FOURPORT) {
2379 /* reset interrupts on the AST Fourport board */
2380 inb((port->iobase & 0xfe0) | 0x1f);
2381 port->mctrl |= TIOCM_OUT1;
2383 port->mctrl &= ~TIOCM_OUT2;
2385 serial8250_set_mctrl(port, port->mctrl);
2386 spin_unlock_irqrestore(&port->lock, flags);
2389 * Disable break condition and FIFOs
2391 serial_port_out(port, UART_LCR,
2392 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2393 serial8250_clear_fifos(up);
2395 #ifdef CONFIG_SERIAL_8250_RSA
2397 * Reset the RSA board back to 115kbps compat mode.
2403 * Read data port to reset things, and then unlink from
2406 serial_port_in(port, UART_RX);
2407 serial8250_rpm_put(up);
2409 up->ops->release_irq(up);
2411 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2413 static void serial8250_shutdown(struct uart_port *port)
2416 port->shutdown(port);
2418 serial8250_do_shutdown(port);
2422 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2423 * Calculate divisor with extra 4-bit fractional portion
2425 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2429 struct uart_port *port = &up->port;
2430 unsigned int quot_16;
2432 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2433 *frac = quot_16 & 0x0f;
2435 return quot_16 >> 4;
2438 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2442 struct uart_port *port = &up->port;
2446 * Handle magic divisors for baud rates above baud_base on
2447 * SMSC SuperIO chips.
2450 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2451 baud == (port->uartclk/4))
2453 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2454 baud == (port->uartclk/8))
2456 else if (up->port.type == PORT_XR17V35X)
2457 quot = xr17v35x_get_divisor(up, baud, frac);
2459 quot = uart_get_divisor(port, baud);
2462 * Oxford Semi 952 rev B workaround
2464 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2470 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2475 switch (c_cflag & CSIZE) {
2477 cval = UART_LCR_WLEN5;
2480 cval = UART_LCR_WLEN6;
2483 cval = UART_LCR_WLEN7;
2487 cval = UART_LCR_WLEN8;
2491 if (c_cflag & CSTOPB)
2492 cval |= UART_LCR_STOP;
2493 if (c_cflag & PARENB) {
2494 cval |= UART_LCR_PARITY;
2495 if (up->bugs & UART_BUG_PARITY)
2496 up->fifo_bug = true;
2498 if (!(c_cflag & PARODD))
2499 cval |= UART_LCR_EPAR;
2501 if (c_cflag & CMSPAR)
2502 cval |= UART_LCR_SPAR;
2508 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2509 unsigned int quot, unsigned int quot_frac)
2511 struct uart_8250_port *up = up_to_u8250p(port);
2513 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2514 if (is_omap1510_8250(up)) {
2515 if (baud == 115200) {
2517 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2519 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2523 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2524 * otherwise just set DLAB
2526 if (up->capabilities & UART_NATSEMI)
2527 serial_port_out(port, UART_LCR, 0xe0);
2529 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2531 serial_dl_write(up, quot);
2533 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2534 if (up->port.type == PORT_XR17V35X)
2535 serial_port_out(port, 0x2, quot_frac);
2538 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2539 struct ktermios *termios,
2540 struct ktermios *old)
2543 * Ask the core to calculate the divisor for us.
2544 * Allow 1% tolerance at the upper limit so uart clks marginally
2545 * slower than nominal still match standard baud rates without
2546 * causing transmission errors.
2548 return uart_get_baud_rate(port, termios, old,
2549 port->uartclk / 16 / 0xffff,
2554 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2555 struct ktermios *old)
2557 struct uart_8250_port *up = up_to_u8250p(port);
2559 unsigned long flags;
2560 unsigned int baud, quot, frac = 0;
2562 cval = serial8250_compute_lcr(up, termios->c_cflag);
2564 baud = serial8250_get_baud_rate(port, termios, old);
2565 quot = serial8250_get_divisor(up, baud, &frac);
2568 * Ok, we're now changing the port state. Do it with
2569 * interrupts disabled.
2571 serial8250_rpm_get(up);
2572 spin_lock_irqsave(&port->lock, flags);
2574 up->lcr = cval; /* Save computed LCR */
2576 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2577 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2578 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2579 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2580 up->fcr |= UART_FCR_TRIGGER_1;
2585 * MCR-based auto flow control. When AFE is enabled, RTS will be
2586 * deasserted when the receive FIFO contains more characters than
2587 * the trigger, or the MCR RTS bit is cleared.
2589 if (up->capabilities & UART_CAP_AFE) {
2590 up->mcr &= ~UART_MCR_AFE;
2591 if (termios->c_cflag & CRTSCTS)
2592 up->mcr |= UART_MCR_AFE;
2596 * Update the per-port timeout.
2598 uart_update_timeout(port, termios->c_cflag, baud);
2600 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2601 if (termios->c_iflag & INPCK)
2602 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2603 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2604 port->read_status_mask |= UART_LSR_BI;
2607 * Characteres to ignore
2609 port->ignore_status_mask = 0;
2610 if (termios->c_iflag & IGNPAR)
2611 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2612 if (termios->c_iflag & IGNBRK) {
2613 port->ignore_status_mask |= UART_LSR_BI;
2615 * If we're ignoring parity and break indicators,
2616 * ignore overruns too (for real raw support).
2618 if (termios->c_iflag & IGNPAR)
2619 port->ignore_status_mask |= UART_LSR_OE;
2623 * ignore all characters if CREAD is not set
2625 if ((termios->c_cflag & CREAD) == 0)
2626 port->ignore_status_mask |= UART_LSR_DR;
2629 * CTS flow control flag and modem status interrupts
2631 up->ier &= ~UART_IER_MSI;
2632 if (!(up->bugs & UART_BUG_NOMSR) &&
2633 UART_ENABLE_MS(&up->port, termios->c_cflag))
2634 up->ier |= UART_IER_MSI;
2635 if (up->capabilities & UART_CAP_UUE)
2636 up->ier |= UART_IER_UUE;
2637 if (up->capabilities & UART_CAP_RTOIE)
2638 up->ier |= UART_IER_RTOIE;
2640 serial_port_out(port, UART_IER, up->ier);
2642 if (up->capabilities & UART_CAP_EFR) {
2643 unsigned char efr = 0;
2645 * TI16C752/Startech hardware flow control. FIXME:
2646 * - TI16C752 requires control thresholds to be set.
2647 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2649 if (termios->c_cflag & CRTSCTS)
2650 efr |= UART_EFR_CTS;
2652 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2653 if (port->flags & UPF_EXAR_EFR)
2654 serial_port_out(port, UART_XR_EFR, efr);
2656 serial_port_out(port, UART_EFR, efr);
2659 serial8250_set_divisor(port, baud, quot, frac);
2662 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2663 * is written without DLAB set, this mode will be disabled.
2665 if (port->type == PORT_16750)
2666 serial_port_out(port, UART_FCR, up->fcr);
2668 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2669 if (port->type != PORT_16750) {
2670 /* emulated UARTs (Lucent Venus 167x) need two steps */
2671 if (up->fcr & UART_FCR_ENABLE_FIFO)
2672 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2673 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2675 serial8250_set_mctrl(port, port->mctrl);
2676 spin_unlock_irqrestore(&port->lock, flags);
2677 serial8250_rpm_put(up);
2679 /* Don't rewrite B0 */
2680 if (tty_termios_baud_rate(termios))
2681 tty_termios_encode_baud_rate(termios, baud, baud);
2683 EXPORT_SYMBOL(serial8250_do_set_termios);
2686 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2687 struct ktermios *old)
2689 if (port->set_termios)
2690 port->set_termios(port, termios, old);
2692 serial8250_do_set_termios(port, termios, old);
2696 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2698 if (termios->c_line == N_PPS) {
2699 port->flags |= UPF_HARDPPS_CD;
2700 spin_lock_irq(&port->lock);
2701 serial8250_enable_ms(port);
2702 spin_unlock_irq(&port->lock);
2704 port->flags &= ~UPF_HARDPPS_CD;
2705 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2706 spin_lock_irq(&port->lock);
2707 serial8250_disable_ms(port);
2708 spin_unlock_irq(&port->lock);
2714 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2715 unsigned int oldstate)
2717 struct uart_8250_port *p = up_to_u8250p(port);
2719 serial8250_set_sleep(p, state != 0);
2721 EXPORT_SYMBOL(serial8250_do_pm);
2724 serial8250_pm(struct uart_port *port, unsigned int state,
2725 unsigned int oldstate)
2728 port->pm(port, state, oldstate);
2730 serial8250_do_pm(port, state, oldstate);
2733 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2735 if (pt->port.mapsize)
2736 return pt->port.mapsize;
2737 if (pt->port.iotype == UPIO_AU) {
2738 if (pt->port.type == PORT_RT2880)
2742 if (is_omap1_8250(pt))
2743 return 0x16 << pt->port.regshift;
2745 return 8 << pt->port.regshift;
2749 * Resource handling.
2751 static int serial8250_request_std_resource(struct uart_8250_port *up)
2753 unsigned int size = serial8250_port_size(up);
2754 struct uart_port *port = &up->port;
2757 switch (port->iotype) {
2767 if (!request_mem_region(port->mapbase, size, "serial")) {
2772 if (port->flags & UPF_IOREMAP) {
2773 port->membase = ioremap_nocache(port->mapbase, size);
2774 if (!port->membase) {
2775 release_mem_region(port->mapbase, size);
2783 if (!request_region(port->iobase, size, "serial"))
2790 static void serial8250_release_std_resource(struct uart_8250_port *up)
2792 unsigned int size = serial8250_port_size(up);
2793 struct uart_port *port = &up->port;
2795 switch (port->iotype) {
2805 if (port->flags & UPF_IOREMAP) {
2806 iounmap(port->membase);
2807 port->membase = NULL;
2810 release_mem_region(port->mapbase, size);
2815 release_region(port->iobase, size);
2820 static void serial8250_release_port(struct uart_port *port)
2822 struct uart_8250_port *up = up_to_u8250p(port);
2824 serial8250_release_std_resource(up);
2827 static int serial8250_request_port(struct uart_port *port)
2829 struct uart_8250_port *up = up_to_u8250p(port);
2831 return serial8250_request_std_resource(up);
2834 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2836 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2837 unsigned char bytes;
2839 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2841 return bytes ? bytes : -EOPNOTSUPP;
2844 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2846 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2849 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2852 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2853 if (bytes < conf_type->rxtrig_bytes[i])
2854 /* Use the nearest lower value */
2855 return (--i) << UART_FCR_R_TRIG_SHIFT;
2858 return UART_FCR_R_TRIG_11;
2861 static int do_get_rxtrig(struct tty_port *port)
2863 struct uart_state *state = container_of(port, struct uart_state, port);
2864 struct uart_port *uport = state->uart_port;
2865 struct uart_8250_port *up = up_to_u8250p(uport);
2867 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2870 return fcr_get_rxtrig_bytes(up);
2873 static int do_serial8250_get_rxtrig(struct tty_port *port)
2877 mutex_lock(&port->mutex);
2878 rxtrig_bytes = do_get_rxtrig(port);
2879 mutex_unlock(&port->mutex);
2881 return rxtrig_bytes;
2884 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2885 struct device_attribute *attr, char *buf)
2887 struct tty_port *port = dev_get_drvdata(dev);
2890 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2891 if (rxtrig_bytes < 0)
2892 return rxtrig_bytes;
2894 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2897 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2899 struct uart_state *state = container_of(port, struct uart_state, port);
2900 struct uart_port *uport = state->uart_port;
2901 struct uart_8250_port *up = up_to_u8250p(uport);
2904 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2908 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2912 serial8250_clear_fifos(up);
2913 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2914 up->fcr |= (unsigned char)rxtrig;
2915 serial_out(up, UART_FCR, up->fcr);
2919 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2923 mutex_lock(&port->mutex);
2924 ret = do_set_rxtrig(port, bytes);
2925 mutex_unlock(&port->mutex);
2930 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2931 struct device_attribute *attr, const char *buf, size_t count)
2933 struct tty_port *port = dev_get_drvdata(dev);
2934 unsigned char bytes;
2940 ret = kstrtou8(buf, 10, &bytes);
2944 ret = do_serial8250_set_rxtrig(port, bytes);
2951 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2952 serial8250_get_attr_rx_trig_bytes,
2953 serial8250_set_attr_rx_trig_bytes);
2955 static struct attribute *serial8250_dev_attrs[] = {
2956 &dev_attr_rx_trig_bytes.attr,
2960 static struct attribute_group serial8250_dev_attr_group = {
2961 .attrs = serial8250_dev_attrs,
2964 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2966 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2968 if (conf_type->rxtrig_bytes[0])
2969 up->port.attr_group = &serial8250_dev_attr_group;
2972 static void serial8250_config_port(struct uart_port *port, int flags)
2974 struct uart_8250_port *up = up_to_u8250p(port);
2978 * Find the region that we can probe for. This in turn
2979 * tells us whether we can probe for the type of port.
2981 ret = serial8250_request_std_resource(up);
2985 if (port->iotype != up->cur_iotype)
2986 set_io_from_upio(port);
2988 if (flags & UART_CONFIG_TYPE)
2991 /* if access method is AU, it is a 16550 with a quirk */
2992 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2993 up->bugs |= UART_BUG_NOMSR;
2995 /* HW bugs may trigger IRQ while IIR == NO_INT */
2996 if (port->type == PORT_TEGRA)
2997 up->bugs |= UART_BUG_NOMSR;
2999 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3002 if (port->type == PORT_UNKNOWN)
3003 serial8250_release_std_resource(up);
3005 /* Fixme: probably not the best place for this */
3006 if ((port->type == PORT_XR17V35X) ||
3007 (port->type == PORT_XR17D15X))
3008 port->handle_irq = exar_handle_irq;
3010 register_dev_spec_attr_grp(up);
3011 up->fcr = uart_config[up->port.type].fcr;
3015 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3017 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3018 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3019 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3020 ser->type == PORT_STARTECH)
3025 static const char *serial8250_type(struct uart_port *port)
3027 int type = port->type;
3029 if (type >= ARRAY_SIZE(uart_config))
3031 return uart_config[type].name;
3034 static const struct uart_ops serial8250_pops = {
3035 .tx_empty = serial8250_tx_empty,
3036 .set_mctrl = serial8250_set_mctrl,
3037 .get_mctrl = serial8250_get_mctrl,
3038 .stop_tx = serial8250_stop_tx,
3039 .start_tx = serial8250_start_tx,
3040 .throttle = serial8250_throttle,
3041 .unthrottle = serial8250_unthrottle,
3042 .stop_rx = serial8250_stop_rx,
3043 .enable_ms = serial8250_enable_ms,
3044 .break_ctl = serial8250_break_ctl,
3045 .startup = serial8250_startup,
3046 .shutdown = serial8250_shutdown,
3047 .set_termios = serial8250_set_termios,
3048 .set_ldisc = serial8250_set_ldisc,
3049 .pm = serial8250_pm,
3050 .type = serial8250_type,
3051 .release_port = serial8250_release_port,
3052 .request_port = serial8250_request_port,
3053 .config_port = serial8250_config_port,
3054 .verify_port = serial8250_verify_port,
3055 #ifdef CONFIG_CONSOLE_POLL
3056 .poll_get_char = serial8250_get_poll_char,
3057 .poll_put_char = serial8250_put_poll_char,
3061 void serial8250_init_port(struct uart_8250_port *up)
3063 struct uart_port *port = &up->port;
3065 spin_lock_init(&port->lock);
3066 port->ops = &serial8250_pops;
3068 up->cur_iotype = 0xFF;
3070 EXPORT_SYMBOL_GPL(serial8250_init_port);
3072 void serial8250_set_defaults(struct uart_8250_port *up)
3074 struct uart_port *port = &up->port;
3076 if (up->port.flags & UPF_FIXED_TYPE) {
3077 unsigned int type = up->port.type;
3079 if (!up->port.fifosize)
3080 up->port.fifosize = uart_config[type].fifo_size;
3082 up->tx_loadsz = uart_config[type].tx_loadsz;
3083 if (!up->capabilities)
3084 up->capabilities = uart_config[type].flags;
3087 set_io_from_upio(port);
3089 /* default dma handlers */
3091 if (!up->dma->tx_dma)
3092 up->dma->tx_dma = serial8250_tx_dma;
3093 if (!up->dma->rx_dma)
3094 up->dma->rx_dma = serial8250_rx_dma;
3097 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3099 #ifdef CONFIG_SERIAL_8250_CONSOLE
3101 static void serial8250_console_putchar(struct uart_port *port, int ch)
3103 struct uart_8250_port *up = up_to_u8250p(port);
3105 wait_for_xmitr(up, UART_LSR_THRE);
3106 serial_port_out(port, UART_TX, ch);
3110 * Restore serial console when h/w power-off detected
3112 static void serial8250_console_restore(struct uart_8250_port *up)
3114 struct uart_port *port = &up->port;
3115 struct ktermios termios;
3116 unsigned int baud, quot, frac = 0;
3118 termios.c_cflag = port->cons->cflag;
3119 if (port->state->port.tty && termios.c_cflag == 0)
3120 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3122 baud = serial8250_get_baud_rate(port, &termios, NULL);
3123 quot = serial8250_get_divisor(up, baud, &frac);
3125 serial8250_set_divisor(port, baud, quot, frac);
3126 serial_port_out(port, UART_LCR, up->lcr);
3127 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3131 * Print a string to the serial port trying not to disturb
3132 * any possible real use of the port...
3134 * The console_lock must be held when we get here.
3136 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3139 struct uart_port *port = &up->port;
3140 unsigned long flags;
3144 touch_nmi_watchdog();
3146 serial8250_rpm_get(up);
3148 if (port->sysrq || oops_in_progress)
3150 else if (in_kdb_printk())
3151 locked = spin_trylock_irqsave(&port->lock, flags);
3153 spin_lock_irqsave(&port->lock, flags);
3156 * First save the IER then disable the interrupts
3158 ier = serial_port_in(port, UART_IER);
3160 if (up->capabilities & UART_CAP_UUE)
3161 serial_port_out(port, UART_IER, UART_IER_UUE);
3163 serial_port_out(port, UART_IER, 0);
3165 /* check scratch reg to see if port powered off during system sleep */
3166 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3167 serial8250_console_restore(up);
3171 uart_console_write(port, s, count, serial8250_console_putchar);
3174 * Finally, wait for transmitter to become empty
3175 * and restore the IER
3177 wait_for_xmitr(up, BOTH_EMPTY);
3178 serial_port_out(port, UART_IER, ier);
3181 * The receive handling will happen properly because the
3182 * receive ready bit will still be set; it is not cleared
3183 * on read. However, modem control will not, we must
3184 * call it if we have saved something in the saved flags
3185 * while processing with interrupts off.
3187 if (up->msr_saved_flags)
3188 serial8250_modem_status(up);
3191 spin_unlock_irqrestore(&port->lock, flags);
3192 serial8250_rpm_put(up);
3195 static unsigned int probe_baud(struct uart_port *port)
3197 unsigned char lcr, dll, dlm;
3200 lcr = serial_port_in(port, UART_LCR);
3201 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3202 dll = serial_port_in(port, UART_DLL);
3203 dlm = serial_port_in(port, UART_DLM);
3204 serial_port_out(port, UART_LCR, lcr);
3206 quot = (dlm << 8) | dll;
3207 return (port->uartclk / 16) / quot;
3210 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3217 if (!port->iobase && !port->membase)
3221 uart_parse_options(options, &baud, &parity, &bits, &flow);
3223 baud = probe_baud(port);
3225 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3228 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3230 MODULE_LICENSE("GPL");