2 * Xilinx DRM DisplayPort encoder driver for Xilinx
4 * Copyright (C) 2014 Xilinx, Inc.
6 * Author: Hyun Woo Kwon <hyunk@xilinx.com>
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <drm/drm_crtc.h>
20 #include <drm/drm_crtc_helper.h>
21 #include <drm/drm_dp_helper.h>
22 #include <drm/drm_encoder_slave.h>
24 #include <linux/clk.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/mutex.h>
30 #include <linux/phy/phy.h>
31 #include <linux/phy/phy-zynqmp.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/uaccess.h>
36 #include "xilinx_drm_dp_sub.h"
37 #include "xilinx_drm_drv.h"
39 static uint xilinx_drm_dp_aux_timeout_ms = 50;
40 module_param_named(aux_timeout_ms, xilinx_drm_dp_aux_timeout_ms, uint, 0444);
41 MODULE_PARM_DESC(aux_timeout_ms,
42 "DP aux timeout value in msec (default: 50)");
44 static uint xilinx_drm_dp_power_on_delay_ms = 4;
45 module_param_named(power_on_delay_ms, xilinx_drm_dp_power_on_delay_ms, uint,
47 MODULE_PARM_DESC(power_on_delay,
48 "Delay after power on request in msec (default: 4)");
50 /* Link configuration registers */
51 #define XILINX_DP_TX_LINK_BW_SET 0x0
52 #define XILINX_DP_TX_LANE_CNT_SET 0x4
53 #define XILINX_DP_TX_ENHANCED_FRAME_EN 0x8
54 #define XILINX_DP_TX_TRAINING_PATTERN_SET 0xc
55 #define XILINX_DP_TX_SCRAMBLING_DISABLE 0x14
56 #define XILINX_DP_TX_DOWNSPREAD_CTL 0x18
57 #define XILINX_DP_TX_SW_RESET 0x1c
58 #define XILINX_DP_TX_SW_RESET_STREAM1 BIT(0)
59 #define XILINX_DP_TX_SW_RESET_STREAM2 BIT(1)
60 #define XILINX_DP_TX_SW_RESET_STREAM3 BIT(2)
61 #define XILINX_DP_TX_SW_RESET_STREAM4 BIT(3)
62 #define XILINX_DP_TX_SW_RESET_AUX BIT(7)
63 #define XILINX_DP_TX_SW_RESET_ALL (XILINX_DP_TX_SW_RESET_STREAM1 | \
64 XILINX_DP_TX_SW_RESET_STREAM2 | \
65 XILINX_DP_TX_SW_RESET_STREAM3 | \
66 XILINX_DP_TX_SW_RESET_STREAM4 | \
67 XILINX_DP_TX_SW_RESET_AUX)
69 /* Core enable registers */
70 #define XILINX_DP_TX_ENABLE 0x80
71 #define XILINX_DP_TX_ENABLE_MAIN_STREAM 0x84
72 #define XILINX_DP_TX_FORCE_SCRAMBLER_RESET 0xc0
73 #define XILINX_DP_TX_VERSION 0xf8
74 #define XILINX_DP_TX_VERSION_MAJOR_MASK (0xff << 24)
75 #define XILINX_DP_TX_VERSION_MAJOR_SHIFT 24
76 #define XILINX_DP_TX_VERSION_MINOR_MASK (0xff << 16)
77 #define XILINX_DP_TX_VERSION_MINOR_SHIFT 16
78 #define XILINX_DP_TX_VERSION_REVISION_MASK (0xf << 12)
79 #define XILINX_DP_TX_VERSION_REVISION_SHIFT 12
80 #define XILINX_DP_TX_VERSION_PATCH_MASK (0xf << 8)
81 #define XILINX_DP_TX_VERSION_PATCH_SHIFT 8
82 #define XILINX_DP_TX_VERSION_INTERNAL_MASK (0xff << 0)
83 #define XILINX_DP_TX_VERSION_INTERNAL_SHIFT 0
85 /* Core ID registers */
86 #define XILINX_DP_TX_CORE_ID 0xfc
87 #define XILINX_DP_TX_CORE_ID_MAJOR_MASK (0xff << 24)
88 #define XILINX_DP_TX_CORE_ID_MAJOR_SHIFT 24
89 #define XILINX_DP_TX_CORE_ID_MINOR_MASK (0xff << 16)
90 #define XILINX_DP_TX_CORE_ID_MINOR_SHIFT 16
91 #define XILINX_DP_TX_CORE_ID_REVISION_MASK (0xff << 8)
92 #define XILINX_DP_TX_CORE_ID_REVISION_SHIFT 8
93 #define XILINX_DP_TX_CORE_ID_DIRECTION BIT(0)
95 /* AUX channel interface registers */
96 #define XILINX_DP_TX_AUX_COMMAND 0x100
97 #define XILINX_DP_TX_AUX_COMMAND_CMD_SHIFT 8
98 #define XILINX_DP_TX_AUX_COMMAND_ADDRESS_ONLY BIT(12)
99 #define XILINX_DP_TX_AUX_COMMAND_BYTES_SHIFT 0
100 #define XILINX_DP_TX_AUX_WRITE_FIFO 0x104
101 #define XILINX_DP_TX_AUX_ADDRESS 0x108
102 #define XILINX_DP_TX_CLK_DIVIDER 0x10c
103 #define XILINX_DP_TX_CLK_DIVIDER_MHZ 1000000
104 #define XILINX_DP_TX_CLK_DIVIDER_AUX_FILTER_SHIFT 8
105 #define XILINX_DP_TX_INTR_SIGNAL_STATE 0x130
106 #define XILINX_DP_TX_INTR_SIGNAL_STATE_HPD BIT(0)
107 #define XILINX_DP_TX_INTR_SIGNAL_STATE_REQUEST BIT(1)
108 #define XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY BIT(2)
109 #define XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY_TIMEOUT BIT(3)
110 #define XILINX_DP_TX_AUX_REPLY_DATA 0x134
111 #define XILINX_DP_TX_AUX_REPLY_CODE 0x138
112 #define XILINX_DP_TX_AUX_REPLY_CODE_AUX_ACK (0)
113 #define XILINX_DP_TX_AUX_REPLY_CODE_AUX_NACK BIT(0)
114 #define XILINX_DP_TX_AUX_REPLY_CODE_AUX_DEFER BIT(1)
115 #define XILINX_DP_TX_AUX_REPLY_CODE_I2C_ACK (0)
116 #define XILINX_DP_TX_AUX_REPLY_CODE_I2C_NACK BIT(2)
117 #define XILINX_DP_TX_AUX_REPLY_CODE_I2C_DEFER BIT(3)
118 #define XILINX_DP_TX_AUX_REPLY_CNT 0x13c
119 #define XILINX_DP_TX_AUX_REPLY_CNT_MASK 0xff
120 #define XILINX_DP_TX_INTR_STATUS 0x140
121 #define XILINX_DP_TX_INTR_MASK 0x144
122 #define XILINX_DP_TX_INTR_HPD_IRQ BIT(0)
123 #define XILINX_DP_TX_INTR_HPD_EVENT BIT(1)
124 #define XILINX_DP_TX_INTR_REPLY_RECV BIT(2)
125 #define XILINX_DP_TX_INTR_REPLY_TIMEOUT BIT(3)
126 #define XILINX_DP_TX_INTR_HPD_PULSE BIT(4)
127 #define XILINX_DP_TX_INTR_EXT_PKT_TXD BIT(5)
128 #define XILINX_DP_TX_INTR_LIV_ABUF_UNDRFLW BIT(12)
129 #define XILINX_DP_TX_INTR_VBLANK_START BIT(13)
130 #define XILINX_DP_TX_INTR_PIXEL0_MATCH BIT(14)
131 #define XILINX_DP_TX_INTR_PIXEL1_MATCH BIT(15)
132 #define XILINX_DP_TX_INTR_CHBUF_UNDERFLW_MASK 0x3f0000
133 #define XILINX_DP_TX_INTR_CHBUF_OVERFLW_MASK 0xfc00000
134 #define XILINX_DP_TX_INTR_CUST_TS_2 BIT(28)
135 #define XILINX_DP_TX_INTR_CUST_TS BIT(29)
136 #define XILINX_DP_TX_INTR_EXT_VSYNC_TS BIT(30)
137 #define XILINX_DP_TX_INTR_VSYNC_TS BIT(31)
138 #define XILINX_DP_TX_INTR_ALL (XILINX_DP_TX_INTR_HPD_IRQ | \
139 XILINX_DP_TX_INTR_HPD_EVENT | \
140 XILINX_DP_TX_INTR_REPLY_RECV | \
141 XILINX_DP_TX_INTR_REPLY_TIMEOUT | \
142 XILINX_DP_TX_INTR_HPD_PULSE | \
143 XILINX_DP_TX_INTR_EXT_PKT_TXD | \
144 XILINX_DP_TX_INTR_LIV_ABUF_UNDRFLW | \
145 XILINX_DP_TX_INTR_VBLANK_START | \
146 XILINX_DP_TX_INTR_CHBUF_UNDERFLW_MASK | \
147 XILINX_DP_TX_INTR_CHBUF_OVERFLW_MASK)
148 #define XILINX_DP_TX_REPLY_DATA_CNT 0x148
149 #define XILINX_DP_SUB_TX_INTR_STATUS 0x3a0
150 #define XILINX_DP_SUB_TX_INTR_MASK 0x3a4
151 #define XILINX_DP_SUB_TX_INTR_EN 0x3a8
152 #define XILINX_DP_SUB_TX_INTR_DS 0x3ac
154 /* Main stream attribute registers */
155 #define XILINX_DP_TX_MAIN_STREAM_HTOTAL 0x180
156 #define XILINX_DP_TX_MAIN_STREAM_VTOTAL 0x184
157 #define XILINX_DP_TX_MAIN_STREAM_POLARITY 0x188
158 #define XILINX_DP_TX_MAIN_STREAM_POLARITY_HSYNC_SHIFT 0
159 #define XILINX_DP_TX_MAIN_STREAM_POLARITY_VSYNC_SHIFT 1
160 #define XILINX_DP_TX_MAIN_STREAM_HSWIDTH 0x18c
161 #define XILINX_DP_TX_MAIN_STREAM_VSWIDTH 0x190
162 #define XILINX_DP_TX_MAIN_STREAM_HRES 0x194
163 #define XILINX_DP_TX_MAIN_STREAM_VRES 0x198
164 #define XILINX_DP_TX_MAIN_STREAM_HSTART 0x19c
165 #define XILINX_DP_TX_MAIN_STREAM_VSTART 0x1a0
166 #define XILINX_DP_TX_MAIN_STREAM_MISC0 0x1a4
167 #define XILINX_DP_TX_MAIN_STREAM_MISC0_SYNC BIT(0)
168 #define XILINX_DP_TX_MAIN_STREAM_MISC0_FORMAT_SHIFT 1
169 #define XILINX_DP_TX_MAIN_STREAM_MISC0_DYNAMIC_RANGE BIT(3)
170 #define XILINX_DP_TX_MAIN_STREAM_MISC0_YCBCR_COLRIMETRY BIT(4)
171 #define XILINX_DP_TX_MAIN_STREAM_MISC0_BPC_SHIFT 5
172 #define XILINX_DP_TX_MAIN_STREAM_MISC1 0x1a8
173 #define XILINX_DP_TX_MAIN_STREAM_MISC0_INTERLACED_VERT BIT(0)
174 #define XILINX_DP_TX_MAIN_STREAM_MISC0_STEREO_VID_SHIFT 1
175 #define XILINX_DP_TX_M_VID 0x1ac
176 #define XILINX_DP_TX_TRANSFER_UNIT_SIZE 0x1b0
177 #define XILINX_DP_TX_DEF_TRANSFER_UNIT_SIZE 64
178 #define XILINX_DP_TX_N_VID 0x1b4
179 #define XILINX_DP_TX_USER_PIXEL_WIDTH 0x1b8
180 #define XILINX_DP_TX_USER_DATA_CNT_PER_LANE 0x1bc
181 #define XILINX_DP_TX_MIN_BYTES_PER_TU 0x1c4
182 #define XILINX_DP_TX_FRAC_BYTES_PER_TU 0x1c8
183 #define XILINX_DP_TX_INIT_WAIT 0x1cc
185 /* PHY configuration and status registers */
186 #define XILINX_DP_TX_PHY_CONFIG 0x200
187 #define XILINX_DP_TX_PHY_CONFIG_PHY_RESET BIT(0)
188 #define XILINX_DP_TX_PHY_CONFIG_GTTX_RESET BIT(1)
189 #define XILINX_DP_TX_PHY_CONFIG_PHY_PMA_RESET BIT(8)
190 #define XILINX_DP_TX_PHY_CONFIG_PHY_PCS_RESET BIT(9)
191 #define XILINX_DP_TX_PHY_CONFIG_ALL_RESET (XILINX_DP_TX_PHY_CONFIG_PHY_RESET | \
192 XILINX_DP_TX_PHY_CONFIG_GTTX_RESET | \
193 XILINX_DP_TX_PHY_CONFIG_PHY_PMA_RESET | \
194 XILINX_DP_TX_PHY_CONFIG_PHY_PCS_RESET)
195 #define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_0 0x210
196 #define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_1 0x214
197 #define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_2 0x218
198 #define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_3 0x21c
199 #define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x220
200 #define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x224
201 #define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x228
202 #define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x22c
203 #define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING 0x234
204 #define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_162 0x1
205 #define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_270 0x3
206 #define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_540 0x5
207 #define XILINX_DP_TX_PHY_POWER_DOWN 0x238
208 #define XILINX_DP_TX_PHY_POWER_DOWN_LANE_0 BIT(0)
209 #define XILINX_DP_TX_PHY_POWER_DOWN_LANE_1 BIT(1)
210 #define XILINX_DP_TX_PHY_POWER_DOWN_LANE_2 BIT(2)
211 #define XILINX_DP_TX_PHY_POWER_DOWN_LANE_3 BIT(3)
212 #define XILINX_DP_TX_PHY_POWER_DOWN_ALL 0xf
213 #define XILINX_DP_TX_PHY_PRECURSOR_LANE_0 0x23c
214 #define XILINX_DP_TX_PHY_PRECURSOR_LANE_1 0x240
215 #define XILINX_DP_TX_PHY_PRECURSOR_LANE_2 0x244
216 #define XILINX_DP_TX_PHY_PRECURSOR_LANE_3 0x248
217 #define XILINX_DP_TX_PHY_POSTCURSOR_LANE_0 0x24c
218 #define XILINX_DP_TX_PHY_POSTCURSOR_LANE_1 0x250
219 #define XILINX_DP_TX_PHY_POSTCURSOR_LANE_2 0x254
220 #define XILINX_DP_TX_PHY_POSTCURSOR_LANE_3 0x258
221 #define XILINX_DP_SUB_TX_PHY_PRECURSOR_LANE_0 0x24c
222 #define XILINX_DP_SUB_TX_PHY_PRECURSOR_LANE_1 0x250
223 #define XILINX_DP_TX_PHY_STATUS 0x280
224 #define XILINX_DP_TX_PHY_STATUS_PLL_LOCKED_SHIFT 4
225 #define XILINX_DP_TX_PHY_STATUS_FPGA_PLL_LOCKED BIT(6)
227 /* Audio registers */
228 #define XILINX_DP_TX_AUDIO_CONTROL 0x300
229 #define XILINX_DP_TX_AUDIO_CHANNELS 0x304
230 #define XILINX_DP_TX_AUDIO_INFO_DATA 0x308
231 #define XILINX_DP_TX_AUDIO_M_AUD 0x328
232 #define XILINX_DP_TX_AUDIO_N_AUD 0x32c
233 #define XILINX_DP_TX_AUDIO_EXT_DATA 0x330
235 #define XILINX_DP_MISC0_RGB (0)
236 #define XILINX_DP_MISC0_YCRCB_422 (5 << 1)
237 #define XILINX_DP_MISC0_YCRCB_444 (6 << 1)
238 #define XILINX_DP_MISC0_FORMAT_MASK 0xe
239 #define XILINX_DP_MISC0_BPC_6 (0 << 5)
240 #define XILINX_DP_MISC0_BPC_8 (1 << 5)
241 #define XILINX_DP_MISC0_BPC_10 (2 << 5)
242 #define XILINX_DP_MISC0_BPC_12 (3 << 5)
243 #define XILINX_DP_MISC0_BPC_16 (4 << 5)
244 #define XILINX_DP_MISC0_BPC_MASK 0xe0
245 #define XILINX_DP_MISC1_Y_ONLY (1 << 7)
247 #define DP_REDUCED_BIT_RATE 162000
248 #define DP_HIGH_BIT_RATE 270000
249 #define DP_HIGH_BIT_RATE2 540000
250 #define DP_MAX_TRAINING_TRIES 5
251 #define DP_MAX_LANES 4
259 * struct xilinx_drm_dp_link_config - Common link config between source and sink
260 * @max_rate: maximum link rate
261 * @max_lanes: maximum number of lanes
263 struct xilinx_drm_dp_link_config {
269 * struct xilinx_drm_dp_mode - Configured mode of DisplayPort
270 * @bw_code: code for bandwidth(link rate)
271 * @lane_cnt: number of lanes
272 * @pclock: pixel clock frequency of current mode
274 struct xilinx_drm_dp_mode {
281 * struct xilinx_drm_dp_config - Configuration of DisplayPort from DTS
282 * @dp_version: DisplayPort protocol version
283 * @max_lanes: max number of lanes
284 * @max_link_rate: max link rate
285 * @max_bpc: maximum bits-per-color
286 * @max_pclock: maximum pixel clock rate
287 * @enable_yonly: enable yonly color space logic
288 * @enable_ycrcb: enable ycrcb color space logic
289 * @misc0: misc0 configuration (per DP v1.2 spec)
290 * @misc1: misc1 configuration (per DP v1.2 spec)
291 * @bpp: bits per pixel
293 struct xilinx_drm_dp_config {
294 enum dp_version dp_version;
308 * struct xilinx_drm_dp - Xilinx DisplayPort core
309 * @encoder: pointer to the drm encoder structure
310 * @dev: device structure
311 * @iomem: device I/O memory for register access
312 * @config: IP core configuration from DTS
314 * @dp_sub: DisplayPort subsystem
315 * @phy: PHY handles for DP lanes
316 * @aclk: clock source device for internal axi4-lite clock
317 * @aud_clk: clock source device for audio clock
318 * @aud_clk_enabled: if audio clock is enabled
319 * @dpms: current dpms state
320 * @status: the connection status
321 * @dpcd: DP configuration data from currently connected sink device
322 * @link_config: common link configuration between IP core and sink device
323 * @mode: current mode between IP core and sink device
324 * @train_set: set of training data
326 struct xilinx_drm_dp {
327 struct drm_encoder *encoder;
331 struct xilinx_drm_dp_config config;
332 struct drm_dp_aux aux;
333 struct xilinx_drm_dp_sub *dp_sub;
334 struct phy *phy[DP_MAX_LANES];
337 bool aud_clk_enabled;
340 enum drm_connector_status status;
341 u8 dpcd[DP_RECEIVER_CAP_SIZE];
342 struct xilinx_drm_dp_link_config link_config;
343 struct xilinx_drm_dp_mode mode;
344 u8 train_set[DP_MAX_LANES];
347 static inline struct xilinx_drm_dp *to_dp(struct drm_encoder *encoder)
349 return to_encoder_slave(encoder)->slave_priv;
352 #define AUX_READ_BIT 0x1
354 #ifdef CONFIG_DRM_XILINX_DP_DEBUG_FS
355 #define XILINX_DP_DEBUGFS_READ_MAX_SIZE 32
356 #define XILINX_DP_DEBUGFS_UINT8_MAX_STR "255"
357 #define IN_RANGE(x, min, max) ({ \
358 typeof(x) _x = (x); \
359 _x >= (min) && _x <= (max); })
361 /* Match xilinx_dp_testcases vs dp_debugfs_reqs[] entry */
362 enum xilinx_dp_testcases {
369 struct xilinx_dp_debugfs {
370 enum xilinx_dp_testcases testcase;
374 struct xilinx_drm_dp *dp;
377 struct xilinx_dp_debugfs dp_debugfs;
378 struct xilinx_dp_debugfs_request {
380 enum xilinx_dp_testcases tc;
381 ssize_t (*read_handler)(char **kern_buff);
382 ssize_t (*write_handler)(char **cmd);
385 static s64 xilinx_dp_debugfs_argument_value(char *arg)
392 if (!kstrtos64(arg, 0, &value))
398 static int xilinx_dp_update_output_format(u8 output_fmt, u32 num_colors)
400 struct xilinx_drm_dp *dp = dp_debugfs.dp;
401 struct xilinx_drm_dp_config *config = &dp->config;
403 u8 bpc_bits = (config->misc0 & XILINX_DP_MISC0_BPC_MASK);
404 bool misc1 = output_fmt & XILINX_DP_MISC1_Y_ONLY ? true : false;
407 case XILINX_DP_MISC0_BPC_6:
410 case XILINX_DP_MISC0_BPC_8:
413 case XILINX_DP_MISC0_BPC_10:
416 case XILINX_DP_MISC0_BPC_12:
419 case XILINX_DP_MISC0_BPC_16:
423 dev_err(dp->dev, "Invalid bpc count for misc0\n");
427 /* clear old format */
428 config->misc0 &= ~XILINX_DP_MISC0_FORMAT_MASK;
429 config->misc1 &= ~XILINX_DP_MISC1_Y_ONLY;
432 config->misc1 |= output_fmt;
433 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_MISC1,
436 config->misc0 |= output_fmt;
437 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_MISC0,
440 config->bpp = num_colors * bpc;
445 static ssize_t xilinx_dp_debugfs_max_linkrate_write(char **dp_test_arg)
450 link_rate_arg = strsep(dp_test_arg, " ");
451 link_rate = xilinx_dp_debugfs_argument_value(link_rate_arg);
452 if (link_rate < 0 || (link_rate != DP_HIGH_BIT_RATE2 &&
453 link_rate != DP_HIGH_BIT_RATE &&
454 link_rate != DP_REDUCED_BIT_RATE))
457 dp_debugfs.link_rate = drm_dp_link_rate_to_bw_code(link_rate);
458 dp_debugfs.testcase = DP_TC_LINK_RATE;
463 static ssize_t xilinx_dp_debugfs_max_lanecnt_write(char **dp_test_arg)
468 lane_cnt_arg = strsep(dp_test_arg, " ");
469 lane_count = xilinx_dp_debugfs_argument_value(lane_cnt_arg);
470 if (lane_count < 0 || !IN_RANGE(lane_count, 1,
471 dp_debugfs.dp->config.max_lanes))
474 dp_debugfs.lane_cnt = lane_count;
475 dp_debugfs.testcase = DP_TC_LANE_COUNT;
480 static ssize_t xilinx_dp_debugfs_output_display_format_write(char **dp_test_arg)
483 struct xilinx_drm_dp *dp = dp_debugfs.dp;
488 /* Read the value from an user value */
489 output_format = strsep(dp_test_arg, " ");
491 if (strncmp(output_format, "rgb", 3) == 0) {
492 output_fmt = XILINX_DP_MISC0_RGB;
494 } else if (strncmp(output_format, "ycbcr422", 8) == 0) {
495 output_fmt = XILINX_DP_MISC0_YCRCB_422;
497 } else if (strncmp(output_format, "ycbcr444", 8) == 0) {
498 output_fmt = XILINX_DP_MISC0_YCRCB_444;
500 } else if (strncmp(output_format, "yonly", 5) == 0) {
501 output_fmt = XILINX_DP_MISC1_Y_ONLY;
504 dev_err(dp->dev, "Invalid output format\n");
508 if (dp->config.misc1 & XILINX_DP_MISC1_Y_ONLY)
509 dp_debugfs.old_output_fmt = XILINX_DP_MISC1_Y_ONLY;
511 dp_debugfs.old_output_fmt = dp->config.misc0 &
512 XILINX_DP_MISC0_FORMAT_MASK;
514 ret = xilinx_dp_update_output_format(output_fmt, num_colors);
516 dp_debugfs.testcase = DP_TC_OUTPUT_FMT;
520 static ssize_t xilinx_dp_debugfs_max_linkrate_read(char **kern_buff)
522 struct xilinx_drm_dp *dp = dp_debugfs.dp;
523 size_t output_str_len;
527 dp_debugfs.testcase = DP_TC_NONE;
528 dp_debugfs.link_rate = 0;
530 /* Getting Sink Side Link Rate */
531 ret = drm_dp_dpcd_readb(&dp->aux, DP_LINK_BW_SET, &dpcd_link_bw);
533 dev_err(dp->dev, "Failed to read link rate via AUX.\n");
538 output_str_len = strlen(XILINX_DP_DEBUGFS_UINT8_MAX_STR);
539 output_str_len = min_t(size_t, XILINX_DP_DEBUGFS_READ_MAX_SIZE,
541 snprintf(*kern_buff, output_str_len, "%u", dpcd_link_bw);
546 static ssize_t xilinx_dp_debugfs_max_lanecnt_read(char **kern_buff)
548 struct xilinx_drm_dp *dp = dp_debugfs.dp;
549 size_t output_str_len;
553 dp_debugfs.testcase = DP_TC_NONE;
554 dp_debugfs.lane_cnt = 0;
556 /* Getting Sink Side Lane Count */
557 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &dpcd_lane_cnt);
559 dev_err(dp->dev, "Failed to read link rate via AUX.\n");
564 dpcd_lane_cnt &= DP_LANE_COUNT_MASK;
565 output_str_len = strlen(XILINX_DP_DEBUGFS_UINT8_MAX_STR);
566 output_str_len = min_t(size_t, XILINX_DP_DEBUGFS_READ_MAX_SIZE,
568 snprintf(*kern_buff, output_str_len, "%u", dpcd_lane_cnt);
574 xilinx_dp_debugfs_output_display_format_read(char **kern_buff)
577 struct xilinx_drm_dp *dp = dp_debugfs.dp;
578 u8 old_output_fmt = dp_debugfs.old_output_fmt;
579 size_t output_str_len;
582 dp_debugfs.testcase = DP_TC_NONE;
584 if (old_output_fmt == XILINX_DP_MISC0_RGB) {
586 } else if (old_output_fmt == XILINX_DP_MISC0_YCRCB_422) {
588 } else if (old_output_fmt == XILINX_DP_MISC0_YCRCB_444) {
590 } else if (old_output_fmt == XILINX_DP_MISC1_Y_ONLY) {
593 dev_err(dp->dev, "Invalid output format in misc0\n");
597 ret = xilinx_dp_update_output_format(old_output_fmt, num_colors);
601 output_str_len = strlen("Success");
602 output_str_len = min_t(size_t, XILINX_DP_DEBUGFS_READ_MAX_SIZE,
604 snprintf(*kern_buff, output_str_len, "%s", "Success");
609 /* Match xilinx_dp_testcases vs dp_debugfs_reqs[] entry */
610 struct xilinx_dp_debugfs_request dp_debugfs_reqs[] = {
611 {"LINK_RATE", DP_TC_LINK_RATE,
612 xilinx_dp_debugfs_max_linkrate_read,
613 xilinx_dp_debugfs_max_linkrate_write},
614 {"LANE_COUNT", DP_TC_LANE_COUNT,
615 xilinx_dp_debugfs_max_lanecnt_read,
616 xilinx_dp_debugfs_max_lanecnt_write},
617 {"OUTPUT_DISPLAY_FORMAT", DP_TC_OUTPUT_FMT,
618 xilinx_dp_debugfs_output_display_format_read,
619 xilinx_dp_debugfs_output_display_format_write},
622 static ssize_t xilinx_dp_debugfs_read(struct file *f, char __user *buf,
623 size_t size, loff_t *pos)
625 char *kern_buff = NULL;
626 size_t kern_buff_len, out_str_len;
635 kern_buff = kzalloc(XILINX_DP_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL);
637 dp_debugfs.testcase = DP_TC_NONE;
641 if (dp_debugfs.testcase == DP_TC_NONE) {
642 out_str_len = strlen("No testcase executed");
643 out_str_len = min_t(size_t, XILINX_DP_DEBUGFS_READ_MAX_SIZE,
645 snprintf(kern_buff, out_str_len, "%s", "No testcase executed");
647 ret = dp_debugfs_reqs[dp_debugfs.testcase].read_handler(
655 kern_buff_len = strlen(kern_buff);
656 size = min(size, kern_buff_len);
658 ret = copy_to_user(buf, kern_buff, size);
669 xilinx_dp_debugfs_write(struct file *f, const char __user *buf,
670 size_t size, loff_t *pos)
672 char *kern_buff, *kern_buff_start;
677 if (*pos != 0 || size <= 0)
680 if (dp_debugfs.testcase != DP_TC_NONE)
683 kern_buff = kzalloc(size, GFP_KERNEL);
686 kern_buff_start = kern_buff;
688 ret = strncpy_from_user(kern_buff, buf, size);
690 kfree(kern_buff_start);
694 /* Read the testcase name and argument from an user request */
695 dp_test_req = strsep(&kern_buff, " ");
697 for (i = 0; i < ARRAY_SIZE(dp_debugfs_reqs); i++) {
698 if (!strcasecmp(dp_test_req, dp_debugfs_reqs[i].req))
699 if (!dp_debugfs_reqs[i].write_handler(&kern_buff)) {
700 kfree(kern_buff_start);
705 kfree(kern_buff_start);
709 static const struct file_operations fops_xilinx_dp_dbgfs = {
710 .owner = THIS_MODULE,
711 .read = xilinx_dp_debugfs_read,
712 .write = xilinx_dp_debugfs_write,
715 static int xilinx_dp_debugfs_init(struct xilinx_drm_dp *dp)
718 struct dentry *xilinx_dp_debugfs_dir, *xilinx_dp_debugfs_file;
720 dp_debugfs.testcase = DP_TC_NONE;
723 xilinx_dp_debugfs_dir = debugfs_create_dir("dp", NULL);
724 if (!xilinx_dp_debugfs_dir) {
725 dev_err(dp->dev, "debugfs_create_dir failed\n");
729 xilinx_dp_debugfs_file =
730 debugfs_create_file("testcase", 0444, xilinx_dp_debugfs_dir,
731 NULL, &fops_xilinx_dp_dbgfs);
732 if (!xilinx_dp_debugfs_file) {
733 dev_err(dp->dev, "debugfs_create_file testcase failed\n");
740 debugfs_remove_recursive(xilinx_dp_debugfs_dir);
741 xilinx_dp_debugfs_dir = NULL;
745 static void xilinx_dp_debugfs_mode_config(struct xilinx_drm_dp *dp)
748 dp_debugfs.link_rate ? dp_debugfs.link_rate : dp->mode.bw_code;
750 dp_debugfs.lane_cnt ? dp_debugfs.lane_cnt : dp->mode.lane_cnt;
753 static int xilinx_dp_debugfs_init(struct xilinx_drm_dp *dp)
758 static void xilinx_dp_debugfs_mode_config(struct xilinx_drm_dp *dp)
761 #endif /* DRM_XILINX_DP_DEBUG_FS */
764 * xilinx_drm_dp_aux_cmd_submit - Submit aux command
765 * @dp: DisplayPort IP core structure
768 * @buf: buffer for command data
769 * @bytes: number of bytes for @buf
770 * @reply: reply code to be returned
772 * Submit an aux command. All aux related commands, native or i2c aux
773 * read/write, are submitted through this function. The function is mapped to
774 * the transfer function of struct drm_dp_aux. This function involves in
775 * multiple register reads/writes, thus synchronization is needed, and it is
776 * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
777 * if there's no immediate reply to the command submission. The reply code is
778 * returned at @reply if @reply != NULL.
780 * Return: 0 if the command is submitted properly, or corresponding error code:
781 * -EBUSY when there is any request already being processed
782 * -ETIMEDOUT when receiving reply is timed out
783 * -EIO when received bytes are less than requested
785 static int xilinx_drm_dp_aux_cmd_submit(struct xilinx_drm_dp *dp, u32 cmd,
786 u16 addr, u8 *buf, u8 bytes, u8 *reply)
788 bool is_read = (cmd & AUX_READ_BIT) ? true : false;
789 void __iomem *iomem = dp->iomem;
792 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_INTR_SIGNAL_STATE);
793 if (reg & XILINX_DP_TX_INTR_SIGNAL_STATE_REQUEST)
796 xilinx_drm_writel(iomem, XILINX_DP_TX_AUX_ADDRESS, addr);
799 for (i = 0; i < bytes; i++)
800 xilinx_drm_writel(iomem, XILINX_DP_TX_AUX_WRITE_FIFO,
803 reg = cmd << XILINX_DP_TX_AUX_COMMAND_CMD_SHIFT;
805 reg |= XILINX_DP_TX_AUX_COMMAND_ADDRESS_ONLY;
807 reg |= (bytes - 1) << XILINX_DP_TX_AUX_COMMAND_BYTES_SHIFT;
808 xilinx_drm_writel(iomem, XILINX_DP_TX_AUX_COMMAND, reg);
810 /* Wait for reply to be delivered upto 2ms */
812 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_INTR_SIGNAL_STATE);
814 if (reg & XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY)
817 if (reg & XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY_TIMEOUT ||
821 usleep_range(1000, 1100);
824 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_AUX_REPLY_CODE);
829 (reg == XILINX_DP_TX_AUX_REPLY_CODE_AUX_ACK ||
830 reg == XILINX_DP_TX_AUX_REPLY_CODE_I2C_ACK)) {
831 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_REPLY_DATA_CNT);
832 if ((reg & XILINX_DP_TX_AUX_REPLY_CNT_MASK) != bytes)
835 for (i = 0; i < bytes; i++)
836 buf[i] = xilinx_drm_readl(iomem,
837 XILINX_DP_TX_AUX_REPLY_DATA);
844 * xilinx_drm_dp_phy_ready - Check if PHY is ready
845 * @dp: DisplayPort IP core structure
847 * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
848 * This amount of delay was suggested by IP designer.
850 * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
852 static int xilinx_drm_dp_phy_ready(struct xilinx_drm_dp *dp)
854 u32 i, reg, ready, lane;
856 lane = dp->config.max_lanes;
857 ready = (1 << lane) - 1;
859 ready |= XILINX_DP_TX_PHY_STATUS_FPGA_PLL_LOCKED;
861 /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
863 reg = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_PHY_STATUS);
864 if ((reg & ready) == ready)
868 DRM_ERROR("PHY isn't ready\n");
872 usleep_range(1000, 1100);
879 * xilinx_drm_dp_max_rate - Calculate and return available max pixel clock
880 * @link_rate: link rate (Kilo-bytes / sec)
881 * @lane_num: number of lanes
882 * @bpp: bits per pixel
884 * Return: max pixel clock (KHz) supported by current link config.
886 static inline int xilinx_drm_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
888 return link_rate * lane_num * 8 / bpp;
892 * xilinx_drm_dp_mode_configure - Configure the link values
893 * @dp: DisplayPort IP core structure
894 * @pclock: pixel clock for requested display mode
895 * @current_bw: current link rate
897 * Find the link configuration values, rate and lane count for requested pixel
898 * clock @pclock. The @pclock is stored in the mode to be used in other
899 * functions later. The returned rate is downshifted from the current rate
902 * Return: Current link rate code, or -EINVAL.
904 static int xilinx_drm_dp_mode_configure(struct xilinx_drm_dp *dp, int pclock,
907 int max_rate = dp->link_config.max_rate;
908 u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
909 u8 max_lanes = dp->link_config.max_lanes;
910 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
911 u8 bpp = dp->config.bpp;
915 for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
916 if (current_bw && bws[i] >= current_bw)
919 if (bws[i] <= max_link_rate_code)
923 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
927 bw = drm_dp_bw_code_to_link_rate(bws[i]);
928 rate = xilinx_drm_dp_max_rate(bw, lane_cnt, bpp);
929 if (pclock <= rate) {
930 dp->mode.bw_code = bws[i];
931 dp->mode.lane_cnt = lane_cnt;
932 dp->mode.pclock = pclock;
933 xilinx_dp_debugfs_mode_config(dp);
934 return dp->mode.bw_code;
938 dev_dbg(dp->dev, "failed to configure link values\n");
944 * xilinx_drm_dp_adjust_train - Adjust train values
945 * @dp: DisplayPort IP core structure
946 * @link_status: link status from sink which contains requested training values
948 static void xilinx_drm_dp_adjust_train(struct xilinx_drm_dp *dp,
949 u8 link_status[DP_LINK_STATUS_SIZE])
951 u8 *train_set = dp->train_set;
952 u8 voltage = 0, preemphasis = 0;
956 for (i = 0; i < dp->mode.lane_cnt; i++) {
957 u8 v = drm_dp_get_adjust_request_voltage(link_status, i);
958 u8 p = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
967 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
968 voltage |= DP_TRAIN_MAX_SWING_REACHED;
970 max_preemphasis = (dp->dp_sub) ? DP_TRAIN_PRE_EMPH_LEVEL_2 :
971 DP_TRAIN_PRE_EMPH_LEVEL_3;
973 if (preemphasis >= max_preemphasis)
974 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
976 for (i = 0; i < dp->mode.lane_cnt; i++)
977 train_set[i] = voltage | preemphasis;
981 * xilinx_drm_dp_update_vs_emph - Update the training values
982 * @dp: DisplayPort IP core structure
984 * Update the training values based on the request from sink. The mapped values
985 * are predefined, and values(vs, pe, pc) are from the device manual.
987 * Return: 0 if vs and emph are updated successfully, or the error code returned
988 * by drm_dp_dpcd_write().
990 static int xilinx_drm_dp_update_vs_emph(struct xilinx_drm_dp *dp)
992 u8 *train_set = dp->train_set;
993 u8 i, v_level, p_level;
995 static u8 vs[4][4] = { { 0x2a, 0x27, 0x24, 0x20 },
996 { 0x27, 0x23, 0x20, 0xff },
997 { 0x24, 0x20, 0xff, 0xff },
998 { 0xff, 0xff, 0xff, 0xff } };
999 static u8 pe[4][4] = { { 0x2, 0x2, 0x2, 0x2 },
1000 { 0x1, 0x1, 0x1, 0xff },
1001 { 0x0, 0x0, 0xff, 0xff },
1002 { 0xff, 0xff, 0xff, 0xff } };
1004 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set,
1009 for (i = 0; i < dp->mode.lane_cnt; i++) {
1010 v_level = (train_set[i] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
1011 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1012 p_level = (train_set[i] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
1013 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1016 u32 reg = XILINX_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
1018 xpsgtr_margining_factor(dp->phy[i], p_level, v_level);
1019 xpsgtr_override_deemph(dp->phy[i], p_level, v_level);
1020 xilinx_drm_writel(dp->iomem, reg, 0x2);
1024 reg = XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_0 + i + 4;
1025 xilinx_drm_writel(dp->iomem, reg, vs[p_level][v_level]);
1026 reg = XILINX_DP_TX_PHY_PRECURSOR_LANE_0 + i + 4;
1027 xilinx_drm_writel(dp->iomem, reg, pe[p_level][v_level]);
1028 reg = XILINX_DP_TX_PHY_POSTCURSOR_LANE_0 + i + 4;
1029 xilinx_drm_writel(dp->iomem, reg, 0);
1037 * xilinx_drm_dp_link_train_cr - Train clock recovery
1038 * @dp: DisplayPort IP core structure
1040 * Return: 0 if clock recovery train is done successfully, or corresponding
1043 static int xilinx_drm_dp_link_train_cr(struct xilinx_drm_dp *dp)
1045 u8 link_status[DP_LINK_STATUS_SIZE];
1046 u8 lane_cnt = dp->mode.lane_cnt;
1047 u8 vs = 0, tries = 0;
1052 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRAINING_PATTERN_SET,
1053 DP_TRAINING_PATTERN_1);
1054 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
1055 DP_TRAINING_PATTERN_1 |
1056 DP_LINK_SCRAMBLING_DISABLE);
1060 /* 256 loops should be maximum iterations for 4 lanes and 4 values.
1061 * So, This loop should exit before 512 iterations
1063 for (max_tries = 0; max_tries < 512; max_tries++) {
1064 ret = xilinx_drm_dp_update_vs_emph(dp);
1068 drm_dp_link_train_clock_recovery_delay(dp->dpcd);
1070 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
1074 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
1078 for (i = 0; i < lane_cnt; i++)
1079 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
1085 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
1090 if (tries == DP_MAX_TRAINING_TRIES)
1093 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1095 xilinx_drm_dp_adjust_train(dp, link_status);
1105 * xilinx_drm_dp_link_train_ce - Train channel equalization
1106 * @dp: DisplayPort IP core structure
1108 * Return: 0 if channel equalization train is done successfully, or
1109 * corresponding error code.
1111 static int xilinx_drm_dp_link_train_ce(struct xilinx_drm_dp *dp)
1113 u8 link_status[DP_LINK_STATUS_SIZE];
1114 u8 lane_cnt = dp->mode.lane_cnt;
1119 if (dp->config.dp_version == DP_V1_2 &&
1120 dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
1121 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
1122 pat = DP_TRAINING_PATTERN_3;
1124 pat = DP_TRAINING_PATTERN_2;
1125 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRAINING_PATTERN_SET, pat);
1126 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
1127 pat | DP_LINK_SCRAMBLING_DISABLE);
1131 for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
1132 ret = xilinx_drm_dp_update_vs_emph(dp);
1136 drm_dp_link_train_channel_eq_delay(dp->dpcd);
1138 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
1142 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
1146 xilinx_drm_dp_adjust_train(dp, link_status);
1156 * xilinx_drm_dp_link_train - Train the link
1157 * @dp: DisplayPort IP core structure
1159 * Return: 0 if all trains are done successfully, or corresponding error code.
1161 static int xilinx_drm_dp_train(struct xilinx_drm_dp *dp)
1164 u8 bw_code = dp->mode.bw_code;
1165 u8 lane_cnt = dp->mode.lane_cnt;
1166 u8 aux_lane_cnt = lane_cnt;
1170 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_LANE_CNT_SET, lane_cnt);
1172 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
1174 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENHANCED_FRAME_EN, 1);
1175 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1178 if (dp->dpcd[3] & 0x1) {
1179 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_DOWNSPREAD_CTL, 1);
1180 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
1183 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_DOWNSPREAD_CTL, 0);
1184 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
1187 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
1189 DRM_ERROR("failed to set lane count\n");
1193 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1196 DRM_ERROR("failed to set ANSI 8B/10B encoding\n");
1200 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
1202 DRM_ERROR("failed to set DP bandwidth\n");
1206 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_LINK_BW_SET, bw_code);
1209 case DP_LINK_BW_1_62:
1210 reg = XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_162;
1212 case DP_LINK_BW_2_7:
1213 reg = XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_270;
1215 case DP_LINK_BW_5_4:
1217 reg = XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_540;
1221 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING,
1223 ret = xilinx_drm_dp_phy_ready(dp);
1227 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_SCRAMBLING_DISABLE, 1);
1229 memset(dp->train_set, 0, 4);
1231 ret = xilinx_drm_dp_link_train_cr(dp);
1235 ret = xilinx_drm_dp_link_train_ce(dp);
1239 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
1240 DP_TRAINING_PATTERN_DISABLE);
1242 DRM_ERROR("failed to disable training pattern\n");
1245 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRAINING_PATTERN_SET,
1246 DP_TRAINING_PATTERN_DISABLE);
1248 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_SCRAMBLING_DISABLE, 0);
1254 * xilinx_drm_dp_train_loop - Downshift the link rate during training
1255 * @dp: DisplayPort IP core structure
1257 * Train the link by downshifting the link rate if training is not successful.
1259 static void xilinx_drm_dp_train_loop(struct xilinx_drm_dp *dp)
1261 struct xilinx_drm_dp_mode *mode = &dp->mode;
1262 u8 bw = mode->bw_code;
1266 if (dp->status == connector_status_disconnected)
1269 ret = xilinx_drm_dp_train(dp);
1273 ret = xilinx_drm_dp_mode_configure(dp, mode->pclock, bw);
1277 } while (bw >= DP_LINK_BW_1_62);
1279 DRM_ERROR("failed to train the DP link\n");
1283 * xilinx_drm_dp_init_aux - Initialize the DP aux
1284 * @dp: DisplayPort IP core structure
1286 * Initialize the DP aux. The aux clock is derived from the axi clock, so
1287 * this function gets the axi clock frequency and calculates the filter
1288 * value. Additionally, the interrupts and transmitter are enabled.
1290 * Return: 0 on success, error value otherwise
1292 static int xilinx_drm_dp_init_aux(struct xilinx_drm_dp *dp)
1297 clock_rate = clk_get_rate(dp->aclk);
1298 if (clock_rate < XILINX_DP_TX_CLK_DIVIDER_MHZ) {
1299 DRM_ERROR("aclk should be higher than 1MHz\n");
1303 /* Allowable values for this register are: 8, 16, 24, 32, 40, 48 */
1304 for (w = 8; w <= 48; w += 8) {
1305 /* AUX pulse width should be between 0.4 to 0.6 usec */
1306 if (w >= (4 * clock_rate / 10000000) &&
1307 w <= (6 * clock_rate / 10000000))
1312 DRM_ERROR("aclk frequency too high\n");
1315 reg = w << XILINX_DP_TX_CLK_DIVIDER_AUX_FILTER_SHIFT;
1317 reg |= clock_rate / XILINX_DP_TX_CLK_DIVIDER_MHZ;
1318 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_CLK_DIVIDER, reg);
1321 xilinx_drm_writel(dp->iomem, XILINX_DP_SUB_TX_INTR_EN,
1322 XILINX_DP_TX_INTR_ALL);
1324 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_INTR_MASK,
1325 (u32)~XILINX_DP_TX_INTR_ALL);
1326 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENABLE, 1);
1332 * xilinx_drm_dp_init_phy - Initialize the phy
1333 * @dp: DisplayPort IP core structure
1335 * Initialize the phy.
1337 * Return: 0 if the phy instances are initialized correctly, or the error code
1338 * returned from the callee functions.
1340 static int xilinx_drm_dp_init_phy(struct xilinx_drm_dp *dp)
1345 for (i = 0; i < dp->config.max_lanes; i++) {
1346 ret = phy_init(dp->phy[i]);
1348 dev_err(dp->dev, "failed to init phy lane %d\n", i);
1354 xilinx_drm_writel(dp->iomem, XILINX_DP_SUB_TX_INTR_DS,
1355 XILINX_DP_TX_INTR_ALL);
1357 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_INTR_MASK,
1358 XILINX_DP_TX_INTR_ALL);
1360 xilinx_drm_clr(dp->iomem, XILINX_DP_TX_PHY_CONFIG,
1361 XILINX_DP_TX_PHY_CONFIG_ALL_RESET);
1363 /* Wait for PLL to be locked for the primary (1st) */
1365 ret = xpsgtr_wait_pll_lock(dp->phy[0]);
1367 dev_err(dp->dev, "failed to lock pll\n");
1376 * xilinx_drm_dp_exit_phy - Exit the phy
1377 * @dp: DisplayPort IP core structure
1381 static void xilinx_drm_dp_exit_phy(struct xilinx_drm_dp *dp)
1386 for (i = 0; i < dp->config.max_lanes; i++) {
1387 ret = phy_exit(dp->phy[i]);
1390 "failed to exit phy (%d) %d\n", i, ret);
1395 static void xilinx_drm_dp_dpms(struct drm_encoder *encoder, int dpms)
1397 struct xilinx_drm_dp *dp = to_dp(encoder);
1398 void __iomem *iomem = dp->iomem;
1402 if (dp->dpms == dpms)
1408 case DRM_MODE_DPMS_ON:
1409 pm_runtime_get_sync(dp->dev);
1411 if (dp->aud_clk && !dp->aud_clk_enabled) {
1412 ret = clk_prepare_enable(dp->aud_clk);
1414 dev_err(dp->dev, "failed to enable aud_clk\n");
1416 xilinx_drm_writel(iomem,
1417 XILINX_DP_TX_AUDIO_CONTROL,
1419 dp->aud_clk_enabled = true;
1422 xilinx_drm_writel(iomem, XILINX_DP_TX_PHY_POWER_DOWN, 0);
1424 if (dp->status == connector_status_connected) {
1425 for (i = 0; i < 3; i++) {
1426 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1430 usleep_range(300, 500);
1432 /* Some monitors take time to wake up properly */
1433 msleep(xilinx_drm_dp_power_on_delay_ms);
1435 dev_dbg(dp->dev, "DP aux failed\n");
1437 xilinx_drm_dp_train_loop(dp);
1439 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_SW_RESET,
1440 XILINX_DP_TX_SW_RESET_ALL);
1441 xilinx_drm_writel(iomem, XILINX_DP_TX_ENABLE_MAIN_STREAM, 1);
1445 xilinx_drm_writel(iomem, XILINX_DP_TX_ENABLE_MAIN_STREAM, 0);
1446 if (dp->status == connector_status_connected) {
1447 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1450 xilinx_drm_writel(iomem, XILINX_DP_TX_PHY_POWER_DOWN,
1451 XILINX_DP_TX_PHY_POWER_DOWN_ALL);
1452 if (dp->aud_clk && dp->aud_clk_enabled) {
1453 xilinx_drm_writel(iomem, XILINX_DP_TX_AUDIO_CONTROL, 0);
1454 clk_disable_unprepare(dp->aud_clk);
1455 dp->aud_clk_enabled = false;
1457 pm_runtime_put_sync(dp->dev);
1463 static void xilinx_drm_dp_save(struct drm_encoder *encoder)
1468 static void xilinx_drm_dp_restore(struct drm_encoder *encoder)
1473 #define XILINX_DP_SUB_TX_MIN_H_BACKPORCH 20
1475 static bool xilinx_drm_dp_mode_fixup(struct drm_encoder *encoder,
1476 const struct drm_display_mode *mode,
1477 struct drm_display_mode *adjusted_mode)
1479 struct xilinx_drm_dp *dp = to_dp(encoder);
1480 int diff = mode->htotal - mode->hsync_end;
1483 * ZynqMP DP requires horizontal backporch to be greater than 12.
1484 * This limitation may conflict with the sink device.
1486 if (dp->dp_sub && diff < XILINX_DP_SUB_TX_MIN_H_BACKPORCH) {
1487 int vrefresh = (adjusted_mode->clock * 1000) /
1488 (adjusted_mode->vtotal * adjusted_mode->htotal);
1490 diff = XILINX_DP_SUB_TX_MIN_H_BACKPORCH - diff;
1491 adjusted_mode->htotal += diff;
1492 adjusted_mode->clock = adjusted_mode->vtotal *
1493 adjusted_mode->htotal * vrefresh / 1000;
1499 static int xilinx_drm_dp_mode_valid(struct drm_encoder *encoder,
1500 struct drm_display_mode *mode)
1502 struct xilinx_drm_dp *dp = to_dp(encoder);
1503 u8 max_lanes = dp->link_config.max_lanes;
1504 u8 bpp = dp->config.bpp;
1505 u32 max_pclock = dp->config.max_pclock;
1506 int max_rate = dp->link_config.max_rate;
1509 if (max_pclock && mode->clock > max_pclock)
1510 return MODE_CLOCK_HIGH;
1512 rate = xilinx_drm_dp_max_rate(max_rate, max_lanes, bpp);
1513 if (mode->clock > rate)
1514 return MODE_CLOCK_HIGH;
1520 * xilinx_drm_dp_mode_set_transfer_unit - Set the transfer unit values
1521 * @dp: DisplayPort IP core structure
1522 * @mode: requested display mode
1524 * Set the transfer unit, and caculate all transfer unit size related values.
1525 * Calculation is based on DP and IP core specification.
1527 static void xilinx_drm_dp_mode_set_transfer_unit(struct xilinx_drm_dp *dp,
1528 struct drm_display_mode *mode)
1530 u32 tu = XILINX_DP_TX_DEF_TRANSFER_UNIT_SIZE;
1531 u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1533 /* Use the max transfer unit size (default) */
1534 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRANSFER_UNIT_SIZE, tu);
1536 vid_kbytes = mode->clock * (dp->config.bpp / 8);
1537 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1538 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1540 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MIN_BYTES_PER_TU,
1541 avg_bytes_per_tu / 1000);
1542 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_FRAC_BYTES_PER_TU,
1543 avg_bytes_per_tu % 1000);
1545 /* Configure the initial wait cycle based on transfer unit size */
1546 if (tu < (avg_bytes_per_tu / 1000))
1548 else if ((avg_bytes_per_tu / 1000) <= 4)
1551 init_wait = tu - avg_bytes_per_tu / 1000;
1553 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_INIT_WAIT, init_wait);
1557 * xilinx_drm_dp_mode_set_stream - Configure the main stream
1558 * @dp: DisplayPort IP core structure
1559 * @mode: requested display mode
1561 * Configure the main stream based on the requested mode @mode. Calculation is
1562 * based on IP core specification.
1564 static void xilinx_drm_dp_mode_set_stream(struct xilinx_drm_dp *dp,
1565 struct drm_display_mode *mode)
1567 u8 lane_cnt = dp->mode.lane_cnt;
1570 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HTOTAL,
1572 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VTOTAL,
1575 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_POLARITY,
1576 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1577 XILINX_DP_TX_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1578 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1579 XILINX_DP_TX_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1581 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HSWIDTH,
1582 mode->hsync_end - mode->hsync_start);
1583 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VSWIDTH,
1584 mode->vsync_end - mode->vsync_start);
1586 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HRES,
1588 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VRES,
1591 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HSTART,
1592 mode->htotal - mode->hsync_start);
1593 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VSTART,
1594 mode->vtotal - mode->vsync_start);
1596 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_MISC0,
1598 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_MISC1,
1601 /* In synchronous mode, set the diviers */
1602 if (dp->config.misc0 & XILINX_DP_TX_MAIN_STREAM_MISC0_SYNC) {
1603 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1604 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_N_VID, reg);
1605 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_M_VID, mode->clock);
1607 int aud_rate = clk_get_rate(dp->aud_clk);
1609 dev_dbg(dp->dev, "Audio rate: %d\n", aud_rate / 512);
1611 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_AUDIO_N_AUD,
1613 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_AUDIO_M_AUD,
1618 /* Only 2 channel is supported now */
1620 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_AUDIO_CHANNELS, 1);
1622 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_USER_PIXEL_WIDTH, 1);
1624 /* Translate to the native 16 bit datapath based on IP core spec */
1625 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1626 reg = wpl + wpl % lane_cnt - lane_cnt;
1627 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_USER_DATA_CNT_PER_LANE, reg);
1630 static void xilinx_drm_dp_mode_set(struct drm_encoder *encoder,
1631 struct drm_display_mode *mode,
1632 struct drm_display_mode *adjusted_mode)
1634 struct xilinx_drm_dp *dp = to_dp(encoder);
1637 ret = xilinx_drm_dp_mode_configure(dp, adjusted_mode->clock, 0);
1641 xilinx_drm_dp_mode_set_stream(dp, adjusted_mode);
1642 xilinx_drm_dp_mode_set_transfer_unit(dp, adjusted_mode);
1645 static enum drm_connector_status
1646 xilinx_drm_dp_detect(struct drm_encoder *encoder,
1647 struct drm_connector *connector)
1649 struct xilinx_drm_dp *dp = to_dp(encoder);
1650 struct xilinx_drm_dp_link_config *link_config = &dp->link_config;
1654 state = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_INTR_SIGNAL_STATE);
1655 if (state & XILINX_DP_TX_INTR_SIGNAL_STATE_HPD) {
1656 dp->status = connector_status_connected;
1657 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1662 link_config->max_rate = min_t(int,
1663 drm_dp_max_link_rate(dp->dpcd),
1664 dp->config.max_link_rate);
1665 link_config->max_lanes = min_t(u8,
1666 drm_dp_max_lane_count(dp->dpcd),
1667 dp->config.max_lanes);
1672 dp->status = connector_status_disconnected;
1676 static int xilinx_drm_dp_get_modes(struct drm_encoder *encoder,
1677 struct drm_connector *connector)
1679 struct xilinx_drm_dp *dp = to_dp(encoder);
1683 edid = drm_get_edid(connector, &dp->aux.ddc);
1687 drm_mode_connector_update_edid_property(connector, edid);
1688 ret = drm_add_edid_modes(connector, edid);
1695 static struct drm_encoder_slave_funcs xilinx_drm_dp_encoder_funcs = {
1696 .dpms = xilinx_drm_dp_dpms,
1697 .save = xilinx_drm_dp_save,
1698 .restore = xilinx_drm_dp_restore,
1699 .mode_fixup = xilinx_drm_dp_mode_fixup,
1700 .mode_valid = xilinx_drm_dp_mode_valid,
1701 .mode_set = xilinx_drm_dp_mode_set,
1702 .detect = xilinx_drm_dp_detect,
1703 .get_modes = xilinx_drm_dp_get_modes,
1706 static int xilinx_drm_dp_encoder_init(struct platform_device *pdev,
1707 struct drm_device *dev,
1708 struct drm_encoder_slave *encoder)
1710 struct xilinx_drm_dp *dp = platform_get_drvdata(pdev);
1712 encoder->slave_priv = dp;
1713 encoder->slave_funcs = &xilinx_drm_dp_encoder_funcs;
1715 dp->encoder = &encoder->base;
1717 return xilinx_drm_dp_init_aux(dp);
1720 static irqreturn_t xilinx_drm_dp_irq_handler(int irq, void *data)
1722 struct xilinx_drm_dp *dp = (struct xilinx_drm_dp *)data;
1726 XILINX_DP_SUB_TX_INTR_STATUS : XILINX_DP_TX_INTR_STATUS;
1727 status = xilinx_drm_readl(dp->iomem, reg);
1731 if (status & XILINX_DP_TX_INTR_CHBUF_UNDERFLW_MASK)
1732 dev_dbg(dp->dev, "underflow interrupt\n");
1733 if (status & XILINX_DP_TX_INTR_CHBUF_OVERFLW_MASK)
1734 dev_dbg(dp->dev, "overflow interrupt\n");
1736 xilinx_drm_writel(dp->iomem, reg, status);
1738 if (status & XILINX_DP_TX_INTR_VBLANK_START)
1739 xilinx_drm_dp_sub_handle_vblank(dp->dp_sub);
1741 if (status & XILINX_DP_TX_INTR_HPD_EVENT)
1742 drm_helper_hpd_irq_event(dp->encoder->dev);
1744 if (status & XILINX_DP_TX_INTR_HPD_IRQ) {
1745 u8 status[DP_LINK_STATUS_SIZE + 2];
1748 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
1749 DP_LINK_STATUS_SIZE + 2);
1753 if (status[4] & DP_LINK_STATUS_UPDATED ||
1754 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
1755 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt))
1756 xilinx_drm_dp_train_loop(dp);
1764 xilinx_drm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1766 struct xilinx_drm_dp *dp = container_of(aux, struct xilinx_drm_dp, aux);
1768 unsigned int i, iter;
1770 /* Number of loops = timeout in msec / aux delay (400 usec) */
1771 iter = xilinx_drm_dp_aux_timeout_ms * 1000 / 400;
1772 iter = iter ? iter : 1;
1774 for (i = 0; i < iter; i++) {
1775 ret = xilinx_drm_dp_aux_cmd_submit(dp, msg->request,
1776 msg->address, msg->buffer,
1777 msg->size, &msg->reply);
1779 dev_dbg(dp->dev, "aux %d retries\n", i);
1783 if (dp->status == connector_status_disconnected) {
1784 dev_dbg(dp->dev, "no aux dev\n");
1788 usleep_range(400, 500);
1791 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1796 static int xilinx_drm_dp_parse_of(struct xilinx_drm_dp *dp)
1798 struct device_node *node = dp->dev->of_node;
1799 struct xilinx_drm_dp_config *config = &dp->config;
1801 u32 num_colors, bpc;
1805 ret = of_property_read_string(node, "xlnx,dp-version", &string);
1807 dev_err(dp->dev, "No DP version in DT\n");
1811 if (strcmp(string, "v1.1a") == 0) {
1812 config->dp_version = DP_V1_1A;
1813 } else if (strcmp(string, "v1.2") == 0) {
1814 config->dp_version = DP_V1_2;
1816 dev_err(dp->dev, "Invalid DP version in DT\n");
1820 ret = of_property_read_u32(node, "xlnx,max-lanes", &config->max_lanes);
1822 dev_err(dp->dev, "No lane count in DT\n");
1826 if (config->max_lanes != 1 && config->max_lanes != 2 &&
1827 config->max_lanes != 4) {
1828 dev_err(dp->dev, "Invalid max lanes in DT\n");
1832 ret = of_property_read_u32(node, "xlnx,max-link-rate",
1833 &config->max_link_rate);
1835 dev_err(dp->dev, "No link rate in DT\n");
1839 if (config->max_link_rate != DP_REDUCED_BIT_RATE &&
1840 config->max_link_rate != DP_HIGH_BIT_RATE &&
1841 config->max_link_rate != DP_HIGH_BIT_RATE2) {
1842 dev_err(dp->dev, "Invalid link rate in DT\n");
1846 config->enable_yonly = of_property_read_bool(node, "xlnx,enable-yonly");
1847 config->enable_ycrcb = of_property_read_bool(node, "xlnx,enable-ycrcb");
1849 sync = of_property_read_bool(node, "xlnx,sync");
1851 config->misc0 |= XILINX_DP_TX_MAIN_STREAM_MISC0_SYNC;
1853 ret = of_property_read_string(node, "xlnx,colormetry", &string);
1855 dev_err(dp->dev, "No colormetry in DT\n");
1859 if (strcmp(string, "rgb") == 0) {
1860 config->misc0 |= XILINX_DP_MISC0_RGB;
1862 } else if (config->enable_ycrcb && strcmp(string, "ycrcb422") == 0) {
1863 config->misc0 |= XILINX_DP_MISC0_YCRCB_422;
1865 } else if (config->enable_ycrcb && strcmp(string, "ycrcb444") == 0) {
1866 config->misc0 |= XILINX_DP_MISC0_YCRCB_444;
1868 } else if (config->enable_yonly && strcmp(string, "yonly") == 0) {
1869 config->misc1 |= XILINX_DP_MISC1_Y_ONLY;
1872 dev_err(dp->dev, "Invalid colormetry in DT\n");
1876 ret = of_property_read_u32(node, "xlnx,max-bpc", &config->max_bpc);
1878 dev_err(dp->dev, "No max bpc in DT\n");
1882 if (config->max_bpc != 8 && config->max_bpc != 10 &&
1883 config->max_bpc != 12 && config->max_bpc != 16) {
1884 dev_err(dp->dev, "Invalid max bpc in DT\n");
1888 ret = of_property_read_u32(node, "xlnx,bpc", &bpc);
1890 dev_err(dp->dev, "No color depth(bpc) in DT\n");
1894 if (bpc > config->max_bpc) {
1895 dev_err(dp->dev, "Invalid color depth(bpc) in DT\n");
1901 config->misc0 |= XILINX_DP_MISC0_BPC_6;
1904 config->misc0 |= XILINX_DP_MISC0_BPC_8;
1907 config->misc0 |= XILINX_DP_MISC0_BPC_10;
1910 config->misc0 |= XILINX_DP_MISC0_BPC_12;
1913 config->misc0 |= XILINX_DP_MISC0_BPC_16;
1916 dev_err(dp->dev, "Not supported color depth in DT\n");
1920 config->bpp = num_colors * bpc;
1922 of_property_read_u32(node, "xlnx,max-pclock-frequency",
1923 &config->max_pclock);
1928 static int __maybe_unused xilinx_drm_dp_pm_suspend(struct device *dev)
1930 struct xilinx_drm_dp *dp = dev_get_drvdata(dev);
1932 xilinx_drm_dp_exit_phy(dp);
1937 static int __maybe_unused xilinx_drm_dp_pm_resume(struct device *dev)
1939 struct xilinx_drm_dp *dp = dev_get_drvdata(dev);
1941 xilinx_drm_dp_init_phy(dp);
1942 xilinx_drm_dp_init_aux(dp);
1943 drm_helper_hpd_irq_event(dp->encoder->dev);
1948 static const struct dev_pm_ops xilinx_drm_dp_pm_ops = {
1949 SET_SYSTEM_SLEEP_PM_OPS(xilinx_drm_dp_pm_suspend,
1950 xilinx_drm_dp_pm_resume)
1953 static int xilinx_drm_dp_probe(struct platform_device *pdev)
1955 struct xilinx_drm_dp *dp;
1956 struct resource *res;
1960 dp = devm_kzalloc(&pdev->dev, sizeof(*dp), GFP_KERNEL);
1964 dp->dpms = DRM_MODE_DPMS_OFF;
1965 dp->status = connector_status_disconnected;
1966 dp->dev = &pdev->dev;
1968 ret = xilinx_drm_dp_parse_of(dp);
1972 dp->aclk = devm_clk_get(dp->dev, "aclk");
1973 if (IS_ERR(dp->aclk))
1974 return PTR_ERR(dp->aclk);
1976 ret = clk_prepare_enable(dp->aclk);
1978 dev_err(dp->dev, "failed to enable the aclk\n");
1982 dp->aud_clk = devm_clk_get(dp->dev, "aud_clk");
1983 if (IS_ERR(dp->aud_clk)) {
1984 ret = PTR_ERR(dp->aud_clk);
1985 if (ret == -EPROBE_DEFER)
1988 dev_dbg(dp->dev, "failed to get the aud_clk:\n");
1991 dp->dp_sub = xilinx_drm_dp_sub_of_get(pdev->dev.of_node);
1992 if (IS_ERR(dp->dp_sub)) {
1993 ret = PTR_ERR(dp->dp_sub);
1997 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1998 dp->iomem = devm_ioremap_resource(dp->dev, res);
1999 if (IS_ERR(dp->iomem)) {
2000 ret = PTR_ERR(dp->iomem);
2004 platform_set_drvdata(pdev, dp);
2006 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_PHY_POWER_DOWN,
2007 XILINX_DP_TX_PHY_POWER_DOWN_ALL);
2008 xilinx_drm_set(dp->iomem, XILINX_DP_TX_PHY_CONFIG,
2009 XILINX_DP_TX_PHY_CONFIG_ALL_RESET);
2010 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_FORCE_SCRAMBLER_RESET, 1);
2011 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENABLE, 0);
2014 for (i = 0; i < dp->config.max_lanes; i++) {
2017 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
2018 dp->phy[i] = devm_phy_get(dp->dev, phy_name);
2019 if (IS_ERR(dp->phy[i])) {
2020 dev_err(dp->dev, "failed to get phy lane\n");
2021 ret = PTR_ERR(dp->phy[i]);
2028 ret = xilinx_drm_dp_init_phy(dp);
2032 dp->aux.name = "Xilinx DP AUX";
2033 dp->aux.dev = dp->dev;
2034 dp->aux.transfer = xilinx_drm_dp_aux_transfer;
2035 ret = drm_dp_aux_register(&dp->aux);
2037 dev_err(dp->dev, "failed to initialize DP aux\n");
2041 irq = platform_get_irq(pdev, 0);
2047 ret = devm_request_threaded_irq(dp->dev, irq, NULL,
2048 xilinx_drm_dp_irq_handler, IRQF_ONESHOT,
2049 dev_name(dp->dev), dp);
2053 version = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_VERSION);
2055 dev_info(dp->dev, "device found, version %u.%02x%x\n",
2056 ((version & XILINX_DP_TX_VERSION_MAJOR_MASK) >>
2057 XILINX_DP_TX_VERSION_MAJOR_SHIFT),
2058 ((version & XILINX_DP_TX_VERSION_MINOR_MASK) >>
2059 XILINX_DP_TX_VERSION_MINOR_SHIFT),
2060 ((version & XILINX_DP_TX_VERSION_REVISION_MASK) >>
2061 XILINX_DP_TX_VERSION_REVISION_SHIFT));
2063 version = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_CORE_ID);
2064 if (version & XILINX_DP_TX_CORE_ID_DIRECTION) {
2065 dev_err(dp->dev, "Receiver is not supported\n");
2070 dev_info(dp->dev, "Display Port, version %u.%02x%02x (tx)\n",
2071 ((version & XILINX_DP_TX_CORE_ID_MAJOR_MASK) >>
2072 XILINX_DP_TX_CORE_ID_MAJOR_SHIFT),
2073 ((version & XILINX_DP_TX_CORE_ID_MINOR_MASK) >>
2074 XILINX_DP_TX_CORE_ID_MINOR_SHIFT),
2075 ((version & XILINX_DP_TX_CORE_ID_REVISION_MASK) >>
2076 XILINX_DP_TX_CORE_ID_REVISION_SHIFT));
2078 pm_runtime_enable(dp->dev);
2080 xilinx_dp_debugfs_init(dp);
2085 drm_dp_aux_unregister(&dp->aux);
2087 xilinx_drm_dp_sub_put(dp->dp_sub);
2089 xilinx_drm_dp_exit_phy(dp);
2091 clk_disable_unprepare(dp->aclk);
2095 static int xilinx_drm_dp_remove(struct platform_device *pdev)
2097 struct xilinx_drm_dp *dp = platform_get_drvdata(pdev);
2099 pm_runtime_disable(dp->dev);
2100 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENABLE, 0);
2102 drm_dp_aux_unregister(&dp->aux);
2103 xilinx_drm_dp_exit_phy(dp);
2104 xilinx_drm_dp_sub_put(dp->dp_sub);
2106 if (dp->aud_clk && dp->aud_clk_enabled)
2107 clk_disable_unprepare(dp->aud_clk);
2108 clk_disable_unprepare(dp->aclk);
2113 static const struct of_device_id xilinx_drm_dp_of_match[] = {
2114 { .compatible = "xlnx,v-dp", },
2115 { /* end of table */ },
2117 MODULE_DEVICE_TABLE(of, xilinx_drm_dp_of_match);
2119 static struct drm_platform_encoder_driver xilinx_drm_dp_driver = {
2120 .platform_driver = {
2121 .probe = xilinx_drm_dp_probe,
2122 .remove = xilinx_drm_dp_remove,
2124 .owner = THIS_MODULE,
2125 .name = "xilinx-drm-dp",
2126 .of_match_table = xilinx_drm_dp_of_match,
2127 .pm = &xilinx_drm_dp_pm_ops,
2131 .encoder_init = xilinx_drm_dp_encoder_init,
2134 static int __init xilinx_drm_dp_init(void)
2136 return platform_driver_register(&xilinx_drm_dp_driver.platform_driver);
2139 static void __exit xilinx_drm_dp_exit(void)
2141 platform_driver_unregister(&xilinx_drm_dp_driver.platform_driver);
2144 module_init(xilinx_drm_dp_init);
2145 module_exit(xilinx_drm_dp_exit);
2147 MODULE_AUTHOR("Xilinx, Inc.");
2148 MODULE_DESCRIPTION("Xilinx DRM KMS DiplayPort Driver");
2149 MODULE_LICENSE("GPL v2");