arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU111
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU111 RevA";
  20         compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  43                 /* Another 4GB connected to PL */
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <108>; /* down */
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &dcc {
  71         status = "okay";
  72 };
  73
  74 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  75 &fpd_dma_chan1 {
  76         status = "okay";
  77 };
  78
  79 &fpd_dma_chan2 {
  80         status = "okay";
  81 };
  82
  83 &fpd_dma_chan3 {
  84         status = "okay";
  85 };
  86
  87 &fpd_dma_chan4 {
  88         status = "okay";
  89 };
  90
  91 &fpd_dma_chan5 {
  92         status = "okay";
  93 };
  94
  95 &fpd_dma_chan6 {
  96         status = "okay";
  97 };
  98
  99 &fpd_dma_chan7 {
 100         status = "okay";
 101 };
 102
 103 &fpd_dma_chan8 {
 104         status = "okay";
 105 };
 106
 107 &gem3 {
 108         status = "okay";
 109         phy-handle = <&phy0>;
 110         phy-mode = "rgmii-id";
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_gem3_default>;
 113         phy0: phy@c {
 114                 reg = <0xc>;
 115                 ti,rx-internal-delay = <0x8>;
 116                 ti,tx-internal-delay = <0xa>;
 117                 ti,fifo-depth = <0x1>;
 118                 ti,rxctrl-strap-worka;
 119         };
 120 };
 121
 122 &gpio {
 123         status = "okay";
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_gpio_default>;
 126 };
 127
 128 &gpu {
 129         status = "okay";
 130 };
 131
 132 &i2c0 {
 133         status = "okay";
 134         clock-frequency = <400000>;
 135         pinctrl-names = "default", "gpio";
 136         pinctrl-0 = <&pinctrl_i2c0_default>;
 137         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 138         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 139         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 140
 141         tca6416_u22: gpio@20 {
 142                 compatible = "ti,tca6416";
 143                 reg = <0x20>;
 144                 gpio-controller; /* interrupt not connected */
 145                 #gpio-cells = <2>;
 146                 /*
 147                  * IRQ not connected
 148                  * Lines:
 149                  * 0 - MAX6643_OT_B
 150                  * 1 - MAX6643_FANFAIL_B
 151                  * 2 - MIO26_PMU_INPUT_LS
 152                  * 4 - SFP_SI5382_INT_ALM
 153                  * 5 - IIC_MUX_RESET_B
 154                  * 6 - GEM3_EXP_RESET_B
 155                  * 10 - FMCP_HSPC_PRSNT_M2C_B
 156                  * 11 - CLK_SPI_MUX_SEL0
 157                  * 12 - CLK_SPI_MUX_SEL1
 158                  * 16 - IRPS5401_ALERT_B
 159                  * 17 - INA226_PMBUS_ALERT
 160                  * 3, 7, 13-15 - not connected
 161                  */
 162         };
 163
 164         i2c-mux@75 { /* u23 */
 165                 compatible = "nxp,pca9544";
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168                 reg = <0x75>;
 169                 i2c@0 {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         reg = <0>;
 173                         /* PS_PMBUS */
 174                         /* PMBUS_ALERT done via pca9544 */
 175                         ina226@40 { /* u67 */
 176                                 compatible = "ti,ina226";
 177                                 reg = <0x40>;
 178                                 shunt-resistor = <2000>;
 179                         };
 180                         ina226@41 { /* u59 */
 181                                 compatible = "ti,ina226";
 182                                 reg = <0x41>;
 183                                 shunt-resistor = <5000>;
 184                         };
 185                         ina226@42 { /* u61 */
 186                                 compatible = "ti,ina226";
 187                                 reg = <0x42>;
 188                                 shunt-resistor = <5000>;
 189                         };
 190                         ina226@43 { /* u60 */
 191                                 compatible = "ti,ina226";
 192                                 reg = <0x43>;
 193                                 shunt-resistor = <5000>;
 194                         };
 195                         ina226@45 { /* u64 */
 196                                 compatible = "ti,ina226";
 197                                 reg = <0x45>;
 198                                 shunt-resistor = <5000>;
 199                         };
 200                         ina226@46 { /* u69 */
 201                                 compatible = "ti,ina226";
 202                                 reg = <0x46>;
 203                                 shunt-resistor = <2000>;
 204                         };
 205                         ina226@47 { /* u66 */
 206                                 compatible = "ti,ina226";
 207                                 reg = <0x47>;
 208                                 shunt-resistor = <5000>;
 209                         };
 210                         ina226@48 { /* u65 */
 211                                 compatible = "ti,ina226";
 212                                 reg = <0x48>;
 213                                 shunt-resistor = <5000>;
 214                         };
 215                         ina226@49 { /* u63 */
 216                                 compatible = "ti,ina226";
 217                                 reg = <0x49>;
 218                                 shunt-resistor = <5000>;
 219                         };
 220                         ina226@4a { /* u3 */
 221                                 compatible = "ti,ina226";
 222                                 reg = <0x4a>;
 223                                 shunt-resistor = <5000>;
 224                         };
 225                         ina226@4b { /* u71 */
 226                                 compatible = "ti,ina226";
 227                                 reg = <0x4b>;
 228                                 shunt-resistor = <5000>;
 229                         };
 230                         ina226@4c { /* u77 */
 231                                 compatible = "ti,ina226";
 232                                 reg = <0x4c>;
 233                                 shunt-resistor = <5000>;
 234                         };
 235                         ina226@4d { /* u73 */
 236                                 compatible = "ti,ina226";
 237                                 reg = <0x4d>;
 238                                 shunt-resistor = <5000>;
 239                         };
 240                         ina226@4e { /* u79 */
 241                                 compatible = "ti,ina226";
 242                                 reg = <0x4e>;
 243                                 shunt-resistor = <5000>;
 244                         };
 245                 };
 246                 i2c@1 {
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         reg = <1>;
 250                         /* NC */
 251                 };
 252                 i2c@2 {
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         reg = <2>;
 256                         irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these   */
 257                                 #clock-cells = <0>;
 258                                 compatible = "infineon,irps5401";
 259                                 reg = <0x43>;
 260                         };
 261                         irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
 262                                 #clock-cells = <0>;
 263                                 compatible = "infineon,irps5401";
 264                                 reg = <0x44>;
 265                         };
 266                         irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
 267                                 #clock-cells = <0>;
 268                                 compatible = "infineon,irps5401";
 269                                 reg = <0x45>;
 270                         };
 271                         /* u68 IR38064 +0 */
 272                         /* u70 IR38060 +1 */
 273                         /* u74 IR38060 +2 */
 274                         /* u75 IR38060 +6 */
 275                         /* J19 header too */
 276
 277                 };
 278                 i2c@3 {
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         reg = <3>;
 282                         /* SYSMON */
 283                 };
 284         };
 285 };
 286
 287 &i2c1 {
 288         status = "okay";
 289         clock-frequency = <400000>;
 290         pinctrl-names = "default", "gpio";
 291         pinctrl-0 = <&pinctrl_i2c1_default>;
 292         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 293         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 294         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 295
 296         i2c-mux@74 { /* u26 */
 297                 compatible = "nxp,pca9548";
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 reg = <0x74>;
 301                 i2c@0 {
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304                         reg = <0>;
 305                         /*
 306                          * IIC_EEPROM 1kB memory which uses 256B blocks
 307                          * where every block has different address.
 308                          *    0 - 256B address 0x54
 309                          * 256B - 512B address 0x55
 310                          * 512B - 768B address 0x56
 311                          * 768B - 1024B address 0x57
 312                          */
 313                         eeprom: eeprom@54 { /* u88 */
 314                                 compatible = "atmel,24c08";
 315                                 reg = <0x54>;
 316                         };
 317                 };
 318                 i2c@1 {
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         reg = <1>;
 322                         si5341: clock-generator@36 { /* SI5341 - u46 */
 323                                 compatible = "si5341";
 324                                 reg = <0x36>;
 325                         };
 326
 327                 };
 328                 i2c@2 {
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                         reg = <2>;
 332                         si570_1: clock-generator@5d { /* USER SI570 - u47 */
 333                                 #clock-cells = <0>;
 334                                 compatible = "silabs,si570";
 335                                 reg = <0x5d>;
 336                                 temperature-stability = <50>;
 337                                 factory-fout = <300000000>;
 338                                 clock-frequency = <300000000>;
 339                         };
 340                 };
 341                 i2c@3 {
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         reg = <3>;
 345                         si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
 346                                 #clock-cells = <0>;
 347                                 compatible = "silabs,si570";
 348                                 reg = <0x5d>;
 349                                 temperature-stability = <50>;
 350                                 factory-fout = <156250000>;
 351                                 clock-frequency = <148500000>;
 352                         };
 353                 };
 354                 i2c@4 {
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         reg = <4>;
 358                         si5328: clock-generator@69 { /* SI5328 - u48 */
 359                                 compatible = "silabs,si5328";
 360                                 reg = <0x69>;
 361                         };
 362                 };
 363                 i2c@5 {
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         reg = <5>;
 367                                 sc18is603@2f { /* sc18is602 - u93 */
 368                                         compatible = "nxp,sc18is603";
 369                                         reg = <0x2f>;
 370                                         /* 4 gpios for CS not handled by driver */
 371                                         /*
 372                                          * USB2ANY cable or
 373                                          * LMK04208 - u90 or
 374                                          * LMX2594 - u102 or
 375                                          * LMX2594 - u103 or
 376                                          * LMX2594 - u104
 377                                          */
 378                                 };
 379                 };
 380                 i2c@6 {
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         reg = <6>;
 384                         /* FMC connector */
 385                 };
 386                 /* 7 NC */
 387         };
 388
 389         i2c-mux@75 {
 390                 compatible = "nxp,pca9548"; /* u27 */
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 reg = <0x75>;
 394
 395                 i2c@0 {
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         reg = <0>;
 399                         /* FMCP_HSPC_IIC */
 400                 };
 401                 i2c@1 {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         reg = <1>;
 405                         /* NC */
 406                 };
 407                 i2c@2 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         reg = <2>;
 411                         /* SYSMON */
 412                 };
 413                 i2c@3 {
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         reg = <3>;
 417                         /* DDR4 SODIMM */
 418                         dev@19 { /* u-boot detection FIXME */
 419                                 compatible = "xxx";
 420                                 reg = <0x19>;
 421                         };
 422                         dev@30 { /* u-boot detection */
 423                                 compatible = "xxx";
 424                                 reg = <0x30>;
 425                         };
 426                         dev@35 { /* u-boot detection */
 427                                 compatible = "xxx";
 428                                 reg = <0x35>;
 429                         };
 430                         dev@36 { /* u-boot detection */
 431                                 compatible = "xxx";
 432                                 reg = <0x36>;
 433                         };
 434                         dev@51 { /* u-boot detection - maybe SPD */
 435                                 compatible = "xxx";
 436                                 reg = <0x51>;
 437                         };
 438                 };
 439                 i2c@4 {
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         reg = <4>;
 443                         /* SFP3 */
 444                 };
 445                 i2c@5 {
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         reg = <5>;
 449                         /* SFP2 */
 450                 };
 451                 i2c@6 {
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         reg = <6>;
 455                         /* SFP1 */
 456                 };
 457                 i2c@7 {
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         reg = <7>;
 461                         /* SFP0 */
 462                 };
 463         };
 464 };
 465
 466 &pinctrl0 {
 467         status = "okay";
 468         pinctrl_i2c0_default: i2c0-default {
 469                 mux {
 470                         groups = "i2c0_3_grp";
 471                         function = "i2c0";
 472                 };
 473
 474                 conf {
 475                         groups = "i2c0_3_grp";
 476                         bias-pull-up;
 477                         slew-rate = <SLEW_RATE_SLOW>;
 478                         io-standard = <IO_STANDARD_LVCMOS18>;
 479                 };
 480         };
 481
 482         pinctrl_i2c0_gpio: i2c0-gpio {
 483                 mux {
 484                         groups = "gpio0_14_grp", "gpio0_15_grp";
 485                         function = "gpio0";
 486                 };
 487
 488                 conf {
 489                         groups = "gpio0_14_grp", "gpio0_15_grp";
 490                         slew-rate = <SLEW_RATE_SLOW>;
 491                         io-standard = <IO_STANDARD_LVCMOS18>;
 492                 };
 493         };
 494
 495         pinctrl_i2c1_default: i2c1-default {
 496                 mux {
 497                         groups = "i2c1_4_grp";
 498                         function = "i2c1";
 499                 };
 500
 501                 conf {
 502                         groups = "i2c1_4_grp";
 503                         bias-pull-up;
 504                         slew-rate = <SLEW_RATE_SLOW>;
 505                         io-standard = <IO_STANDARD_LVCMOS18>;
 506                 };
 507         };
 508
 509         pinctrl_i2c1_gpio: i2c1-gpio {
 510                 mux {
 511                         groups = "gpio0_16_grp", "gpio0_17_grp";
 512                         function = "gpio0";
 513                 };
 514
 515                 conf {
 516                         groups = "gpio0_16_grp", "gpio0_17_grp";
 517                         slew-rate = <SLEW_RATE_SLOW>;
 518                         io-standard = <IO_STANDARD_LVCMOS18>;
 519                 };
 520         };
 521
 522         pinctrl_uart0_default: uart0-default {
 523                 mux {
 524                         groups = "uart0_4_grp";
 525                         function = "uart0";
 526                 };
 527
 528                 conf {
 529                         groups = "uart0_4_grp";
 530                         slew-rate = <SLEW_RATE_SLOW>;
 531                         io-standard = <IO_STANDARD_LVCMOS18>;
 532                 };
 533
 534                 conf-rx {
 535                         pins = "MIO18";
 536                         bias-high-impedance;
 537                 };
 538
 539                 conf-tx {
 540                         pins = "MIO19";
 541                         bias-disable;
 542                 };
 543         };
 544
 545         pinctrl_usb0_default: usb0-default {
 546                 mux {
 547                         groups = "usb0_0_grp";
 548                         function = "usb0";
 549                 };
 550
 551                 conf {
 552                         groups = "usb0_0_grp";
 553                         slew-rate = <SLEW_RATE_SLOW>;
 554                         io-standard = <IO_STANDARD_LVCMOS18>;
 555                 };
 556
 557                 conf-rx {
 558                         pins = "MIO52", "MIO53", "MIO55";
 559                         bias-high-impedance;
 560                 };
 561
 562                 conf-tx {
 563                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 564                                "MIO60", "MIO61", "MIO62", "MIO63";
 565                         bias-disable;
 566                 };
 567         };
 568
 569         pinctrl_gem3_default: gem3-default {
 570                 mux {
 571                         function = "ethernet3";
 572                         groups = "ethernet3_0_grp";
 573                 };
 574
 575                 conf {
 576                         groups = "ethernet3_0_grp";
 577                         slew-rate = <SLEW_RATE_SLOW>;
 578                         io-standard = <IO_STANDARD_LVCMOS18>;
 579                 };
 580
 581                 conf-rx {
 582                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 583                                                                         "MIO75";
 584                         bias-high-impedance;
 585                         low-power-disable;
 586                 };
 587
 588                 conf-tx {
 589                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 590                                                                         "MIO69";
 591                         bias-disable;
 592                         low-power-enable;
 593                 };
 594
 595                 mux-mdio {
 596                         function = "mdio3";
 597                         groups = "mdio3_0_grp";
 598                 };
 599
 600                 conf-mdio {
 601                         groups = "mdio3_0_grp";
 602                         slew-rate = <SLEW_RATE_SLOW>;
 603                         io-standard = <IO_STANDARD_LVCMOS18>;
 604                         bias-disable;
 605                 };
 606         };
 607
 608         pinctrl_sdhci1_default: sdhci1-default {
 609                 mux {
 610                         groups = "sdio1_0_grp";
 611                         function = "sdio1";
 612                 };
 613
 614                 conf {
 615                         groups = "sdio1_0_grp";
 616                         slew-rate = <SLEW_RATE_SLOW>;
 617                         io-standard = <IO_STANDARD_LVCMOS18>;
 618                         bias-disable;
 619                 };
 620
 621                 mux-cd {
 622                         groups = "sdio1_cd_0_grp";
 623                         function = "sdio1_cd";
 624                 };
 625
 626                 conf-cd {
 627                         groups = "sdio1_cd_0_grp";
 628                         bias-high-impedance;
 629                         bias-pull-up;
 630                         slew-rate = <SLEW_RATE_SLOW>;
 631                         io-standard = <IO_STANDARD_LVCMOS18>;
 632                 };
 633         };
 634
 635         pinctrl_gpio_default: gpio-default {
 636                 mux {
 637                         function = "gpio0";
 638                         groups = "gpio0_22_grp", "gpio0_23_grp";
 639                 };
 640
 641                 conf {
 642                         groups = "gpio0_22_grp", "gpio0_23_grp";
 643                         slew-rate = <SLEW_RATE_SLOW>;
 644                         io-standard = <IO_STANDARD_LVCMOS18>;
 645                 };
 646
 647                 mux-msp {
 648                         function = "gpio0";
 649                         groups = "gpio0_13_grp", "gpio0_38_grp";
 650                 };
 651
 652                 conf-msp {
 653                         groups = "gpio0_13_grp", "gpio0_38_grp";
 654                         slew-rate = <SLEW_RATE_SLOW>;
 655                         io-standard = <IO_STANDARD_LVCMOS18>;
 656                 };
 657
 658                 conf-pull-up {
 659                         pins = "MIO22";
 660                         bias-pull-up;
 661                 };
 662
 663                 conf-pull-none {
 664                         pins = "MIO13", "MIO23", "MIO38";
 665                         bias-disable;
 666                 };
 667         };
 668 };
 669
 670 &qspi {
 671         status = "okay";
 672         is-dual = <1>;
 673         flash@0 {
 674                 compatible = "m25p80"; /* 32MB */
 675                 #address-cells = <1>;
 676                 #size-cells = <1>;
 677                 reg = <0x0>;
 678                 spi-tx-bus-width = <1>;
 679                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 680                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 681                 partition@qspi-fsbl-uboot { /* for testing purpose */
 682                         label = "qspi-fsbl-uboot";
 683                         reg = <0x0 0x100000>;
 684                 };
 685                 partition@qspi-linux { /* for testing purpose */
 686                         label = "qspi-linux";
 687                         reg = <0x100000 0x500000>;
 688                 };
 689                 partition@qspi-device-tree { /* for testing purpose */
 690                         label = "qspi-device-tree";
 691                         reg = <0x600000 0x20000>;
 692                 };
 693                 partition@qspi-rootfs { /* for testing purpose */
 694                         label = "qspi-rootfs";
 695                         reg = <0x620000 0x5E0000>;
 696                 };
 697         };
 698 };
 699
 700 &rtc {
 701         status = "okay";
 702 };
 703
 704 &sata {
 705         status = "okay";
 706         /* SATA OOB timing settings */
 707         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 708         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 709         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 710         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 711         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 712         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 713         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 714         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 715         phy-names = "sata-phy";
 716         phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
 717 };
 718
 719 /* SD1 with level shifter */
 720 &sdhci1 {
 721         status = "okay";
 722         pinctrl-names = "default";
 723         pinctrl-0 = <&pinctrl_sdhci1_default>;
 724         no-1-8-v;
 725         disable-wp;
 726         xlnx,mio_bank = <1>;
 727 };
 728
 729 &serdes {
 730         status = "okay";
 731 };
 732
 733 &uart0 {
 734         status = "okay";
 735         pinctrl-names = "default";
 736         pinctrl-0 = <&pinctrl_uart0_default>;
 737 };
 738
 739 /* ULPI SMSC USB3320 */
 740 &usb0 {
 741         status = "okay";
 742         pinctrl-names = "default";
 743         pinctrl-0 = <&pinctrl_usb0_default>;
 744 };
 745
 746 &dwc3_0 {
 747         status = "okay";
 748         dr_mode = "host";
 749         snps,usb3_lpm_capable;
 750         phy-names = "usb3-phy";
 751         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 752 };
 753
 754 &zynqmp_dpsub {
 755         status = "okay";
 756         phy-names = "dp-phy0", "dp-phy1";
 757         phys = <&lane1 PHY_TYPE_DP 0 1 27000000>, <&lane0 PHY_TYPE_DP 1 1 27000000>;
 758 };
 759
 760 &zynqmp_dp_snd_pcm0 {
 761         status = "okay";
 762 };
 763
 764 &zynqmp_dp_snd_pcm1 {
 765         status = "okay";
 766 };
 767
 768 &zynqmp_dp_snd_card0 {
 769         status = "okay";
 770 };
 771
 772 &zynqmp_dp_snd_codec0 {
 773         status = "okay";
 774 };
 775
 776 &xlnx_dpdma {
 777         status = "okay";
 778 };