2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
46 #include <asm/cmpxchg.h>
49 #include <asm/kvm_page_track.h>
53 * When setting this variable to true it enables Two-Dimensional-Paging
54 * where the hardware walks 2 page tables:
55 * 1. the guest-virtual to guest-physical
56 * 2. while doing 1. it walks guest-physical to host-physical
57 * If the hardware supports that we don't need to do shadow paging.
59 bool tdp_enabled = false;
63 AUDIT_POST_PAGE_FAULT,
74 module_param(dbg, bool, 0644);
76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
78 #define MMU_WARN_ON(x) WARN_ON(x)
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
82 #define MMU_WARN_ON(x) do { } while (0)
85 #define PTE_PREFETCH_NUM 8
87 #define PT_FIRST_AVAIL_BITS_SHIFT 10
88 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
90 #define PT64_LEVEL_BITS 9
92 #define PT64_LEVEL_SHIFT(level) \
93 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
95 #define PT64_INDEX(address, level)\
96 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
99 #define PT32_LEVEL_BITS 10
101 #define PT32_LEVEL_SHIFT(level) \
102 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
104 #define PT32_LVL_OFFSET_MASK(level) \
105 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
106 * PT32_LEVEL_BITS))) - 1))
108 #define PT32_INDEX(address, level)\
109 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
112 #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
113 #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
115 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
117 #define PT64_LVL_ADDR_MASK(level) \
118 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
119 * PT64_LEVEL_BITS))) - 1))
120 #define PT64_LVL_OFFSET_MASK(level) \
121 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT64_LEVEL_BITS))) - 1))
124 #define PT32_BASE_ADDR_MASK PAGE_MASK
125 #define PT32_DIR_BASE_ADDR_MASK \
126 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
127 #define PT32_LVL_ADDR_MASK(level) \
128 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
129 * PT32_LEVEL_BITS))) - 1))
131 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
132 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
134 #define ACC_EXEC_MASK 1
135 #define ACC_WRITE_MASK PT_WRITABLE_MASK
136 #define ACC_USER_MASK PT_USER_MASK
137 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
139 /* The mask for the R/X bits in EPT PTEs */
140 #define PT64_EPT_READABLE_MASK 0x1ull
141 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
157 * Return values of handle_mmio_page_fault and mmu.page_fault:
158 * RET_PF_RETRY: let CPU fault again on the address.
159 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
161 * For handle_mmio_page_fault only:
162 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
170 struct pte_list_desc {
171 u64 *sptes[PTE_LIST_EXT];
172 struct pte_list_desc *more;
175 struct kvm_shadow_walk_iterator {
183 static const union kvm_mmu_page_role mmu_base_role_mask = {
194 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
195 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
197 shadow_walk_okay(&(_walker)); \
198 shadow_walk_next(&(_walker)))
200 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
201 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
202 shadow_walk_okay(&(_walker)); \
203 shadow_walk_next(&(_walker)))
205 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
206 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
207 shadow_walk_okay(&(_walker)) && \
208 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
209 __shadow_walk_next(&(_walker), spte))
211 static struct kmem_cache *pte_list_desc_cache;
212 static struct kmem_cache *mmu_page_header_cache;
213 static struct percpu_counter kvm_total_used_mmu_pages;
215 static u64 __read_mostly shadow_nx_mask;
216 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
217 static u64 __read_mostly shadow_user_mask;
218 static u64 __read_mostly shadow_accessed_mask;
219 static u64 __read_mostly shadow_dirty_mask;
220 static u64 __read_mostly shadow_mmio_mask;
221 static u64 __read_mostly shadow_mmio_value;
222 static u64 __read_mostly shadow_present_mask;
223 static u64 __read_mostly shadow_me_mask;
226 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
227 * Non-present SPTEs with shadow_acc_track_value set are in place for access
230 static u64 __read_mostly shadow_acc_track_mask;
231 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
234 * The mask/shift to use for saving the original R/X bits when marking the PTE
235 * as not-present for access tracking purposes. We do not save the W bit as the
236 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
237 * restored only when a write is attempted to the page.
239 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
240 PT64_EPT_EXECUTABLE_MASK;
241 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
244 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
245 * to guard against L1TF attacks.
247 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
250 * The number of high-order 1 bits to use in the mask above.
252 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
255 * In some cases, we need to preserve the GFN of a non-present or reserved
256 * SPTE when we usurp the upper five bits of the physical address space to
257 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
258 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
259 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
260 * high and low parts. This mask covers the lower bits of the GFN.
262 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
265 static void mmu_spte_set(u64 *sptep, u64 spte);
266 static union kvm_mmu_page_role
267 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
270 static inline bool kvm_available_flush_tlb_with_range(void)
272 return kvm_x86_ops->tlb_remote_flush_with_range;
275 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
276 struct kvm_tlb_range *range)
280 if (range && kvm_x86_ops->tlb_remote_flush_with_range)
281 ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range);
284 kvm_flush_remote_tlbs(kvm);
287 static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
288 u64 start_gfn, u64 pages)
290 struct kvm_tlb_range range;
292 range.start_gfn = start_gfn;
295 kvm_flush_remote_tlbs_with_range(kvm, &range);
298 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value)
300 BUG_ON((mmio_mask & mmio_value) != mmio_value);
301 shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK;
302 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
304 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
306 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
308 return sp->role.ad_disabled;
311 static inline bool spte_ad_enabled(u64 spte)
313 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
314 return !(spte & shadow_acc_track_value);
317 static inline u64 spte_shadow_accessed_mask(u64 spte)
319 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
320 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
323 static inline u64 spte_shadow_dirty_mask(u64 spte)
325 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
326 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
329 static inline bool is_access_track_spte(u64 spte)
331 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
335 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
336 * the memslots generation and is derived as follows:
338 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
339 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61
341 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
342 * the MMIO generation number, as doing so would require stealing a bit from
343 * the "real" generation number and thus effectively halve the maximum number
344 * of MMIO generations that can be handled before encountering a wrap (which
345 * requires a full MMU zap). The flag is instead explicitly queried when
346 * checking for MMIO spte cache hits.
348 #define MMIO_SPTE_GEN_MASK GENMASK_ULL(18, 0)
350 #define MMIO_SPTE_GEN_LOW_START 3
351 #define MMIO_SPTE_GEN_LOW_END 11
352 #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
353 MMIO_SPTE_GEN_LOW_START)
355 #define MMIO_SPTE_GEN_HIGH_START 52
356 #define MMIO_SPTE_GEN_HIGH_END 61
357 #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
358 MMIO_SPTE_GEN_HIGH_START)
359 static u64 generation_mmio_spte_mask(u64 gen)
363 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
365 mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;
366 mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;
370 static u64 get_mmio_spte_generation(u64 spte)
374 spte &= ~shadow_mmio_mask;
376 gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;
377 gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;
381 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
384 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
385 u64 mask = generation_mmio_spte_mask(gen);
386 u64 gpa = gfn << PAGE_SHIFT;
388 access &= ACC_WRITE_MASK | ACC_USER_MASK;
389 mask |= shadow_mmio_value | access;
390 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
391 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
392 << shadow_nonpresent_or_rsvd_mask_len;
394 page_header(__pa(sptep))->mmio_cached = true;
396 trace_mark_mmio_spte(sptep, gfn, access, gen);
397 mmu_spte_set(sptep, mask);
400 static bool is_mmio_spte(u64 spte)
402 return (spte & shadow_mmio_mask) == shadow_mmio_value;
405 static gfn_t get_mmio_spte_gfn(u64 spte)
407 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
409 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
410 & shadow_nonpresent_or_rsvd_mask;
412 return gpa >> PAGE_SHIFT;
415 static unsigned get_mmio_spte_access(u64 spte)
417 u64 mask = generation_mmio_spte_mask(MMIO_SPTE_GEN_MASK) | shadow_mmio_mask;
418 return (spte & ~mask) & ~PAGE_MASK;
421 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
422 kvm_pfn_t pfn, unsigned access)
424 if (unlikely(is_noslot_pfn(pfn))) {
425 mark_mmio_spte(vcpu, sptep, gfn, access);
432 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
434 u64 kvm_gen, spte_gen, gen;
436 gen = kvm_vcpu_memslots(vcpu)->generation;
437 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
440 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
441 spte_gen = get_mmio_spte_generation(spte);
443 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
444 return likely(kvm_gen == spte_gen);
448 * Sets the shadow PTE masks used by the MMU.
451 * - Setting either @accessed_mask or @dirty_mask requires setting both
452 * - At least one of @accessed_mask or @acc_track_mask must be set
454 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
455 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
456 u64 acc_track_mask, u64 me_mask)
458 BUG_ON(!dirty_mask != !accessed_mask);
459 BUG_ON(!accessed_mask && !acc_track_mask);
460 BUG_ON(acc_track_mask & shadow_acc_track_value);
462 shadow_user_mask = user_mask;
463 shadow_accessed_mask = accessed_mask;
464 shadow_dirty_mask = dirty_mask;
465 shadow_nx_mask = nx_mask;
466 shadow_x_mask = x_mask;
467 shadow_present_mask = p_mask;
468 shadow_acc_track_mask = acc_track_mask;
469 shadow_me_mask = me_mask;
471 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
473 static void kvm_mmu_reset_all_pte_masks(void)
477 shadow_user_mask = 0;
478 shadow_accessed_mask = 0;
479 shadow_dirty_mask = 0;
482 shadow_mmio_mask = 0;
483 shadow_present_mask = 0;
484 shadow_acc_track_mask = 0;
487 * If the CPU has 46 or less physical address bits, then set an
488 * appropriate mask to guard against L1TF attacks. Otherwise, it is
489 * assumed that the CPU is not vulnerable to L1TF.
491 low_phys_bits = boot_cpu_data.x86_phys_bits;
492 if (boot_cpu_data.x86_phys_bits <
493 52 - shadow_nonpresent_or_rsvd_mask_len) {
494 shadow_nonpresent_or_rsvd_mask =
495 rsvd_bits(boot_cpu_data.x86_phys_bits -
496 shadow_nonpresent_or_rsvd_mask_len,
497 boot_cpu_data.x86_phys_bits - 1);
498 low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len;
500 shadow_nonpresent_or_rsvd_lower_gfn_mask =
501 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
504 static int is_cpuid_PSE36(void)
509 static int is_nx(struct kvm_vcpu *vcpu)
511 return vcpu->arch.efer & EFER_NX;
514 static int is_shadow_present_pte(u64 pte)
516 return (pte != 0) && !is_mmio_spte(pte);
519 static int is_large_pte(u64 pte)
521 return pte & PT_PAGE_SIZE_MASK;
524 static int is_last_spte(u64 pte, int level)
526 if (level == PT_PAGE_TABLE_LEVEL)
528 if (is_large_pte(pte))
533 static bool is_executable_pte(u64 spte)
535 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
538 static kvm_pfn_t spte_to_pfn(u64 pte)
540 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
543 static gfn_t pse36_gfn_delta(u32 gpte)
545 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
547 return (gpte & PT32_DIR_PSE36_MASK) << shift;
551 static void __set_spte(u64 *sptep, u64 spte)
553 WRITE_ONCE(*sptep, spte);
556 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
558 WRITE_ONCE(*sptep, spte);
561 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
563 return xchg(sptep, spte);
566 static u64 __get_spte_lockless(u64 *sptep)
568 return READ_ONCE(*sptep);
579 static void count_spte_clear(u64 *sptep, u64 spte)
581 struct kvm_mmu_page *sp = page_header(__pa(sptep));
583 if (is_shadow_present_pte(spte))
586 /* Ensure the spte is completely set before we increase the count */
588 sp->clear_spte_count++;
591 static void __set_spte(u64 *sptep, u64 spte)
593 union split_spte *ssptep, sspte;
595 ssptep = (union split_spte *)sptep;
596 sspte = (union split_spte)spte;
598 ssptep->spte_high = sspte.spte_high;
601 * If we map the spte from nonpresent to present, We should store
602 * the high bits firstly, then set present bit, so cpu can not
603 * fetch this spte while we are setting the spte.
607 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
610 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
612 union split_spte *ssptep, sspte;
614 ssptep = (union split_spte *)sptep;
615 sspte = (union split_spte)spte;
617 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
620 * If we map the spte from present to nonpresent, we should clear
621 * present bit firstly to avoid vcpu fetch the old high bits.
625 ssptep->spte_high = sspte.spte_high;
626 count_spte_clear(sptep, spte);
629 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
631 union split_spte *ssptep, sspte, orig;
633 ssptep = (union split_spte *)sptep;
634 sspte = (union split_spte)spte;
636 /* xchg acts as a barrier before the setting of the high bits */
637 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
638 orig.spte_high = ssptep->spte_high;
639 ssptep->spte_high = sspte.spte_high;
640 count_spte_clear(sptep, spte);
646 * The idea using the light way get the spte on x86_32 guest is from
647 * gup_get_pte(arch/x86/mm/gup.c).
649 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
650 * coalesces them and we are running out of the MMU lock. Therefore
651 * we need to protect against in-progress updates of the spte.
653 * Reading the spte while an update is in progress may get the old value
654 * for the high part of the spte. The race is fine for a present->non-present
655 * change (because the high part of the spte is ignored for non-present spte),
656 * but for a present->present change we must reread the spte.
658 * All such changes are done in two steps (present->non-present and
659 * non-present->present), hence it is enough to count the number of
660 * present->non-present updates: if it changed while reading the spte,
661 * we might have hit the race. This is done using clear_spte_count.
663 static u64 __get_spte_lockless(u64 *sptep)
665 struct kvm_mmu_page *sp = page_header(__pa(sptep));
666 union split_spte spte, *orig = (union split_spte *)sptep;
670 count = sp->clear_spte_count;
673 spte.spte_low = orig->spte_low;
676 spte.spte_high = orig->spte_high;
679 if (unlikely(spte.spte_low != orig->spte_low ||
680 count != sp->clear_spte_count))
687 static bool spte_can_locklessly_be_made_writable(u64 spte)
689 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
690 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
693 static bool spte_has_volatile_bits(u64 spte)
695 if (!is_shadow_present_pte(spte))
699 * Always atomically update spte if it can be updated
700 * out of mmu-lock, it can ensure dirty bit is not lost,
701 * also, it can help us to get a stable is_writable_pte()
702 * to ensure tlb flush is not missed.
704 if (spte_can_locklessly_be_made_writable(spte) ||
705 is_access_track_spte(spte))
708 if (spte_ad_enabled(spte)) {
709 if ((spte & shadow_accessed_mask) == 0 ||
710 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
717 static bool is_accessed_spte(u64 spte)
719 u64 accessed_mask = spte_shadow_accessed_mask(spte);
721 return accessed_mask ? spte & accessed_mask
722 : !is_access_track_spte(spte);
725 static bool is_dirty_spte(u64 spte)
727 u64 dirty_mask = spte_shadow_dirty_mask(spte);
729 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
732 /* Rules for using mmu_spte_set:
733 * Set the sptep from nonpresent to present.
734 * Note: the sptep being assigned *must* be either not present
735 * or in a state where the hardware will not attempt to update
738 static void mmu_spte_set(u64 *sptep, u64 new_spte)
740 WARN_ON(is_shadow_present_pte(*sptep));
741 __set_spte(sptep, new_spte);
745 * Update the SPTE (excluding the PFN), but do not track changes in its
746 * accessed/dirty status.
748 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
750 u64 old_spte = *sptep;
752 WARN_ON(!is_shadow_present_pte(new_spte));
754 if (!is_shadow_present_pte(old_spte)) {
755 mmu_spte_set(sptep, new_spte);
759 if (!spte_has_volatile_bits(old_spte))
760 __update_clear_spte_fast(sptep, new_spte);
762 old_spte = __update_clear_spte_slow(sptep, new_spte);
764 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
769 /* Rules for using mmu_spte_update:
770 * Update the state bits, it means the mapped pfn is not changed.
772 * Whenever we overwrite a writable spte with a read-only one we
773 * should flush remote TLBs. Otherwise rmap_write_protect
774 * will find a read-only spte, even though the writable spte
775 * might be cached on a CPU's TLB, the return value indicates this
778 * Returns true if the TLB needs to be flushed
780 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
783 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
785 if (!is_shadow_present_pte(old_spte))
789 * For the spte updated out of mmu-lock is safe, since
790 * we always atomically update it, see the comments in
791 * spte_has_volatile_bits().
793 if (spte_can_locklessly_be_made_writable(old_spte) &&
794 !is_writable_pte(new_spte))
798 * Flush TLB when accessed/dirty states are changed in the page tables,
799 * to guarantee consistency between TLB and page tables.
802 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
804 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
807 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
809 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
816 * Rules for using mmu_spte_clear_track_bits:
817 * It sets the sptep from present to nonpresent, and track the
818 * state bits, it is used to clear the last level sptep.
819 * Returns non-zero if the PTE was previously valid.
821 static int mmu_spte_clear_track_bits(u64 *sptep)
824 u64 old_spte = *sptep;
826 if (!spte_has_volatile_bits(old_spte))
827 __update_clear_spte_fast(sptep, 0ull);
829 old_spte = __update_clear_spte_slow(sptep, 0ull);
831 if (!is_shadow_present_pte(old_spte))
834 pfn = spte_to_pfn(old_spte);
837 * KVM does not hold the refcount of the page used by
838 * kvm mmu, before reclaiming the page, we should
839 * unmap it from mmu first.
841 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
843 if (is_accessed_spte(old_spte))
844 kvm_set_pfn_accessed(pfn);
846 if (is_dirty_spte(old_spte))
847 kvm_set_pfn_dirty(pfn);
853 * Rules for using mmu_spte_clear_no_track:
854 * Directly clear spte without caring the state bits of sptep,
855 * it is used to set the upper level spte.
857 static void mmu_spte_clear_no_track(u64 *sptep)
859 __update_clear_spte_fast(sptep, 0ull);
862 static u64 mmu_spte_get_lockless(u64 *sptep)
864 return __get_spte_lockless(sptep);
867 static u64 mark_spte_for_access_track(u64 spte)
869 if (spte_ad_enabled(spte))
870 return spte & ~shadow_accessed_mask;
872 if (is_access_track_spte(spte))
876 * Making an Access Tracking PTE will result in removal of write access
877 * from the PTE. So, verify that we will be able to restore the write
878 * access in the fast page fault path later on.
880 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
881 !spte_can_locklessly_be_made_writable(spte),
882 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
884 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
885 shadow_acc_track_saved_bits_shift),
886 "kvm: Access Tracking saved bit locations are not zero\n");
888 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
889 shadow_acc_track_saved_bits_shift;
890 spte &= ~shadow_acc_track_mask;
895 /* Restore an acc-track PTE back to a regular PTE */
896 static u64 restore_acc_track_spte(u64 spte)
899 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
900 & shadow_acc_track_saved_bits_mask;
902 WARN_ON_ONCE(spte_ad_enabled(spte));
903 WARN_ON_ONCE(!is_access_track_spte(spte));
905 new_spte &= ~shadow_acc_track_mask;
906 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
907 shadow_acc_track_saved_bits_shift);
908 new_spte |= saved_bits;
913 /* Returns the Accessed status of the PTE and resets it at the same time. */
914 static bool mmu_spte_age(u64 *sptep)
916 u64 spte = mmu_spte_get_lockless(sptep);
918 if (!is_accessed_spte(spte))
921 if (spte_ad_enabled(spte)) {
922 clear_bit((ffs(shadow_accessed_mask) - 1),
923 (unsigned long *)sptep);
926 * Capture the dirty status of the page, so that it doesn't get
927 * lost when the SPTE is marked for access tracking.
929 if (is_writable_pte(spte))
930 kvm_set_pfn_dirty(spte_to_pfn(spte));
932 spte = mark_spte_for_access_track(spte);
933 mmu_spte_update_no_track(sptep, spte);
939 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
942 * Prevent page table teardown by making any free-er wait during
943 * kvm_flush_remote_tlbs() IPI to all active vcpus.
948 * Make sure a following spte read is not reordered ahead of the write
951 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
954 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
957 * Make sure the write to vcpu->mode is not reordered in front of
958 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
959 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
961 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
965 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
966 struct kmem_cache *base_cache, int min)
970 if (cache->nobjs >= min)
972 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
973 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT);
975 return cache->nobjs >= min ? 0 : -ENOMEM;
976 cache->objects[cache->nobjs++] = obj;
981 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
986 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
987 struct kmem_cache *cache)
990 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
993 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
998 if (cache->nobjs >= min)
1000 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1001 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
1003 return cache->nobjs >= min ? 0 : -ENOMEM;
1004 cache->objects[cache->nobjs++] = page;
1009 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
1012 free_page((unsigned long)mc->objects[--mc->nobjs]);
1015 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
1019 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1020 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
1023 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
1026 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
1027 mmu_page_header_cache, 4);
1032 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
1034 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1035 pte_list_desc_cache);
1036 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
1037 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
1038 mmu_page_header_cache);
1041 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
1046 p = mc->objects[--mc->nobjs];
1050 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
1052 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
1055 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1057 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1060 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1062 if (!sp->role.direct)
1063 return sp->gfns[index];
1065 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1068 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1070 if (sp->role.direct)
1071 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
1073 sp->gfns[index] = gfn;
1077 * Return the pointer to the large page information for a given gfn,
1078 * handling slots that are not large page aligned.
1080 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1081 struct kvm_memory_slot *slot,
1086 idx = gfn_to_index(gfn, slot->base_gfn, level);
1087 return &slot->arch.lpage_info[level - 2][idx];
1090 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1091 gfn_t gfn, int count)
1093 struct kvm_lpage_info *linfo;
1096 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1097 linfo = lpage_info_slot(gfn, slot, i);
1098 linfo->disallow_lpage += count;
1099 WARN_ON(linfo->disallow_lpage < 0);
1103 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1105 update_gfn_disallow_lpage_count(slot, gfn, 1);
1108 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1110 update_gfn_disallow_lpage_count(slot, gfn, -1);
1113 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1115 struct kvm_memslots *slots;
1116 struct kvm_memory_slot *slot;
1119 kvm->arch.indirect_shadow_pages++;
1121 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1122 slot = __gfn_to_memslot(slots, gfn);
1124 /* the non-leaf shadow pages are keeping readonly. */
1125 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1126 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1127 KVM_PAGE_TRACK_WRITE);
1129 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1132 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1134 struct kvm_memslots *slots;
1135 struct kvm_memory_slot *slot;
1138 kvm->arch.indirect_shadow_pages--;
1140 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1141 slot = __gfn_to_memslot(slots, gfn);
1142 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1143 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1144 KVM_PAGE_TRACK_WRITE);
1146 kvm_mmu_gfn_allow_lpage(slot, gfn);
1149 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1150 struct kvm_memory_slot *slot)
1152 struct kvm_lpage_info *linfo;
1155 linfo = lpage_info_slot(gfn, slot, level);
1156 return !!linfo->disallow_lpage;
1162 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1165 struct kvm_memory_slot *slot;
1167 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1168 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1171 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1173 unsigned long page_size;
1176 page_size = kvm_host_page_size(kvm, gfn);
1178 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1179 if (page_size >= KVM_HPAGE_SIZE(i))
1188 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1191 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1193 if (no_dirty_log && slot->dirty_bitmap)
1199 static struct kvm_memory_slot *
1200 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1203 struct kvm_memory_slot *slot;
1205 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1206 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1212 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1213 bool *force_pt_level)
1215 int host_level, level, max_level;
1216 struct kvm_memory_slot *slot;
1218 if (unlikely(*force_pt_level))
1219 return PT_PAGE_TABLE_LEVEL;
1221 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1222 *force_pt_level = !memslot_valid_for_gpte(slot, true);
1223 if (unlikely(*force_pt_level))
1224 return PT_PAGE_TABLE_LEVEL;
1226 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1228 if (host_level == PT_PAGE_TABLE_LEVEL)
1231 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1233 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1234 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1241 * About rmap_head encoding:
1243 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1244 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1245 * pte_list_desc containing more mappings.
1249 * Returns the number of pointers in the rmap chain, not counting the new one.
1251 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1252 struct kvm_rmap_head *rmap_head)
1254 struct pte_list_desc *desc;
1257 if (!rmap_head->val) {
1258 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1259 rmap_head->val = (unsigned long)spte;
1260 } else if (!(rmap_head->val & 1)) {
1261 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1262 desc = mmu_alloc_pte_list_desc(vcpu);
1263 desc->sptes[0] = (u64 *)rmap_head->val;
1264 desc->sptes[1] = spte;
1265 rmap_head->val = (unsigned long)desc | 1;
1268 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1269 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1270 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1272 count += PTE_LIST_EXT;
1274 if (desc->sptes[PTE_LIST_EXT-1]) {
1275 desc->more = mmu_alloc_pte_list_desc(vcpu);
1278 for (i = 0; desc->sptes[i]; ++i)
1280 desc->sptes[i] = spte;
1286 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1287 struct pte_list_desc *desc, int i,
1288 struct pte_list_desc *prev_desc)
1292 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1294 desc->sptes[i] = desc->sptes[j];
1295 desc->sptes[j] = NULL;
1298 if (!prev_desc && !desc->more)
1299 rmap_head->val = (unsigned long)desc->sptes[0];
1302 prev_desc->more = desc->more;
1304 rmap_head->val = (unsigned long)desc->more | 1;
1305 mmu_free_pte_list_desc(desc);
1308 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1310 struct pte_list_desc *desc;
1311 struct pte_list_desc *prev_desc;
1314 if (!rmap_head->val) {
1315 pr_err("%s: %p 0->BUG\n", __func__, spte);
1317 } else if (!(rmap_head->val & 1)) {
1318 rmap_printk("%s: %p 1->0\n", __func__, spte);
1319 if ((u64 *)rmap_head->val != spte) {
1320 pr_err("%s: %p 1->BUG\n", __func__, spte);
1325 rmap_printk("%s: %p many->many\n", __func__, spte);
1326 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1329 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1330 if (desc->sptes[i] == spte) {
1331 pte_list_desc_remove_entry(rmap_head,
1332 desc, i, prev_desc);
1339 pr_err("%s: %p many->many\n", __func__, spte);
1344 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
1346 mmu_spte_clear_track_bits(sptep);
1347 __pte_list_remove(sptep, rmap_head);
1350 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1351 struct kvm_memory_slot *slot)
1355 idx = gfn_to_index(gfn, slot->base_gfn, level);
1356 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1359 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1360 struct kvm_mmu_page *sp)
1362 struct kvm_memslots *slots;
1363 struct kvm_memory_slot *slot;
1365 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1366 slot = __gfn_to_memslot(slots, gfn);
1367 return __gfn_to_rmap(gfn, sp->role.level, slot);
1370 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1372 struct kvm_mmu_memory_cache *cache;
1374 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1375 return mmu_memory_cache_free_objects(cache);
1378 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1380 struct kvm_mmu_page *sp;
1381 struct kvm_rmap_head *rmap_head;
1383 sp = page_header(__pa(spte));
1384 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1385 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1386 return pte_list_add(vcpu, spte, rmap_head);
1389 static void rmap_remove(struct kvm *kvm, u64 *spte)
1391 struct kvm_mmu_page *sp;
1393 struct kvm_rmap_head *rmap_head;
1395 sp = page_header(__pa(spte));
1396 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1397 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1398 __pte_list_remove(spte, rmap_head);
1402 * Used by the following functions to iterate through the sptes linked by a
1403 * rmap. All fields are private and not assumed to be used outside.
1405 struct rmap_iterator {
1406 /* private fields */
1407 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1408 int pos; /* index of the sptep */
1412 * Iteration must be started by this function. This should also be used after
1413 * removing/dropping sptes from the rmap link because in such cases the
1414 * information in the itererator may not be valid.
1416 * Returns sptep if found, NULL otherwise.
1418 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1419 struct rmap_iterator *iter)
1423 if (!rmap_head->val)
1426 if (!(rmap_head->val & 1)) {
1428 sptep = (u64 *)rmap_head->val;
1432 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1434 sptep = iter->desc->sptes[iter->pos];
1436 BUG_ON(!is_shadow_present_pte(*sptep));
1441 * Must be used with a valid iterator: e.g. after rmap_get_first().
1443 * Returns sptep if found, NULL otherwise.
1445 static u64 *rmap_get_next(struct rmap_iterator *iter)
1450 if (iter->pos < PTE_LIST_EXT - 1) {
1452 sptep = iter->desc->sptes[iter->pos];
1457 iter->desc = iter->desc->more;
1461 /* desc->sptes[0] cannot be NULL */
1462 sptep = iter->desc->sptes[iter->pos];
1469 BUG_ON(!is_shadow_present_pte(*sptep));
1473 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1474 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1475 _spte_; _spte_ = rmap_get_next(_iter_))
1477 static void drop_spte(struct kvm *kvm, u64 *sptep)
1479 if (mmu_spte_clear_track_bits(sptep))
1480 rmap_remove(kvm, sptep);
1484 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1486 if (is_large_pte(*sptep)) {
1487 WARN_ON(page_header(__pa(sptep))->role.level ==
1488 PT_PAGE_TABLE_LEVEL);
1489 drop_spte(kvm, sptep);
1497 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1499 if (__drop_large_spte(vcpu->kvm, sptep)) {
1500 struct kvm_mmu_page *sp = page_header(__pa(sptep));
1502 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1503 KVM_PAGES_PER_HPAGE(sp->role.level));
1508 * Write-protect on the specified @sptep, @pt_protect indicates whether
1509 * spte write-protection is caused by protecting shadow page table.
1511 * Note: write protection is difference between dirty logging and spte
1513 * - for dirty logging, the spte can be set to writable at anytime if
1514 * its dirty bitmap is properly set.
1515 * - for spte protection, the spte can be writable only after unsync-ing
1518 * Return true if tlb need be flushed.
1520 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1524 if (!is_writable_pte(spte) &&
1525 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1528 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1531 spte &= ~SPTE_MMU_WRITEABLE;
1532 spte = spte & ~PT_WRITABLE_MASK;
1534 return mmu_spte_update(sptep, spte);
1537 static bool __rmap_write_protect(struct kvm *kvm,
1538 struct kvm_rmap_head *rmap_head,
1542 struct rmap_iterator iter;
1545 for_each_rmap_spte(rmap_head, &iter, sptep)
1546 flush |= spte_write_protect(sptep, pt_protect);
1551 static bool spte_clear_dirty(u64 *sptep)
1555 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1557 spte &= ~shadow_dirty_mask;
1559 return mmu_spte_update(sptep, spte);
1562 static bool wrprot_ad_disabled_spte(u64 *sptep)
1564 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1565 (unsigned long *)sptep);
1567 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1569 return was_writable;
1573 * Gets the GFN ready for another round of dirty logging by clearing the
1574 * - D bit on ad-enabled SPTEs, and
1575 * - W bit on ad-disabled SPTEs.
1576 * Returns true iff any D or W bits were cleared.
1578 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1581 struct rmap_iterator iter;
1584 for_each_rmap_spte(rmap_head, &iter, sptep)
1585 if (spte_ad_enabled(*sptep))
1586 flush |= spte_clear_dirty(sptep);
1588 flush |= wrprot_ad_disabled_spte(sptep);
1593 static bool spte_set_dirty(u64 *sptep)
1597 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1599 spte |= shadow_dirty_mask;
1601 return mmu_spte_update(sptep, spte);
1604 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1607 struct rmap_iterator iter;
1610 for_each_rmap_spte(rmap_head, &iter, sptep)
1611 if (spte_ad_enabled(*sptep))
1612 flush |= spte_set_dirty(sptep);
1618 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1619 * @kvm: kvm instance
1620 * @slot: slot to protect
1621 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1622 * @mask: indicates which pages we should protect
1624 * Used when we do not need to care about huge page mappings: e.g. during dirty
1625 * logging we do not have any such mappings.
1627 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1628 struct kvm_memory_slot *slot,
1629 gfn_t gfn_offset, unsigned long mask)
1631 struct kvm_rmap_head *rmap_head;
1634 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1635 PT_PAGE_TABLE_LEVEL, slot);
1636 __rmap_write_protect(kvm, rmap_head, false);
1638 /* clear the first set bit */
1644 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1645 * protect the page if the D-bit isn't supported.
1646 * @kvm: kvm instance
1647 * @slot: slot to clear D-bit
1648 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1649 * @mask: indicates which pages we should clear D-bit
1651 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1653 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1654 struct kvm_memory_slot *slot,
1655 gfn_t gfn_offset, unsigned long mask)
1657 struct kvm_rmap_head *rmap_head;
1660 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1661 PT_PAGE_TABLE_LEVEL, slot);
1662 __rmap_clear_dirty(kvm, rmap_head);
1664 /* clear the first set bit */
1668 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1671 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1674 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1675 * enable dirty logging for them.
1677 * Used when we do not need to care about huge page mappings: e.g. during dirty
1678 * logging we do not have any such mappings.
1680 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1681 struct kvm_memory_slot *slot,
1682 gfn_t gfn_offset, unsigned long mask)
1684 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1685 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1688 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1692 * kvm_arch_write_log_dirty - emulate dirty page logging
1693 * @vcpu: Guest mode vcpu
1695 * Emulate arch specific page modification logging for the
1698 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1700 if (kvm_x86_ops->write_log_dirty)
1701 return kvm_x86_ops->write_log_dirty(vcpu);
1706 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1707 struct kvm_memory_slot *slot, u64 gfn)
1709 struct kvm_rmap_head *rmap_head;
1711 bool write_protected = false;
1713 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1714 rmap_head = __gfn_to_rmap(gfn, i, slot);
1715 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1718 return write_protected;
1721 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1723 struct kvm_memory_slot *slot;
1725 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1726 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1729 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1732 struct rmap_iterator iter;
1735 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1736 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1738 pte_list_remove(rmap_head, sptep);
1745 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1746 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1749 return kvm_zap_rmapp(kvm, rmap_head);
1752 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1753 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1757 struct rmap_iterator iter;
1760 pte_t *ptep = (pte_t *)data;
1763 WARN_ON(pte_huge(*ptep));
1764 new_pfn = pte_pfn(*ptep);
1767 for_each_rmap_spte(rmap_head, &iter, sptep) {
1768 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1769 sptep, *sptep, gfn, level);
1773 if (pte_write(*ptep)) {
1774 pte_list_remove(rmap_head, sptep);
1777 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1778 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1780 new_spte &= ~PT_WRITABLE_MASK;
1781 new_spte &= ~SPTE_HOST_WRITEABLE;
1783 new_spte = mark_spte_for_access_track(new_spte);
1785 mmu_spte_clear_track_bits(sptep);
1786 mmu_spte_set(sptep, new_spte);
1790 if (need_flush && kvm_available_flush_tlb_with_range()) {
1791 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1798 struct slot_rmap_walk_iterator {
1800 struct kvm_memory_slot *slot;
1806 /* output fields. */
1808 struct kvm_rmap_head *rmap;
1811 /* private field. */
1812 struct kvm_rmap_head *end_rmap;
1816 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1818 iterator->level = level;
1819 iterator->gfn = iterator->start_gfn;
1820 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1821 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1826 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1827 struct kvm_memory_slot *slot, int start_level,
1828 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1830 iterator->slot = slot;
1831 iterator->start_level = start_level;
1832 iterator->end_level = end_level;
1833 iterator->start_gfn = start_gfn;
1834 iterator->end_gfn = end_gfn;
1836 rmap_walk_init_level(iterator, iterator->start_level);
1839 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1841 return !!iterator->rmap;
1844 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1846 if (++iterator->rmap <= iterator->end_rmap) {
1847 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1851 if (++iterator->level > iterator->end_level) {
1852 iterator->rmap = NULL;
1856 rmap_walk_init_level(iterator, iterator->level);
1859 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1860 _start_gfn, _end_gfn, _iter_) \
1861 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1862 _end_level_, _start_gfn, _end_gfn); \
1863 slot_rmap_walk_okay(_iter_); \
1864 slot_rmap_walk_next(_iter_))
1866 static int kvm_handle_hva_range(struct kvm *kvm,
1867 unsigned long start,
1870 int (*handler)(struct kvm *kvm,
1871 struct kvm_rmap_head *rmap_head,
1872 struct kvm_memory_slot *slot,
1875 unsigned long data))
1877 struct kvm_memslots *slots;
1878 struct kvm_memory_slot *memslot;
1879 struct slot_rmap_walk_iterator iterator;
1883 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1884 slots = __kvm_memslots(kvm, i);
1885 kvm_for_each_memslot(memslot, slots) {
1886 unsigned long hva_start, hva_end;
1887 gfn_t gfn_start, gfn_end;
1889 hva_start = max(start, memslot->userspace_addr);
1890 hva_end = min(end, memslot->userspace_addr +
1891 (memslot->npages << PAGE_SHIFT));
1892 if (hva_start >= hva_end)
1895 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1896 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1898 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1899 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1901 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1902 PT_MAX_HUGEPAGE_LEVEL,
1903 gfn_start, gfn_end - 1,
1905 ret |= handler(kvm, iterator.rmap, memslot,
1906 iterator.gfn, iterator.level, data);
1913 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1915 int (*handler)(struct kvm *kvm,
1916 struct kvm_rmap_head *rmap_head,
1917 struct kvm_memory_slot *slot,
1918 gfn_t gfn, int level,
1919 unsigned long data))
1921 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1924 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1926 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1929 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1931 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1934 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1935 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1939 struct rmap_iterator uninitialized_var(iter);
1942 for_each_rmap_spte(rmap_head, &iter, sptep)
1943 young |= mmu_spte_age(sptep);
1945 trace_kvm_age_page(gfn, level, slot, young);
1949 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1950 struct kvm_memory_slot *slot, gfn_t gfn,
1951 int level, unsigned long data)
1954 struct rmap_iterator iter;
1956 for_each_rmap_spte(rmap_head, &iter, sptep)
1957 if (is_accessed_spte(*sptep))
1962 #define RMAP_RECYCLE_THRESHOLD 1000
1964 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1966 struct kvm_rmap_head *rmap_head;
1967 struct kvm_mmu_page *sp;
1969 sp = page_header(__pa(spte));
1971 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1973 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1974 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1975 KVM_PAGES_PER_HPAGE(sp->role.level));
1978 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1980 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1983 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1985 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1989 static int is_empty_shadow_page(u64 *spt)
1994 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1995 if (is_shadow_present_pte(*pos)) {
1996 printk(KERN_ERR "%s: %p %llx\n", __func__,
2005 * This value is the sum of all of the kvm instances's
2006 * kvm->arch.n_used_mmu_pages values. We need a global,
2007 * aggregate version in order to make the slab shrinker
2010 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
2012 kvm->arch.n_used_mmu_pages += nr;
2013 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
2016 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
2018 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
2019 hlist_del(&sp->hash_link);
2020 list_del(&sp->link);
2021 free_page((unsigned long)sp->spt);
2022 if (!sp->role.direct)
2023 free_page((unsigned long)sp->gfns);
2024 kmem_cache_free(mmu_page_header_cache, sp);
2027 static unsigned kvm_page_table_hashfn(gfn_t gfn)
2029 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
2032 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
2033 struct kvm_mmu_page *sp, u64 *parent_pte)
2038 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
2041 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
2044 __pte_list_remove(parent_pte, &sp->parent_ptes);
2047 static void drop_parent_pte(struct kvm_mmu_page *sp,
2050 mmu_page_remove_parent_pte(sp, parent_pte);
2051 mmu_spte_clear_no_track(parent_pte);
2054 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
2056 struct kvm_mmu_page *sp;
2058 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2059 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2061 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2062 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
2063 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2064 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2068 static void mark_unsync(u64 *spte);
2069 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2072 struct rmap_iterator iter;
2074 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2079 static void mark_unsync(u64 *spte)
2081 struct kvm_mmu_page *sp;
2084 sp = page_header(__pa(spte));
2085 index = spte - sp->spt;
2086 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2088 if (sp->unsync_children++)
2090 kvm_mmu_mark_parents_unsync(sp);
2093 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2094 struct kvm_mmu_page *sp)
2099 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root)
2103 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2104 struct kvm_mmu_page *sp, u64 *spte,
2110 #define KVM_PAGE_ARRAY_NR 16
2112 struct kvm_mmu_pages {
2113 struct mmu_page_and_offset {
2114 struct kvm_mmu_page *sp;
2116 } page[KVM_PAGE_ARRAY_NR];
2120 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2126 for (i=0; i < pvec->nr; i++)
2127 if (pvec->page[i].sp == sp)
2130 pvec->page[pvec->nr].sp = sp;
2131 pvec->page[pvec->nr].idx = idx;
2133 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2136 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2138 --sp->unsync_children;
2139 WARN_ON((int)sp->unsync_children < 0);
2140 __clear_bit(idx, sp->unsync_child_bitmap);
2143 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2144 struct kvm_mmu_pages *pvec)
2146 int i, ret, nr_unsync_leaf = 0;
2148 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2149 struct kvm_mmu_page *child;
2150 u64 ent = sp->spt[i];
2152 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2153 clear_unsync_child_bit(sp, i);
2157 child = page_header(ent & PT64_BASE_ADDR_MASK);
2159 if (child->unsync_children) {
2160 if (mmu_pages_add(pvec, child, i))
2163 ret = __mmu_unsync_walk(child, pvec);
2165 clear_unsync_child_bit(sp, i);
2167 } else if (ret > 0) {
2168 nr_unsync_leaf += ret;
2171 } else if (child->unsync) {
2173 if (mmu_pages_add(pvec, child, i))
2176 clear_unsync_child_bit(sp, i);
2179 return nr_unsync_leaf;
2182 #define INVALID_INDEX (-1)
2184 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2185 struct kvm_mmu_pages *pvec)
2188 if (!sp->unsync_children)
2191 mmu_pages_add(pvec, sp, INVALID_INDEX);
2192 return __mmu_unsync_walk(sp, pvec);
2195 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2197 WARN_ON(!sp->unsync);
2198 trace_kvm_mmu_sync_page(sp);
2200 --kvm->stat.mmu_unsync;
2203 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2204 struct list_head *invalid_list);
2205 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2206 struct list_head *invalid_list);
2208 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2209 hlist_for_each_entry(_sp, \
2210 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2211 if ((_sp)->role.invalid) { \
2214 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2215 for_each_valid_sp(_kvm, _sp, _gfn) \
2216 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2218 /* @sp->gfn should be write-protected at the call site */
2219 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2220 struct list_head *invalid_list)
2222 if (sp->role.cr4_pae != !!is_pae(vcpu)
2223 || vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
2224 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2231 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
2232 struct list_head *invalid_list,
2235 if (!remote_flush && !list_empty(invalid_list))
2238 if (!list_empty(invalid_list))
2239 kvm_mmu_commit_zap_page(kvm, invalid_list);
2241 kvm_flush_remote_tlbs(kvm);
2245 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2246 struct list_head *invalid_list,
2247 bool remote_flush, bool local_flush)
2249 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
2253 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2256 #ifdef CONFIG_KVM_MMU_AUDIT
2257 #include "mmu_audit.c"
2259 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2260 static void mmu_audit_disable(void) { }
2263 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2264 struct list_head *invalid_list)
2266 kvm_unlink_unsync_page(vcpu->kvm, sp);
2267 return __kvm_sync_page(vcpu, sp, invalid_list);
2270 /* @gfn should be write-protected at the call site */
2271 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2272 struct list_head *invalid_list)
2274 struct kvm_mmu_page *s;
2277 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2281 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2282 ret |= kvm_sync_page(vcpu, s, invalid_list);
2288 struct mmu_page_path {
2289 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2290 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2293 #define for_each_sp(pvec, sp, parents, i) \
2294 for (i = mmu_pages_first(&pvec, &parents); \
2295 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2296 i = mmu_pages_next(&pvec, &parents, i))
2298 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2299 struct mmu_page_path *parents,
2304 for (n = i+1; n < pvec->nr; n++) {
2305 struct kvm_mmu_page *sp = pvec->page[n].sp;
2306 unsigned idx = pvec->page[n].idx;
2307 int level = sp->role.level;
2309 parents->idx[level-1] = idx;
2310 if (level == PT_PAGE_TABLE_LEVEL)
2313 parents->parent[level-2] = sp;
2319 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2320 struct mmu_page_path *parents)
2322 struct kvm_mmu_page *sp;
2328 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2330 sp = pvec->page[0].sp;
2331 level = sp->role.level;
2332 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2334 parents->parent[level-2] = sp;
2336 /* Also set up a sentinel. Further entries in pvec are all
2337 * children of sp, so this element is never overwritten.
2339 parents->parent[level-1] = NULL;
2340 return mmu_pages_next(pvec, parents, 0);
2343 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2345 struct kvm_mmu_page *sp;
2346 unsigned int level = 0;
2349 unsigned int idx = parents->idx[level];
2350 sp = parents->parent[level];
2354 WARN_ON(idx == INVALID_INDEX);
2355 clear_unsync_child_bit(sp, idx);
2357 } while (!sp->unsync_children);
2360 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2361 struct kvm_mmu_page *parent)
2364 struct kvm_mmu_page *sp;
2365 struct mmu_page_path parents;
2366 struct kvm_mmu_pages pages;
2367 LIST_HEAD(invalid_list);
2370 while (mmu_unsync_walk(parent, &pages)) {
2371 bool protected = false;
2373 for_each_sp(pages, sp, parents, i)
2374 protected |= rmap_write_protect(vcpu, sp->gfn);
2377 kvm_flush_remote_tlbs(vcpu->kvm);
2381 for_each_sp(pages, sp, parents, i) {
2382 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2383 mmu_pages_clear_parents(&parents);
2385 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2386 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2387 cond_resched_lock(&vcpu->kvm->mmu_lock);
2392 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2395 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2397 atomic_set(&sp->write_flooding_count, 0);
2400 static void clear_sp_write_flooding_count(u64 *spte)
2402 struct kvm_mmu_page *sp = page_header(__pa(spte));
2404 __clear_sp_write_flooding_count(sp);
2407 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2414 union kvm_mmu_page_role role;
2416 struct kvm_mmu_page *sp;
2417 bool need_sync = false;
2420 LIST_HEAD(invalid_list);
2422 role = vcpu->arch.mmu->mmu_role.base;
2424 role.direct = direct;
2427 role.access = access;
2428 if (!vcpu->arch.mmu->direct_map
2429 && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2430 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2431 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2432 role.quadrant = quadrant;
2434 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2435 if (sp->gfn != gfn) {
2440 if (!need_sync && sp->unsync)
2443 if (sp->role.word != role.word)
2447 /* The page is good, but __kvm_sync_page might still end
2448 * up zapping it. If so, break in order to rebuild it.
2450 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2453 WARN_ON(!list_empty(&invalid_list));
2454 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2457 if (sp->unsync_children)
2458 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2460 __clear_sp_write_flooding_count(sp);
2461 trace_kvm_mmu_get_page(sp, false);
2465 ++vcpu->kvm->stat.mmu_cache_miss;
2467 sp = kvm_mmu_alloc_page(vcpu, direct);
2471 hlist_add_head(&sp->hash_link,
2472 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2475 * we should do write protection before syncing pages
2476 * otherwise the content of the synced shadow page may
2477 * be inconsistent with guest page table.
2479 account_shadowed(vcpu->kvm, sp);
2480 if (level == PT_PAGE_TABLE_LEVEL &&
2481 rmap_write_protect(vcpu, gfn))
2482 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2484 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2485 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2487 clear_page(sp->spt);
2488 trace_kvm_mmu_get_page(sp, true);
2490 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2492 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2493 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2497 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2498 struct kvm_vcpu *vcpu, hpa_t root,
2501 iterator->addr = addr;
2502 iterator->shadow_addr = root;
2503 iterator->level = vcpu->arch.mmu->shadow_root_level;
2505 if (iterator->level == PT64_ROOT_4LEVEL &&
2506 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2507 !vcpu->arch.mmu->direct_map)
2510 if (iterator->level == PT32E_ROOT_LEVEL) {
2512 * prev_root is currently only used for 64-bit hosts. So only
2513 * the active root_hpa is valid here.
2515 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2517 iterator->shadow_addr
2518 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2519 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2521 if (!iterator->shadow_addr)
2522 iterator->level = 0;
2526 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2527 struct kvm_vcpu *vcpu, u64 addr)
2529 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2533 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2535 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2538 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2539 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2543 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2546 if (is_last_spte(spte, iterator->level)) {
2547 iterator->level = 0;
2551 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2555 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2557 __shadow_walk_next(iterator, *iterator->sptep);
2560 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2561 struct kvm_mmu_page *sp)
2565 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2567 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2568 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2570 if (sp_ad_disabled(sp))
2571 spte |= shadow_acc_track_value;
2573 spte |= shadow_accessed_mask;
2575 mmu_spte_set(sptep, spte);
2577 mmu_page_add_parent_pte(vcpu, sp, sptep);
2579 if (sp->unsync_children || sp->unsync)
2583 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2584 unsigned direct_access)
2586 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2587 struct kvm_mmu_page *child;
2590 * For the direct sp, if the guest pte's dirty bit
2591 * changed form clean to dirty, it will corrupt the
2592 * sp's access: allow writable in the read-only sp,
2593 * so we should update the spte at this point to get
2594 * a new sp with the correct access.
2596 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2597 if (child->role.access == direct_access)
2600 drop_parent_pte(child, sptep);
2601 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2605 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2609 struct kvm_mmu_page *child;
2612 if (is_shadow_present_pte(pte)) {
2613 if (is_last_spte(pte, sp->role.level)) {
2614 drop_spte(kvm, spte);
2615 if (is_large_pte(pte))
2618 child = page_header(pte & PT64_BASE_ADDR_MASK);
2619 drop_parent_pte(child, spte);
2624 if (is_mmio_spte(pte))
2625 mmu_spte_clear_no_track(spte);
2630 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2631 struct kvm_mmu_page *sp)
2635 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2636 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2639 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2642 struct rmap_iterator iter;
2644 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2645 drop_parent_pte(sp, sptep);
2648 static int mmu_zap_unsync_children(struct kvm *kvm,
2649 struct kvm_mmu_page *parent,
2650 struct list_head *invalid_list)
2653 struct mmu_page_path parents;
2654 struct kvm_mmu_pages pages;
2656 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2659 while (mmu_unsync_walk(parent, &pages)) {
2660 struct kvm_mmu_page *sp;
2662 for_each_sp(pages, sp, parents, i) {
2663 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2664 mmu_pages_clear_parents(&parents);
2672 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2673 struct kvm_mmu_page *sp,
2674 struct list_head *invalid_list,
2679 trace_kvm_mmu_prepare_zap_page(sp);
2680 ++kvm->stat.mmu_shadow_zapped;
2681 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2682 kvm_mmu_page_unlink_children(kvm, sp);
2683 kvm_mmu_unlink_parents(kvm, sp);
2685 /* Zapping children means active_mmu_pages has become unstable. */
2686 list_unstable = *nr_zapped;
2688 if (!sp->role.invalid && !sp->role.direct)
2689 unaccount_shadowed(kvm, sp);
2692 kvm_unlink_unsync_page(kvm, sp);
2693 if (!sp->root_count) {
2696 list_move(&sp->link, invalid_list);
2697 kvm_mod_used_mmu_pages(kvm, -1);
2699 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2701 if (!sp->role.invalid)
2702 kvm_reload_remote_mmus(kvm);
2705 sp->role.invalid = 1;
2706 return list_unstable;
2709 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2710 struct list_head *invalid_list)
2714 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2718 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2719 struct list_head *invalid_list)
2721 struct kvm_mmu_page *sp, *nsp;
2723 if (list_empty(invalid_list))
2727 * We need to make sure everyone sees our modifications to
2728 * the page tables and see changes to vcpu->mode here. The barrier
2729 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2730 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2732 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2733 * guest mode and/or lockless shadow page table walks.
2735 kvm_flush_remote_tlbs(kvm);
2737 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2738 WARN_ON(!sp->role.invalid || sp->root_count);
2739 kvm_mmu_free_page(sp);
2743 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2744 struct list_head *invalid_list)
2746 struct kvm_mmu_page *sp;
2748 if (list_empty(&kvm->arch.active_mmu_pages))
2751 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2752 struct kvm_mmu_page, link);
2753 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2757 * Changing the number of mmu pages allocated to the vm
2758 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2760 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2762 LIST_HEAD(invalid_list);
2764 spin_lock(&kvm->mmu_lock);
2766 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2767 /* Need to free some mmu pages to achieve the goal. */
2768 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2769 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2772 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2773 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2776 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2778 spin_unlock(&kvm->mmu_lock);
2781 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2783 struct kvm_mmu_page *sp;
2784 LIST_HEAD(invalid_list);
2787 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2789 spin_lock(&kvm->mmu_lock);
2790 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2791 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2794 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2796 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2797 spin_unlock(&kvm->mmu_lock);
2801 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2803 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2805 trace_kvm_mmu_unsync_page(sp);
2806 ++vcpu->kvm->stat.mmu_unsync;
2809 kvm_mmu_mark_parents_unsync(sp);
2812 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2815 struct kvm_mmu_page *sp;
2817 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2820 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2827 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2828 kvm_unsync_page(vcpu, sp);
2832 * We need to ensure that the marking of unsync pages is visible
2833 * before the SPTE is updated to allow writes because
2834 * kvm_mmu_sync_roots() checks the unsync flags without holding
2835 * the MMU lock and so can race with this. If the SPTE was updated
2836 * before the page had been marked as unsync-ed, something like the
2837 * following could happen:
2840 * ---------------------------------------------------------------------
2841 * 1.2 Host updates SPTE
2843 * 2.1 Guest writes a GPTE for GVA X.
2844 * (GPTE being in the guest page table shadowed
2845 * by the SP from CPU 1.)
2846 * This reads SPTE during the page table walk.
2847 * Since SPTE.W is read as 1, there is no
2850 * 2.2 Guest issues TLB flush.
2851 * That causes a VM Exit.
2853 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2854 * Since it is false, so it just returns.
2856 * 2.4 Guest accesses GVA X.
2857 * Since the mapping in the SP was not updated,
2858 * so the old mapping for GVA X incorrectly
2862 * (sp->unsync = true)
2864 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2865 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2866 * pairs with this write barrier.
2873 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2876 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2878 * Some reserved pages, such as those from NVDIMM
2879 * DAX devices, are not for MMIO, and can be mapped
2880 * with cached memory type for better performance.
2881 * However, the above check misconceives those pages
2882 * as MMIO, and results in KVM mapping them with UC
2883 * memory type, which would hurt the performance.
2884 * Therefore, we check the host memory type in addition
2885 * and only treat UC/UC-/WC pages as MMIO.
2887 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
2892 /* Bits which may be returned by set_spte() */
2893 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
2894 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
2896 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2897 unsigned pte_access, int level,
2898 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2899 bool can_unsync, bool host_writable)
2903 struct kvm_mmu_page *sp;
2905 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2908 sp = page_header(__pa(sptep));
2909 if (sp_ad_disabled(sp))
2910 spte |= shadow_acc_track_value;
2913 * For the EPT case, shadow_present_mask is 0 if hardware
2914 * supports exec-only page table entries. In that case,
2915 * ACC_USER_MASK and shadow_user_mask are used to represent
2916 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2918 spte |= shadow_present_mask;
2920 spte |= spte_shadow_accessed_mask(spte);
2922 if (pte_access & ACC_EXEC_MASK)
2923 spte |= shadow_x_mask;
2925 spte |= shadow_nx_mask;
2927 if (pte_access & ACC_USER_MASK)
2928 spte |= shadow_user_mask;
2930 if (level > PT_PAGE_TABLE_LEVEL)
2931 spte |= PT_PAGE_SIZE_MASK;
2933 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2934 kvm_is_mmio_pfn(pfn));
2937 spte |= SPTE_HOST_WRITEABLE;
2939 pte_access &= ~ACC_WRITE_MASK;
2941 if (!kvm_is_mmio_pfn(pfn))
2942 spte |= shadow_me_mask;
2944 spte |= (u64)pfn << PAGE_SHIFT;
2946 if (pte_access & ACC_WRITE_MASK) {
2949 * Other vcpu creates new sp in the window between
2950 * mapping_level() and acquiring mmu-lock. We can
2951 * allow guest to retry the access, the mapping can
2952 * be fixed if guest refault.
2954 if (level > PT_PAGE_TABLE_LEVEL &&
2955 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2958 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2961 * Optimization: for pte sync, if spte was writable the hash
2962 * lookup is unnecessary (and expensive). Write protection
2963 * is responsibility of mmu_get_page / kvm_sync_page.
2964 * Same reasoning can be applied to dirty page accounting.
2966 if (!can_unsync && is_writable_pte(*sptep))
2969 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2970 pgprintk("%s: found shadow page for %llx, marking ro\n",
2972 ret |= SET_SPTE_WRITE_PROTECTED_PT;
2973 pte_access &= ~ACC_WRITE_MASK;
2974 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2978 if (pte_access & ACC_WRITE_MASK) {
2979 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2980 spte |= spte_shadow_dirty_mask(spte);
2984 spte = mark_spte_for_access_track(spte);
2987 if (mmu_spte_update(sptep, spte))
2988 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2993 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2994 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2995 bool speculative, bool host_writable)
2997 int was_rmapped = 0;
3000 int ret = RET_PF_RETRY;
3003 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
3004 *sptep, write_fault, gfn);
3006 if (is_shadow_present_pte(*sptep)) {
3008 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
3009 * the parent of the now unreachable PTE.
3011 if (level > PT_PAGE_TABLE_LEVEL &&
3012 !is_large_pte(*sptep)) {
3013 struct kvm_mmu_page *child;
3016 child = page_header(pte & PT64_BASE_ADDR_MASK);
3017 drop_parent_pte(child, sptep);
3019 } else if (pfn != spte_to_pfn(*sptep)) {
3020 pgprintk("hfn old %llx new %llx\n",
3021 spte_to_pfn(*sptep), pfn);
3022 drop_spte(vcpu->kvm, sptep);
3028 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
3029 speculative, true, host_writable);
3030 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
3032 ret = RET_PF_EMULATE;
3033 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3036 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
3037 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
3038 KVM_PAGES_PER_HPAGE(level));
3040 if (unlikely(is_mmio_spte(*sptep)))
3041 ret = RET_PF_EMULATE;
3043 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
3044 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
3045 is_large_pte(*sptep)? "2MB" : "4kB",
3046 *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
3048 if (!was_rmapped && is_large_pte(*sptep))
3049 ++vcpu->kvm->stat.lpages;
3051 if (is_shadow_present_pte(*sptep)) {
3053 rmap_count = rmap_add(vcpu, sptep, gfn);
3054 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3055 rmap_recycle(vcpu, sptep, gfn);
3059 kvm_release_pfn_clean(pfn);
3064 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
3067 struct kvm_memory_slot *slot;
3069 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3071 return KVM_PFN_ERR_FAULT;
3073 return gfn_to_pfn_memslot_atomic(slot, gfn);
3076 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3077 struct kvm_mmu_page *sp,
3078 u64 *start, u64 *end)
3080 struct page *pages[PTE_PREFETCH_NUM];
3081 struct kvm_memory_slot *slot;
3082 unsigned access = sp->role.access;
3086 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3087 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3091 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3095 for (i = 0; i < ret; i++, gfn++, start++)
3096 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3097 page_to_pfn(pages[i]), true, true);
3102 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3103 struct kvm_mmu_page *sp, u64 *sptep)
3105 u64 *spte, *start = NULL;
3108 WARN_ON(!sp->role.direct);
3110 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3113 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3114 if (is_shadow_present_pte(*spte) || spte == sptep) {
3117 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3125 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3127 struct kvm_mmu_page *sp;
3129 sp = page_header(__pa(sptep));
3132 * Without accessed bits, there's no way to distinguish between
3133 * actually accessed translations and prefetched, so disable pte
3134 * prefetch if accessed bits aren't available.
3136 if (sp_ad_disabled(sp))
3139 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3142 __direct_pte_prefetch(vcpu, sp, sptep);
3145 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
3146 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
3148 struct kvm_shadow_walk_iterator iterator;
3149 struct kvm_mmu_page *sp;
3153 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3156 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
3157 if (iterator.level == level) {
3158 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
3159 write, level, gfn, pfn, prefault,
3161 direct_pte_prefetch(vcpu, iterator.sptep);
3162 ++vcpu->stat.pf_fixed;
3166 drop_large_spte(vcpu, iterator.sptep);
3167 if (!is_shadow_present_pte(*iterator.sptep)) {
3168 u64 base_addr = iterator.addr;
3170 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
3171 pseudo_gfn = base_addr >> PAGE_SHIFT;
3172 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
3173 iterator.level - 1, 1, ACC_ALL);
3175 link_shadow_page(vcpu, iterator.sptep, sp);
3181 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3183 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3186 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3189 * Do not cache the mmio info caused by writing the readonly gfn
3190 * into the spte otherwise read access on readonly gfn also can
3191 * caused mmio page fault and treat it as mmio access.
3193 if (pfn == KVM_PFN_ERR_RO_FAULT)
3194 return RET_PF_EMULATE;
3196 if (pfn == KVM_PFN_ERR_HWPOISON) {
3197 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3198 return RET_PF_RETRY;
3204 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3205 gfn_t *gfnp, kvm_pfn_t *pfnp,
3208 kvm_pfn_t pfn = *pfnp;
3210 int level = *levelp;
3213 * Check if it's a transparent hugepage. If this would be an
3214 * hugetlbfs page, level wouldn't be set to
3215 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3218 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3219 level == PT_PAGE_TABLE_LEVEL &&
3220 PageTransCompoundMap(pfn_to_page(pfn)) &&
3221 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3224 * mmu_notifier_retry was successful and we hold the
3225 * mmu_lock here, so the pmd can't become splitting
3226 * from under us, and in turn
3227 * __split_huge_page_refcount() can't run from under
3228 * us and we can safely transfer the refcount from
3229 * PG_tail to PG_head as we switch the pfn to tail to
3232 *levelp = level = PT_DIRECTORY_LEVEL;
3233 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3234 VM_BUG_ON((gfn & mask) != (pfn & mask));
3238 kvm_release_pfn_clean(pfn);
3246 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3247 kvm_pfn_t pfn, unsigned access, int *ret_val)
3249 /* The pfn is invalid, report the error! */
3250 if (unlikely(is_error_pfn(pfn))) {
3251 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3255 if (unlikely(is_noslot_pfn(pfn)))
3256 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3261 static bool page_fault_can_be_fast(u32 error_code)
3264 * Do not fix the mmio spte with invalid generation number which
3265 * need to be updated by slow page fault path.
3267 if (unlikely(error_code & PFERR_RSVD_MASK))
3270 /* See if the page fault is due to an NX violation */
3271 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3272 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3276 * #PF can be fast if:
3277 * 1. The shadow page table entry is not present, which could mean that
3278 * the fault is potentially caused by access tracking (if enabled).
3279 * 2. The shadow page table entry is present and the fault
3280 * is caused by write-protect, that means we just need change the W
3281 * bit of the spte which can be done out of mmu-lock.
3283 * However, if access tracking is disabled we know that a non-present
3284 * page must be a genuine page fault where we have to create a new SPTE.
3285 * So, if access tracking is disabled, we return true only for write
3286 * accesses to a present page.
3289 return shadow_acc_track_mask != 0 ||
3290 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3291 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3295 * Returns true if the SPTE was fixed successfully. Otherwise,
3296 * someone else modified the SPTE from its original value.
3299 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3300 u64 *sptep, u64 old_spte, u64 new_spte)
3304 WARN_ON(!sp->role.direct);
3307 * Theoretically we could also set dirty bit (and flush TLB) here in
3308 * order to eliminate unnecessary PML logging. See comments in
3309 * set_spte. But fast_page_fault is very unlikely to happen with PML
3310 * enabled, so we do not do this. This might result in the same GPA
3311 * to be logged in PML buffer again when the write really happens, and
3312 * eventually to be called by mark_page_dirty twice. But it's also no
3313 * harm. This also avoids the TLB flush needed after setting dirty bit
3314 * so non-PML cases won't be impacted.
3316 * Compare with set_spte where instead shadow_dirty_mask is set.
3318 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3321 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3323 * The gfn of direct spte is stable since it is
3324 * calculated by sp->gfn.
3326 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3327 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3333 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3335 if (fault_err_code & PFERR_FETCH_MASK)
3336 return is_executable_pte(spte);
3338 if (fault_err_code & PFERR_WRITE_MASK)
3339 return is_writable_pte(spte);
3341 /* Fault was on Read access */
3342 return spte & PT_PRESENT_MASK;
3347 * - true: let the vcpu to access on the same address again.
3348 * - false: let the real page fault path to fix it.
3350 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3353 struct kvm_shadow_walk_iterator iterator;
3354 struct kvm_mmu_page *sp;
3355 bool fault_handled = false;
3357 uint retry_count = 0;
3359 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3362 if (!page_fault_can_be_fast(error_code))
3365 walk_shadow_page_lockless_begin(vcpu);
3370 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3371 if (!is_shadow_present_pte(spte) ||
3372 iterator.level < level)
3375 sp = page_header(__pa(iterator.sptep));
3376 if (!is_last_spte(spte, sp->role.level))
3380 * Check whether the memory access that caused the fault would
3381 * still cause it if it were to be performed right now. If not,
3382 * then this is a spurious fault caused by TLB lazily flushed,
3383 * or some other CPU has already fixed the PTE after the
3384 * current CPU took the fault.
3386 * Need not check the access of upper level table entries since
3387 * they are always ACC_ALL.
3389 if (is_access_allowed(error_code, spte)) {
3390 fault_handled = true;
3396 if (is_access_track_spte(spte))
3397 new_spte = restore_acc_track_spte(new_spte);
3400 * Currently, to simplify the code, write-protection can
3401 * be removed in the fast path only if the SPTE was
3402 * write-protected for dirty-logging or access tracking.
3404 if ((error_code & PFERR_WRITE_MASK) &&
3405 spte_can_locklessly_be_made_writable(spte))
3407 new_spte |= PT_WRITABLE_MASK;
3410 * Do not fix write-permission on the large spte. Since
3411 * we only dirty the first page into the dirty-bitmap in
3412 * fast_pf_fix_direct_spte(), other pages are missed
3413 * if its slot has dirty logging enabled.
3415 * Instead, we let the slow page fault path create a
3416 * normal spte to fix the access.
3418 * See the comments in kvm_arch_commit_memory_region().
3420 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3424 /* Verify that the fault can be handled in the fast path */
3425 if (new_spte == spte ||
3426 !is_access_allowed(error_code, new_spte))
3430 * Currently, fast page fault only works for direct mapping
3431 * since the gfn is not stable for indirect shadow page. See
3432 * Documentation/virtual/kvm/locking.txt to get more detail.
3434 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3435 iterator.sptep, spte,
3440 if (++retry_count > 4) {
3441 printk_once(KERN_WARNING
3442 "kvm: Fast #PF retrying more than 4 times.\n");
3448 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3449 spte, fault_handled);
3450 walk_shadow_page_lockless_end(vcpu);
3452 return fault_handled;
3455 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3456 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3457 static int make_mmu_pages_available(struct kvm_vcpu *vcpu);
3459 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3460 gfn_t gfn, bool prefault)
3464 bool force_pt_level = false;
3466 unsigned long mmu_seq;
3467 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3469 level = mapping_level(vcpu, gfn, &force_pt_level);
3470 if (likely(!force_pt_level)) {
3472 * This path builds a PAE pagetable - so we can map
3473 * 2mb pages at maximum. Therefore check if the level
3474 * is larger than that.
3476 if (level > PT_DIRECTORY_LEVEL)
3477 level = PT_DIRECTORY_LEVEL;
3479 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3482 if (fast_page_fault(vcpu, v, level, error_code))
3483 return RET_PF_RETRY;
3485 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3488 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3489 return RET_PF_RETRY;
3491 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3494 spin_lock(&vcpu->kvm->mmu_lock);
3495 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3497 if (make_mmu_pages_available(vcpu) < 0)
3499 if (likely(!force_pt_level))
3500 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3501 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3502 spin_unlock(&vcpu->kvm->mmu_lock);
3507 spin_unlock(&vcpu->kvm->mmu_lock);
3508 kvm_release_pfn_clean(pfn);
3509 return RET_PF_RETRY;
3512 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3513 struct list_head *invalid_list)
3515 struct kvm_mmu_page *sp;
3517 if (!VALID_PAGE(*root_hpa))
3520 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3522 if (!sp->root_count && sp->role.invalid)
3523 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3525 *root_hpa = INVALID_PAGE;
3528 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3529 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3530 ulong roots_to_free)
3533 LIST_HEAD(invalid_list);
3534 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3536 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3538 /* Before acquiring the MMU lock, see if we need to do any real work. */
3539 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3540 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3541 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3542 VALID_PAGE(mmu->prev_roots[i].hpa))
3545 if (i == KVM_MMU_NUM_PREV_ROOTS)
3549 spin_lock(&vcpu->kvm->mmu_lock);
3551 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3552 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3553 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3556 if (free_active_root) {
3557 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3558 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3559 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3562 for (i = 0; i < 4; ++i)
3563 if (mmu->pae_root[i] != 0)
3564 mmu_free_root_page(vcpu->kvm,
3567 mmu->root_hpa = INVALID_PAGE;
3571 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3572 spin_unlock(&vcpu->kvm->mmu_lock);
3574 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3576 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3580 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3581 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3588 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3590 struct kvm_mmu_page *sp;
3593 if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3594 spin_lock(&vcpu->kvm->mmu_lock);
3595 if(make_mmu_pages_available(vcpu) < 0) {
3596 spin_unlock(&vcpu->kvm->mmu_lock);
3599 sp = kvm_mmu_get_page(vcpu, 0, 0,
3600 vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL);
3602 spin_unlock(&vcpu->kvm->mmu_lock);
3603 vcpu->arch.mmu->root_hpa = __pa(sp->spt);
3604 } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) {
3605 for (i = 0; i < 4; ++i) {
3606 hpa_t root = vcpu->arch.mmu->pae_root[i];
3608 MMU_WARN_ON(VALID_PAGE(root));
3609 spin_lock(&vcpu->kvm->mmu_lock);
3610 if (make_mmu_pages_available(vcpu) < 0) {
3611 spin_unlock(&vcpu->kvm->mmu_lock);
3614 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3615 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3616 root = __pa(sp->spt);
3618 spin_unlock(&vcpu->kvm->mmu_lock);
3619 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3621 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3628 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3630 struct kvm_mmu_page *sp;
3635 root_gfn = vcpu->arch.mmu->get_cr3(vcpu) >> PAGE_SHIFT;
3637 if (mmu_check_root(vcpu, root_gfn))
3641 * Do we shadow a long mode page table? If so we need to
3642 * write-protect the guests page table root.
3644 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3645 hpa_t root = vcpu->arch.mmu->root_hpa;
3647 MMU_WARN_ON(VALID_PAGE(root));
3649 spin_lock(&vcpu->kvm->mmu_lock);
3650 if (make_mmu_pages_available(vcpu) < 0) {
3651 spin_unlock(&vcpu->kvm->mmu_lock);
3654 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3655 vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL);
3656 root = __pa(sp->spt);
3658 spin_unlock(&vcpu->kvm->mmu_lock);
3659 vcpu->arch.mmu->root_hpa = root;
3664 * We shadow a 32 bit page table. This may be a legacy 2-level
3665 * or a PAE 3-level page table. In either case we need to be aware that
3666 * the shadow page table may be a PAE or a long mode page table.
3668 pm_mask = PT_PRESENT_MASK;
3669 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3670 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3672 for (i = 0; i < 4; ++i) {
3673 hpa_t root = vcpu->arch.mmu->pae_root[i];
3675 MMU_WARN_ON(VALID_PAGE(root));
3676 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3677 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3678 if (!(pdptr & PT_PRESENT_MASK)) {
3679 vcpu->arch.mmu->pae_root[i] = 0;
3682 root_gfn = pdptr >> PAGE_SHIFT;
3683 if (mmu_check_root(vcpu, root_gfn))
3686 spin_lock(&vcpu->kvm->mmu_lock);
3687 if (make_mmu_pages_available(vcpu) < 0) {
3688 spin_unlock(&vcpu->kvm->mmu_lock);
3691 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3693 root = __pa(sp->spt);
3695 spin_unlock(&vcpu->kvm->mmu_lock);
3697 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3699 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3702 * If we shadow a 32 bit page table with a long mode page
3703 * table we enter this path.
3705 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3706 if (vcpu->arch.mmu->lm_root == NULL) {
3708 * The additional page necessary for this is only
3709 * allocated on demand.
3714 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3715 if (lm_root == NULL)
3718 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3720 vcpu->arch.mmu->lm_root = lm_root;
3723 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3729 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3731 if (vcpu->arch.mmu->direct_map)
3732 return mmu_alloc_direct_roots(vcpu);
3734 return mmu_alloc_shadow_roots(vcpu);
3737 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3740 struct kvm_mmu_page *sp;
3742 if (vcpu->arch.mmu->direct_map)
3745 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3748 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3750 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3751 hpa_t root = vcpu->arch.mmu->root_hpa;
3752 sp = page_header(root);
3755 * Even if another CPU was marking the SP as unsync-ed
3756 * simultaneously, any guest page table changes are not
3757 * guaranteed to be visible anyway until this VCPU issues a TLB
3758 * flush strictly after those changes are made. We only need to
3759 * ensure that the other CPU sets these flags before any actual
3760 * changes to the page tables are made. The comments in
3761 * mmu_need_write_protect() describe what could go wrong if this
3762 * requirement isn't satisfied.
3764 if (!smp_load_acquire(&sp->unsync) &&
3765 !smp_load_acquire(&sp->unsync_children))
3768 spin_lock(&vcpu->kvm->mmu_lock);
3769 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3771 mmu_sync_children(vcpu, sp);
3773 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3774 spin_unlock(&vcpu->kvm->mmu_lock);
3778 spin_lock(&vcpu->kvm->mmu_lock);
3779 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3781 for (i = 0; i < 4; ++i) {
3782 hpa_t root = vcpu->arch.mmu->pae_root[i];
3784 if (root && VALID_PAGE(root)) {
3785 root &= PT64_BASE_ADDR_MASK;
3786 sp = page_header(root);
3787 mmu_sync_children(vcpu, sp);
3791 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3792 spin_unlock(&vcpu->kvm->mmu_lock);
3794 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3796 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3797 u32 access, struct x86_exception *exception)
3800 exception->error_code = 0;
3804 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3806 struct x86_exception *exception)
3809 exception->error_code = 0;
3810 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3814 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3816 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3818 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3819 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3822 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3824 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3827 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3829 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3832 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3835 * A nested guest cannot use the MMIO cache if it is using nested
3836 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3838 if (mmu_is_nested(vcpu))
3842 return vcpu_match_mmio_gpa(vcpu, addr);
3844 return vcpu_match_mmio_gva(vcpu, addr);
3847 /* return true if reserved bit is detected on spte. */
3849 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3851 struct kvm_shadow_walk_iterator iterator;
3852 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3854 bool reserved = false;
3856 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3859 walk_shadow_page_lockless_begin(vcpu);
3861 for (shadow_walk_init(&iterator, vcpu, addr),
3862 leaf = root = iterator.level;
3863 shadow_walk_okay(&iterator);
3864 __shadow_walk_next(&iterator, spte)) {
3865 spte = mmu_spte_get_lockless(iterator.sptep);
3867 sptes[leaf - 1] = spte;
3870 if (!is_shadow_present_pte(spte))
3873 reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte,
3877 walk_shadow_page_lockless_end(vcpu);
3880 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3882 while (root > leaf) {
3883 pr_err("------ spte 0x%llx level %d.\n",
3884 sptes[root - 1], root);
3893 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3898 if (mmio_info_in_cache(vcpu, addr, direct))
3899 return RET_PF_EMULATE;
3901 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3902 if (WARN_ON(reserved))
3905 if (is_mmio_spte(spte)) {
3906 gfn_t gfn = get_mmio_spte_gfn(spte);
3907 unsigned access = get_mmio_spte_access(spte);
3909 if (!check_mmio_spte(vcpu, spte))
3910 return RET_PF_INVALID;
3915 trace_handle_mmio_page_fault(addr, gfn, access);
3916 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3917 return RET_PF_EMULATE;
3921 * If the page table is zapped by other cpus, let CPU fault again on
3924 return RET_PF_RETRY;
3927 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3928 u32 error_code, gfn_t gfn)
3930 if (unlikely(error_code & PFERR_RSVD_MASK))
3933 if (!(error_code & PFERR_PRESENT_MASK) ||
3934 !(error_code & PFERR_WRITE_MASK))
3938 * guest is writing the page which is write tracked which can
3939 * not be fixed by page fault handler.
3941 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3947 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3949 struct kvm_shadow_walk_iterator iterator;
3952 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3955 walk_shadow_page_lockless_begin(vcpu);
3956 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3957 clear_sp_write_flooding_count(iterator.sptep);
3958 if (!is_shadow_present_pte(spte))
3961 walk_shadow_page_lockless_end(vcpu);
3964 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3965 u32 error_code, bool prefault)
3967 gfn_t gfn = gva >> PAGE_SHIFT;
3970 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3972 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3973 return RET_PF_EMULATE;
3975 r = mmu_topup_memory_caches(vcpu);
3979 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
3982 return nonpaging_map(vcpu, gva & PAGE_MASK,
3983 error_code, gfn, prefault);
3986 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3988 struct kvm_arch_async_pf arch;
3990 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3992 arch.direct_map = vcpu->arch.mmu->direct_map;
3993 arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3995 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3998 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
4000 if (unlikely(!lapic_in_kernel(vcpu) ||
4001 kvm_event_needs_reinjection(vcpu) ||
4002 vcpu->arch.exception.pending))
4005 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
4008 return kvm_x86_ops->interrupt_allowed(vcpu);
4011 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
4012 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
4014 struct kvm_memory_slot *slot;
4018 * Don't expose private memslots to L2.
4020 if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
4021 *pfn = KVM_PFN_NOSLOT;
4025 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
4027 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
4029 return false; /* *pfn has correct page already */
4031 if (!prefault && kvm_can_do_async_pf(vcpu)) {
4032 trace_kvm_try_async_get_page(gva, gfn);
4033 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
4034 trace_kvm_async_pf_doublefault(gva, gfn);
4035 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
4037 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
4041 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
4045 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4046 u64 fault_address, char *insn, int insn_len)
4050 vcpu->arch.l1tf_flush_l1d = true;
4051 switch (vcpu->arch.apf.host_apf_reason) {
4053 trace_kvm_page_fault(fault_address, error_code);
4055 if (kvm_event_needs_reinjection(vcpu))
4056 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4057 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4060 case KVM_PV_REASON_PAGE_NOT_PRESENT:
4061 vcpu->arch.apf.host_apf_reason = 0;
4062 local_irq_disable();
4063 kvm_async_pf_task_wait(fault_address, 0);
4066 case KVM_PV_REASON_PAGE_READY:
4067 vcpu->arch.apf.host_apf_reason = 0;
4068 local_irq_disable();
4069 kvm_async_pf_task_wake(fault_address);
4075 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4078 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
4080 int page_num = KVM_PAGES_PER_HPAGE(level);
4082 gfn &= ~(page_num - 1);
4084 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
4087 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
4093 bool force_pt_level;
4094 gfn_t gfn = gpa >> PAGE_SHIFT;
4095 unsigned long mmu_seq;
4096 int write = error_code & PFERR_WRITE_MASK;
4099 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4101 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4102 return RET_PF_EMULATE;
4104 r = mmu_topup_memory_caches(vcpu);
4108 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
4109 PT_DIRECTORY_LEVEL);
4110 level = mapping_level(vcpu, gfn, &force_pt_level);
4111 if (likely(!force_pt_level)) {
4112 if (level > PT_DIRECTORY_LEVEL &&
4113 !check_hugepage_cache_consistency(vcpu, gfn, level))
4114 level = PT_DIRECTORY_LEVEL;
4115 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4118 if (fast_page_fault(vcpu, gpa, level, error_code))
4119 return RET_PF_RETRY;
4121 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4124 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4125 return RET_PF_RETRY;
4127 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
4130 spin_lock(&vcpu->kvm->mmu_lock);
4131 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4133 if (make_mmu_pages_available(vcpu) < 0)
4135 if (likely(!force_pt_level))
4136 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
4137 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
4138 spin_unlock(&vcpu->kvm->mmu_lock);
4143 spin_unlock(&vcpu->kvm->mmu_lock);
4144 kvm_release_pfn_clean(pfn);
4145 return RET_PF_RETRY;
4148 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4149 struct kvm_mmu *context)
4151 context->page_fault = nonpaging_page_fault;
4152 context->gva_to_gpa = nonpaging_gva_to_gpa;
4153 context->sync_page = nonpaging_sync_page;
4154 context->invlpg = nonpaging_invlpg;
4155 context->update_pte = nonpaging_update_pte;
4156 context->root_level = 0;
4157 context->shadow_root_level = PT32E_ROOT_LEVEL;
4158 context->direct_map = true;
4159 context->nx = false;
4163 * Find out if a previously cached root matching the new CR3/role is available.
4164 * The current root is also inserted into the cache.
4165 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4167 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4168 * false is returned. This root should now be freed by the caller.
4170 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4171 union kvm_mmu_page_role new_role)
4174 struct kvm_mmu_root_info root;
4175 struct kvm_mmu *mmu = vcpu->arch.mmu;
4177 root.cr3 = mmu->get_cr3(vcpu);
4178 root.hpa = mmu->root_hpa;
4180 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4181 swap(root, mmu->prev_roots[i]);
4183 if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) &&
4184 page_header(root.hpa) != NULL &&
4185 new_role.word == page_header(root.hpa)->role.word)
4189 mmu->root_hpa = root.hpa;
4191 return i < KVM_MMU_NUM_PREV_ROOTS;
4194 static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4195 union kvm_mmu_page_role new_role,
4196 bool skip_tlb_flush)
4198 struct kvm_mmu *mmu = vcpu->arch.mmu;
4201 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4202 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4203 * later if necessary.
4205 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4206 mmu->root_level >= PT64_ROOT_4LEVEL) {
4207 if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT))
4210 if (cached_root_available(vcpu, new_cr3, new_role)) {
4211 kvm_make_request(KVM_REQ_LOAD_CR3, vcpu);
4212 if (!skip_tlb_flush) {
4213 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4214 kvm_x86_ops->tlb_flush(vcpu, true);
4218 * The last MMIO access's GVA and GPA are cached in the
4219 * VCPU. When switching to a new CR3, that GVA->GPA
4220 * mapping may no longer be valid. So clear any cached
4221 * MMIO info even when we don't need to sync the shadow
4224 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4226 __clear_sp_write_flooding_count(
4227 page_header(mmu->root_hpa));
4236 static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4237 union kvm_mmu_page_role new_role,
4238 bool skip_tlb_flush)
4240 if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush))
4241 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu,
4242 KVM_MMU_ROOT_CURRENT);
4245 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush)
4247 __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu),
4250 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3);
4252 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4254 return kvm_read_cr3(vcpu);
4257 static void inject_page_fault(struct kvm_vcpu *vcpu,
4258 struct x86_exception *fault)
4260 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
4263 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4264 unsigned access, int *nr_present)
4266 if (unlikely(is_mmio_spte(*sptep))) {
4267 if (gfn != get_mmio_spte_gfn(*sptep)) {
4268 mmu_spte_clear_no_track(sptep);
4273 mark_mmio_spte(vcpu, sptep, gfn, access);
4280 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4281 unsigned level, unsigned gpte)
4284 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4285 * If it is clear, there are no large pages at this level, so clear
4286 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4288 gpte &= level - mmu->last_nonleaf_level;
4291 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4292 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4293 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4295 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4297 return gpte & PT_PAGE_SIZE_MASK;
4300 #define PTTYPE_EPT 18 /* arbitrary */
4301 #define PTTYPE PTTYPE_EPT
4302 #include "paging_tmpl.h"
4306 #include "paging_tmpl.h"
4310 #include "paging_tmpl.h"
4314 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4315 struct rsvd_bits_validate *rsvd_check,
4316 int maxphyaddr, int level, bool nx, bool gbpages,
4319 u64 exb_bit_rsvd = 0;
4320 u64 gbpages_bit_rsvd = 0;
4321 u64 nonleaf_bit8_rsvd = 0;
4323 rsvd_check->bad_mt_xwr = 0;
4326 exb_bit_rsvd = rsvd_bits(63, 63);
4328 gbpages_bit_rsvd = rsvd_bits(7, 7);
4331 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4332 * leaf entries) on AMD CPUs only.
4335 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4338 case PT32_ROOT_LEVEL:
4339 /* no rsvd bits for 2 level 4K page table entries */
4340 rsvd_check->rsvd_bits_mask[0][1] = 0;
4341 rsvd_check->rsvd_bits_mask[0][0] = 0;
4342 rsvd_check->rsvd_bits_mask[1][0] =
4343 rsvd_check->rsvd_bits_mask[0][0];
4346 rsvd_check->rsvd_bits_mask[1][1] = 0;
4350 if (is_cpuid_PSE36())
4351 /* 36bits PSE 4MB page */
4352 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4354 /* 32 bits PSE 4MB page */
4355 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4357 case PT32E_ROOT_LEVEL:
4358 rsvd_check->rsvd_bits_mask[0][2] =
4359 rsvd_bits(maxphyaddr, 63) |
4360 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4361 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4362 rsvd_bits(maxphyaddr, 62); /* PDE */
4363 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4364 rsvd_bits(maxphyaddr, 62); /* PTE */
4365 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4366 rsvd_bits(maxphyaddr, 62) |
4367 rsvd_bits(13, 20); /* large page */
4368 rsvd_check->rsvd_bits_mask[1][0] =
4369 rsvd_check->rsvd_bits_mask[0][0];
4371 case PT64_ROOT_5LEVEL:
4372 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4373 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4374 rsvd_bits(maxphyaddr, 51);
4375 rsvd_check->rsvd_bits_mask[1][4] =
4376 rsvd_check->rsvd_bits_mask[0][4];
4378 case PT64_ROOT_4LEVEL:
4379 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4380 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4381 rsvd_bits(maxphyaddr, 51);
4382 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4383 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4384 rsvd_bits(maxphyaddr, 51);
4385 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4386 rsvd_bits(maxphyaddr, 51);
4387 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4388 rsvd_bits(maxphyaddr, 51);
4389 rsvd_check->rsvd_bits_mask[1][3] =
4390 rsvd_check->rsvd_bits_mask[0][3];
4391 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4392 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4394 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4395 rsvd_bits(maxphyaddr, 51) |
4396 rsvd_bits(13, 20); /* large page */
4397 rsvd_check->rsvd_bits_mask[1][0] =
4398 rsvd_check->rsvd_bits_mask[0][0];
4403 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4404 struct kvm_mmu *context)
4406 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4407 cpuid_maxphyaddr(vcpu), context->root_level,
4409 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4410 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4414 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4415 int maxphyaddr, bool execonly)
4419 rsvd_check->rsvd_bits_mask[0][4] =
4420 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4421 rsvd_check->rsvd_bits_mask[0][3] =
4422 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4423 rsvd_check->rsvd_bits_mask[0][2] =
4424 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4425 rsvd_check->rsvd_bits_mask[0][1] =
4426 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4427 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4430 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4431 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4432 rsvd_check->rsvd_bits_mask[1][2] =
4433 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4434 rsvd_check->rsvd_bits_mask[1][1] =
4435 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4436 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4438 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4439 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4440 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4441 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4442 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4444 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4445 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4447 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4450 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4451 struct kvm_mmu *context, bool execonly)
4453 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4454 cpuid_maxphyaddr(vcpu), execonly);
4458 * the page table on host is the shadow page table for the page
4459 * table in guest or amd nested guest, its mmu features completely
4460 * follow the features in guest.
4463 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4465 bool uses_nx = context->nx ||
4466 context->mmu_role.base.smep_andnot_wp;
4467 struct rsvd_bits_validate *shadow_zero_check;
4471 * Passing "true" to the last argument is okay; it adds a check
4472 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4474 shadow_zero_check = &context->shadow_zero_check;
4475 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4476 boot_cpu_data.x86_phys_bits,
4477 context->shadow_root_level, uses_nx,
4478 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4479 is_pse(vcpu), true);
4481 if (!shadow_me_mask)
4484 for (i = context->shadow_root_level; --i >= 0;) {
4485 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4486 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4490 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4492 static inline bool boot_cpu_is_amd(void)
4494 WARN_ON_ONCE(!tdp_enabled);
4495 return shadow_x_mask == 0;
4499 * the direct page table on host, use as much mmu features as
4500 * possible, however, kvm currently does not do execution-protection.
4503 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4504 struct kvm_mmu *context)
4506 struct rsvd_bits_validate *shadow_zero_check;
4509 shadow_zero_check = &context->shadow_zero_check;
4511 if (boot_cpu_is_amd())
4512 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4513 boot_cpu_data.x86_phys_bits,
4514 context->shadow_root_level, false,
4515 boot_cpu_has(X86_FEATURE_GBPAGES),
4518 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4519 boot_cpu_data.x86_phys_bits,
4522 if (!shadow_me_mask)
4525 for (i = context->shadow_root_level; --i >= 0;) {
4526 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4527 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4532 * as the comments in reset_shadow_zero_bits_mask() except it
4533 * is the shadow page table for intel nested guest.
4536 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4537 struct kvm_mmu *context, bool execonly)
4539 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4540 boot_cpu_data.x86_phys_bits, execonly);
4543 #define BYTE_MASK(access) \
4544 ((1 & (access) ? 2 : 0) | \
4545 (2 & (access) ? 4 : 0) | \
4546 (3 & (access) ? 8 : 0) | \
4547 (4 & (access) ? 16 : 0) | \
4548 (5 & (access) ? 32 : 0) | \
4549 (6 & (access) ? 64 : 0) | \
4550 (7 & (access) ? 128 : 0))
4553 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4554 struct kvm_mmu *mmu, bool ept)
4558 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4559 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4560 const u8 u = BYTE_MASK(ACC_USER_MASK);
4562 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4563 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4564 bool cr0_wp = is_write_protection(vcpu);
4566 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4567 unsigned pfec = byte << 1;
4570 * Each "*f" variable has a 1 bit for each UWX value
4571 * that causes a fault with the given PFEC.
4574 /* Faults from writes to non-writable pages */
4575 u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0;
4576 /* Faults from user mode accesses to supervisor pages */
4577 u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0;
4578 /* Faults from fetches of non-executable pages*/
4579 u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0;
4580 /* Faults from kernel mode fetches of user pages */
4582 /* Faults from kernel mode accesses of user pages */
4586 /* Faults from kernel mode accesses to user pages */
4587 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4589 /* Not really needed: !nx will cause pte.nx to fault */
4593 /* Allow supervisor writes if !cr0.wp */
4595 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4597 /* Disallow supervisor fetches of user code if cr4.smep */
4599 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4602 * SMAP:kernel-mode data accesses from user-mode
4603 * mappings should fault. A fault is considered
4604 * as a SMAP violation if all of the following
4605 * conditions are true:
4606 * - X86_CR4_SMAP is set in CR4
4607 * - A user page is accessed
4608 * - The access is not a fetch
4609 * - Page fault in kernel mode
4610 * - if CPL = 3 or X86_EFLAGS_AC is clear
4612 * Here, we cover the first three conditions.
4613 * The fourth is computed dynamically in permission_fault();
4614 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4615 * *not* subject to SMAP restrictions.
4618 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4621 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4626 * PKU is an additional mechanism by which the paging controls access to
4627 * user-mode addresses based on the value in the PKRU register. Protection
4628 * key violations are reported through a bit in the page fault error code.
4629 * Unlike other bits of the error code, the PK bit is not known at the
4630 * call site of e.g. gva_to_gpa; it must be computed directly in
4631 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4632 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4634 * In particular the following conditions come from the error code, the
4635 * page tables and the machine state:
4636 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4637 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4638 * - PK is always zero if U=0 in the page tables
4639 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4641 * The PKRU bitmask caches the result of these four conditions. The error
4642 * code (minus the P bit) and the page table's U bit form an index into the
4643 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4644 * with the two bits of the PKRU register corresponding to the protection key.
4645 * For the first three conditions above the bits will be 00, thus masking
4646 * away both AD and WD. For all reads or if the last condition holds, WD
4647 * only will be masked away.
4649 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4660 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4661 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4666 wp = is_write_protection(vcpu);
4668 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4669 unsigned pfec, pkey_bits;
4670 bool check_pkey, check_write, ff, uf, wf, pte_user;
4673 ff = pfec & PFERR_FETCH_MASK;
4674 uf = pfec & PFERR_USER_MASK;
4675 wf = pfec & PFERR_WRITE_MASK;
4677 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4678 pte_user = pfec & PFERR_RSVD_MASK;
4681 * Only need to check the access which is not an
4682 * instruction fetch and is to a user page.
4684 check_pkey = (!ff && pte_user);
4686 * write access is controlled by PKRU if it is a
4687 * user access or CR0.WP = 1.
4689 check_write = check_pkey && wf && (uf || wp);
4691 /* PKRU.AD stops both read and write access. */
4692 pkey_bits = !!check_pkey;
4693 /* PKRU.WD stops write access. */
4694 pkey_bits |= (!!check_write) << 1;
4696 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4700 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4702 unsigned root_level = mmu->root_level;
4704 mmu->last_nonleaf_level = root_level;
4705 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4706 mmu->last_nonleaf_level++;
4709 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4710 struct kvm_mmu *context,
4713 context->nx = is_nx(vcpu);
4714 context->root_level = level;
4716 reset_rsvds_bits_mask(vcpu, context);
4717 update_permission_bitmask(vcpu, context, false);
4718 update_pkru_bitmask(vcpu, context, false);
4719 update_last_nonleaf_level(vcpu, context);
4721 MMU_WARN_ON(!is_pae(vcpu));
4722 context->page_fault = paging64_page_fault;
4723 context->gva_to_gpa = paging64_gva_to_gpa;
4724 context->sync_page = paging64_sync_page;
4725 context->invlpg = paging64_invlpg;
4726 context->update_pte = paging64_update_pte;
4727 context->shadow_root_level = level;
4728 context->direct_map = false;
4731 static void paging64_init_context(struct kvm_vcpu *vcpu,
4732 struct kvm_mmu *context)
4734 int root_level = is_la57_mode(vcpu) ?
4735 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4737 paging64_init_context_common(vcpu, context, root_level);
4740 static void paging32_init_context(struct kvm_vcpu *vcpu,
4741 struct kvm_mmu *context)
4743 context->nx = false;
4744 context->root_level = PT32_ROOT_LEVEL;
4746 reset_rsvds_bits_mask(vcpu, context);
4747 update_permission_bitmask(vcpu, context, false);
4748 update_pkru_bitmask(vcpu, context, false);
4749 update_last_nonleaf_level(vcpu, context);
4751 context->page_fault = paging32_page_fault;
4752 context->gva_to_gpa = paging32_gva_to_gpa;
4753 context->sync_page = paging32_sync_page;
4754 context->invlpg = paging32_invlpg;
4755 context->update_pte = paging32_update_pte;
4756 context->shadow_root_level = PT32E_ROOT_LEVEL;
4757 context->direct_map = false;
4760 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4761 struct kvm_mmu *context)
4763 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4766 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4768 union kvm_mmu_extended_role ext = {0};
4770 ext.cr0_pg = !!is_paging(vcpu);
4771 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4772 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4773 ext.cr4_pse = !!is_pse(vcpu);
4774 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4775 ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4782 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4785 union kvm_mmu_role role = {0};
4787 role.base.access = ACC_ALL;
4788 role.base.nxe = !!is_nx(vcpu);
4789 role.base.cr4_pae = !!is_pae(vcpu);
4790 role.base.cr0_wp = is_write_protection(vcpu);
4791 role.base.smm = is_smm(vcpu);
4792 role.base.guest_mode = is_guest_mode(vcpu);
4797 role.ext = kvm_calc_mmu_role_ext(vcpu);
4802 static union kvm_mmu_role
4803 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4805 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4807 role.base.ad_disabled = (shadow_accessed_mask == 0);
4808 role.base.level = kvm_x86_ops->get_tdp_level(vcpu);
4809 role.base.direct = true;
4814 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4816 struct kvm_mmu *context = vcpu->arch.mmu;
4817 union kvm_mmu_role new_role =
4818 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4820 new_role.base.word &= mmu_base_role_mask.word;
4821 if (new_role.as_u64 == context->mmu_role.as_u64)
4824 context->mmu_role.as_u64 = new_role.as_u64;
4825 context->page_fault = tdp_page_fault;
4826 context->sync_page = nonpaging_sync_page;
4827 context->invlpg = nonpaging_invlpg;
4828 context->update_pte = nonpaging_update_pte;
4829 context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
4830 context->direct_map = true;
4831 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4832 context->get_cr3 = get_cr3;
4833 context->get_pdptr = kvm_pdptr_read;
4834 context->inject_page_fault = kvm_inject_page_fault;
4836 if (!is_paging(vcpu)) {
4837 context->nx = false;
4838 context->gva_to_gpa = nonpaging_gva_to_gpa;
4839 context->root_level = 0;
4840 } else if (is_long_mode(vcpu)) {
4841 context->nx = is_nx(vcpu);
4842 context->root_level = is_la57_mode(vcpu) ?
4843 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4844 reset_rsvds_bits_mask(vcpu, context);
4845 context->gva_to_gpa = paging64_gva_to_gpa;
4846 } else if (is_pae(vcpu)) {
4847 context->nx = is_nx(vcpu);
4848 context->root_level = PT32E_ROOT_LEVEL;
4849 reset_rsvds_bits_mask(vcpu, context);
4850 context->gva_to_gpa = paging64_gva_to_gpa;
4852 context->nx = false;
4853 context->root_level = PT32_ROOT_LEVEL;
4854 reset_rsvds_bits_mask(vcpu, context);
4855 context->gva_to_gpa = paging32_gva_to_gpa;
4858 update_permission_bitmask(vcpu, context, false);
4859 update_pkru_bitmask(vcpu, context, false);
4860 update_last_nonleaf_level(vcpu, context);
4861 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4864 static union kvm_mmu_role
4865 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4867 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4869 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4870 !is_write_protection(vcpu);
4871 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4872 !is_write_protection(vcpu);
4873 role.base.direct = !is_paging(vcpu);
4875 if (!is_long_mode(vcpu))
4876 role.base.level = PT32E_ROOT_LEVEL;
4877 else if (is_la57_mode(vcpu))
4878 role.base.level = PT64_ROOT_5LEVEL;
4880 role.base.level = PT64_ROOT_4LEVEL;
4885 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4887 struct kvm_mmu *context = vcpu->arch.mmu;
4888 union kvm_mmu_role new_role =
4889 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4891 new_role.base.word &= mmu_base_role_mask.word;
4892 if (new_role.as_u64 == context->mmu_role.as_u64)
4895 if (!is_paging(vcpu))
4896 nonpaging_init_context(vcpu, context);
4897 else if (is_long_mode(vcpu))
4898 paging64_init_context(vcpu, context);
4899 else if (is_pae(vcpu))
4900 paging32E_init_context(vcpu, context);
4902 paging32_init_context(vcpu, context);
4904 context->mmu_role.as_u64 = new_role.as_u64;
4905 reset_shadow_zero_bits_mask(vcpu, context);
4907 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4909 static union kvm_mmu_role
4910 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4913 union kvm_mmu_role role;
4915 /* Base role is inherited from root_mmu */
4916 role.base.word = vcpu->arch.root_mmu.mmu_role.base.word;
4917 role.ext = kvm_calc_mmu_role_ext(vcpu);
4919 role.base.level = PT64_ROOT_4LEVEL;
4920 role.base.direct = false;
4921 role.base.ad_disabled = !accessed_dirty;
4922 role.base.guest_mode = true;
4923 role.base.access = ACC_ALL;
4925 role.ext.execonly = execonly;
4930 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4931 bool accessed_dirty, gpa_t new_eptp)
4933 struct kvm_mmu *context = vcpu->arch.mmu;
4934 union kvm_mmu_role new_role =
4935 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4938 __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false);
4940 new_role.base.word &= mmu_base_role_mask.word;
4941 if (new_role.as_u64 == context->mmu_role.as_u64)
4944 context->shadow_root_level = PT64_ROOT_4LEVEL;
4947 context->ept_ad = accessed_dirty;
4948 context->page_fault = ept_page_fault;
4949 context->gva_to_gpa = ept_gva_to_gpa;
4950 context->sync_page = ept_sync_page;
4951 context->invlpg = ept_invlpg;
4952 context->update_pte = ept_update_pte;
4953 context->root_level = PT64_ROOT_4LEVEL;
4954 context->direct_map = false;
4955 context->mmu_role.as_u64 = new_role.as_u64;
4957 update_permission_bitmask(vcpu, context, true);
4958 update_pkru_bitmask(vcpu, context, true);
4959 update_last_nonleaf_level(vcpu, context);
4960 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4961 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4963 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4965 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4967 struct kvm_mmu *context = vcpu->arch.mmu;
4969 kvm_init_shadow_mmu(vcpu);
4970 context->set_cr3 = kvm_x86_ops->set_cr3;
4971 context->get_cr3 = get_cr3;
4972 context->get_pdptr = kvm_pdptr_read;
4973 context->inject_page_fault = kvm_inject_page_fault;
4976 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4978 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
4979 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4981 new_role.base.word &= mmu_base_role_mask.word;
4982 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4985 g_context->mmu_role.as_u64 = new_role.as_u64;
4986 g_context->get_cr3 = get_cr3;
4987 g_context->get_pdptr = kvm_pdptr_read;
4988 g_context->inject_page_fault = kvm_inject_page_fault;
4991 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4992 * L1's nested page tables (e.g. EPT12). The nested translation
4993 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4994 * L2's page tables as the first level of translation and L1's
4995 * nested page tables as the second level of translation. Basically
4996 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4998 if (!is_paging(vcpu)) {
4999 g_context->nx = false;
5000 g_context->root_level = 0;
5001 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
5002 } else if (is_long_mode(vcpu)) {
5003 g_context->nx = is_nx(vcpu);
5004 g_context->root_level = is_la57_mode(vcpu) ?
5005 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5006 reset_rsvds_bits_mask(vcpu, g_context);
5007 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5008 } else if (is_pae(vcpu)) {
5009 g_context->nx = is_nx(vcpu);
5010 g_context->root_level = PT32E_ROOT_LEVEL;
5011 reset_rsvds_bits_mask(vcpu, g_context);
5012 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5014 g_context->nx = false;
5015 g_context->root_level = PT32_ROOT_LEVEL;
5016 reset_rsvds_bits_mask(vcpu, g_context);
5017 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
5020 update_permission_bitmask(vcpu, g_context, false);
5021 update_pkru_bitmask(vcpu, g_context, false);
5022 update_last_nonleaf_level(vcpu, g_context);
5025 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
5030 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
5032 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5033 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5036 if (mmu_is_nested(vcpu))
5037 init_kvm_nested_mmu(vcpu);
5038 else if (tdp_enabled)
5039 init_kvm_tdp_mmu(vcpu);
5041 init_kvm_softmmu(vcpu);
5043 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5045 static union kvm_mmu_page_role
5046 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5048 union kvm_mmu_role role;
5051 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
5053 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
5058 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5060 kvm_mmu_unload(vcpu);
5061 kvm_init_mmu(vcpu, true);
5063 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5065 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5069 r = mmu_topup_memory_caches(vcpu);
5072 r = mmu_alloc_roots(vcpu);
5073 kvm_mmu_sync_roots(vcpu);
5076 kvm_mmu_load_cr3(vcpu);
5077 kvm_x86_ops->tlb_flush(vcpu, true);
5081 EXPORT_SYMBOL_GPL(kvm_mmu_load);
5083 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5085 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5086 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5087 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5088 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5090 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
5092 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
5093 struct kvm_mmu_page *sp, u64 *spte,
5096 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
5097 ++vcpu->kvm->stat.mmu_pde_zapped;
5101 ++vcpu->kvm->stat.mmu_pte_updated;
5102 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
5105 static bool need_remote_flush(u64 old, u64 new)
5107 if (!is_shadow_present_pte(old))
5109 if (!is_shadow_present_pte(new))
5111 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5113 old ^= shadow_nx_mask;
5114 new ^= shadow_nx_mask;
5115 return (old & ~new & PT64_PERM_MASK) != 0;
5118 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5125 * Assume that the pte write on a page table of the same type
5126 * as the current vcpu paging mode since we update the sptes only
5127 * when they have the same mode.
5129 if (is_pae(vcpu) && *bytes == 4) {
5130 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5135 if (*bytes == 4 || *bytes == 8) {
5136 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5145 * If we're seeing too many writes to a page, it may no longer be a page table,
5146 * or we may be forking, in which case it is better to unmap the page.
5148 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5151 * Skip write-flooding detected for the sp whose level is 1, because
5152 * it can become unsync, then the guest page is not write-protected.
5154 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
5157 atomic_inc(&sp->write_flooding_count);
5158 return atomic_read(&sp->write_flooding_count) >= 3;
5162 * Misaligned accesses are too much trouble to fix up; also, they usually
5163 * indicate a page is not used as a page table.
5165 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5168 unsigned offset, pte_size, misaligned;
5170 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5171 gpa, bytes, sp->role.word);
5173 offset = offset_in_page(gpa);
5174 pte_size = sp->role.cr4_pae ? 8 : 4;
5177 * Sometimes, the OS only writes the last one bytes to update status
5178 * bits, for example, in linux, andb instruction is used in clear_bit().
5180 if (!(offset & (pte_size - 1)) && bytes == 1)
5183 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5184 misaligned |= bytes < 4;
5189 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5191 unsigned page_offset, quadrant;
5195 page_offset = offset_in_page(gpa);
5196 level = sp->role.level;
5198 if (!sp->role.cr4_pae) {
5199 page_offset <<= 1; /* 32->64 */
5201 * A 32-bit pde maps 4MB while the shadow pdes map
5202 * only 2MB. So we need to double the offset again
5203 * and zap two pdes instead of one.
5205 if (level == PT32_ROOT_LEVEL) {
5206 page_offset &= ~7; /* kill rounding error */
5210 quadrant = page_offset >> PAGE_SHIFT;
5211 page_offset &= ~PAGE_MASK;
5212 if (quadrant != sp->role.quadrant)
5216 spte = &sp->spt[page_offset / sizeof(*spte)];
5220 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5221 const u8 *new, int bytes,
5222 struct kvm_page_track_notifier_node *node)
5224 gfn_t gfn = gpa >> PAGE_SHIFT;
5225 struct kvm_mmu_page *sp;
5226 LIST_HEAD(invalid_list);
5227 u64 entry, gentry, *spte;
5229 bool remote_flush, local_flush;
5232 * If we don't have indirect shadow pages, it means no page is
5233 * write-protected, so we can exit simply.
5235 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5238 remote_flush = local_flush = false;
5240 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5243 * No need to care whether allocation memory is successful
5244 * or not since pte prefetch is skiped if it does not have
5245 * enough objects in the cache.
5247 mmu_topup_memory_caches(vcpu);
5249 spin_lock(&vcpu->kvm->mmu_lock);
5251 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5253 ++vcpu->kvm->stat.mmu_pte_write;
5254 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5256 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5257 if (detect_write_misaligned(sp, gpa, bytes) ||
5258 detect_write_flooding(sp)) {
5259 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5260 ++vcpu->kvm->stat.mmu_flooded;
5264 spte = get_written_sptes(sp, gpa, &npte);
5270 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
5273 mmu_page_zap_pte(vcpu->kvm, sp, spte);
5275 !((sp->role.word ^ base_role)
5276 & mmu_base_role_mask.word) && rmap_can_add(vcpu))
5277 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5278 if (need_remote_flush(entry, *spte))
5279 remote_flush = true;
5283 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5284 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5285 spin_unlock(&vcpu->kvm->mmu_lock);
5288 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5293 if (vcpu->arch.mmu->direct_map)
5296 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5298 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5302 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5304 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
5306 LIST_HEAD(invalid_list);
5308 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
5311 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
5312 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
5315 ++vcpu->kvm->stat.mmu_recycled;
5317 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
5319 if (!kvm_mmu_available_pages(vcpu->kvm))
5324 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
5325 void *insn, int insn_len)
5327 int r, emulation_type = 0;
5328 enum emulation_result er;
5329 bool direct = vcpu->arch.mmu->direct_map;
5331 /* With shadow page tables, fault_address contains a GVA or nGPA. */
5332 if (vcpu->arch.mmu->direct_map) {
5333 vcpu->arch.gpa_available = true;
5334 vcpu->arch.gpa_val = cr2;
5338 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5339 r = handle_mmio_page_fault(vcpu, cr2, direct);
5340 if (r == RET_PF_EMULATE)
5344 if (r == RET_PF_INVALID) {
5345 r = vcpu->arch.mmu->page_fault(vcpu, cr2,
5346 lower_32_bits(error_code),
5348 WARN_ON(r == RET_PF_INVALID);
5351 if (r == RET_PF_RETRY)
5357 * Before emulating the instruction, check if the error code
5358 * was due to a RO violation while translating the guest page.
5359 * This can occur when using nested virtualization with nested
5360 * paging in both guests. If true, we simply unprotect the page
5361 * and resume the guest.
5363 if (vcpu->arch.mmu->direct_map &&
5364 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5365 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
5370 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5371 * optimistically try to just unprotect the page and let the processor
5372 * re-execute the instruction that caused the page fault. Do not allow
5373 * retrying MMIO emulation, as it's not only pointless but could also
5374 * cause us to enter an infinite loop because the processor will keep
5375 * faulting on the non-existent MMIO address. Retrying an instruction
5376 * from a nested guest is also pointless and dangerous as we are only
5377 * explicitly shadowing L1's page tables, i.e. unprotecting something
5378 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5380 if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu))
5381 emulation_type = EMULTYPE_ALLOW_RETRY;
5384 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5385 * This can happen if a guest gets a page-fault on data access but the HW
5386 * table walker is not able to read the instruction page (e.g instruction
5387 * page is not present in memory). In those cases we simply restart the
5390 if (unlikely(insn && !insn_len))
5393 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
5398 case EMULATE_USER_EXIT:
5399 ++vcpu->stat.mmio_exits;
5407 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5409 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5411 struct kvm_mmu *mmu = vcpu->arch.mmu;
5414 /* INVLPG on a * non-canonical address is a NOP according to the SDM. */
5415 if (is_noncanonical_address(gva, vcpu))
5418 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5421 * INVLPG is required to invalidate any global mappings for the VA,
5422 * irrespective of PCID. Since it would take us roughly similar amount
5423 * of work to determine whether any of the prev_root mappings of the VA
5424 * is marked global, or to just sync it blindly, so we might as well
5425 * just always sync it.
5427 * Mappings not reachable via the current cr3 or the prev_roots will be
5428 * synced when switching to that cr3, so nothing needs to be done here
5431 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5432 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5433 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5435 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5436 ++vcpu->stat.invlpg;
5438 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5440 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5442 struct kvm_mmu *mmu = vcpu->arch.mmu;
5443 bool tlb_flush = false;
5446 if (pcid == kvm_get_active_pcid(vcpu)) {
5447 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5451 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5452 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5453 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) {
5454 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5460 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5462 ++vcpu->stat.invlpg;
5465 * Mappings not reachable via the current cr3 or the prev_roots will be
5466 * synced when switching to that cr3, so nothing needs to be done here
5470 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5472 void kvm_enable_tdp(void)
5476 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5478 void kvm_disable_tdp(void)
5480 tdp_enabled = false;
5482 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5485 /* The return value indicates if tlb flush on all vcpus is needed. */
5486 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5488 /* The caller should hold mmu-lock before calling this function. */
5489 static __always_inline bool
5490 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5491 slot_level_handler fn, int start_level, int end_level,
5492 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5494 struct slot_rmap_walk_iterator iterator;
5497 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5498 end_gfn, &iterator) {
5500 flush |= fn(kvm, iterator.rmap);
5502 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5503 if (flush && lock_flush_tlb) {
5504 kvm_flush_remote_tlbs(kvm);
5507 cond_resched_lock(&kvm->mmu_lock);
5511 if (flush && lock_flush_tlb) {
5512 kvm_flush_remote_tlbs(kvm);
5519 static __always_inline bool
5520 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5521 slot_level_handler fn, int start_level, int end_level,
5522 bool lock_flush_tlb)
5524 return slot_handle_level_range(kvm, memslot, fn, start_level,
5525 end_level, memslot->base_gfn,
5526 memslot->base_gfn + memslot->npages - 1,
5530 static __always_inline bool
5531 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5532 slot_level_handler fn, bool lock_flush_tlb)
5534 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5535 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5538 static __always_inline bool
5539 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5540 slot_level_handler fn, bool lock_flush_tlb)
5542 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5543 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5546 static __always_inline bool
5547 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5548 slot_level_handler fn, bool lock_flush_tlb)
5550 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5551 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5554 static void free_mmu_pages(struct kvm_vcpu *vcpu)
5556 free_page((unsigned long)vcpu->arch.mmu->pae_root);
5557 free_page((unsigned long)vcpu->arch.mmu->lm_root);
5560 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
5569 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
5570 * Therefore we need to allocate shadow page tables in the first
5571 * 4GB of memory, which happens to fit the DMA32 zone.
5573 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5577 vcpu->arch.mmu->pae_root = page_address(page);
5578 for (i = 0; i < 4; ++i)
5579 vcpu->arch.mmu->pae_root[i] = INVALID_PAGE;
5584 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5588 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5589 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5591 vcpu->arch.root_mmu.root_hpa = INVALID_PAGE;
5592 vcpu->arch.root_mmu.translate_gpa = translate_gpa;
5593 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5594 vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5596 vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE;
5597 vcpu->arch.guest_mmu.translate_gpa = translate_gpa;
5598 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5599 vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5601 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5602 return alloc_mmu_pages(vcpu);
5605 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5606 struct kvm_memory_slot *slot,
5607 struct kvm_page_track_notifier_node *node)
5609 struct kvm_mmu_page *sp;
5610 LIST_HEAD(invalid_list);
5615 spin_lock(&kvm->mmu_lock);
5617 if (list_empty(&kvm->arch.active_mmu_pages))
5620 flush = slot_handle_all_level(kvm, slot, kvm_zap_rmapp, false);
5622 for (i = 0; i < slot->npages; i++) {
5623 gfn = slot->base_gfn + i;
5625 for_each_valid_sp(kvm, sp, gfn) {
5629 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
5631 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5632 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
5634 cond_resched_lock(&kvm->mmu_lock);
5637 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
5640 spin_unlock(&kvm->mmu_lock);
5643 void kvm_mmu_init_vm(struct kvm *kvm)
5645 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5647 node->track_write = kvm_mmu_pte_write;
5648 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5649 kvm_page_track_register_notifier(kvm, node);
5652 void kvm_mmu_uninit_vm(struct kvm *kvm)
5654 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5656 kvm_page_track_unregister_notifier(kvm, node);
5659 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5661 struct kvm_memslots *slots;
5662 struct kvm_memory_slot *memslot;
5665 spin_lock(&kvm->mmu_lock);
5666 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5667 slots = __kvm_memslots(kvm, i);
5668 kvm_for_each_memslot(memslot, slots) {
5671 start = max(gfn_start, memslot->base_gfn);
5672 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5676 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5677 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5678 start, end - 1, true);
5682 spin_unlock(&kvm->mmu_lock);
5685 static bool slot_rmap_write_protect(struct kvm *kvm,
5686 struct kvm_rmap_head *rmap_head)
5688 return __rmap_write_protect(kvm, rmap_head, false);
5691 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5692 struct kvm_memory_slot *memslot)
5696 spin_lock(&kvm->mmu_lock);
5697 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5699 spin_unlock(&kvm->mmu_lock);
5702 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5703 * which do tlb flush out of mmu-lock should be serialized by
5704 * kvm->slots_lock otherwise tlb flush would be missed.
5706 lockdep_assert_held(&kvm->slots_lock);
5709 * We can flush all the TLBs out of the mmu lock without TLB
5710 * corruption since we just change the spte from writable to
5711 * readonly so that we only need to care the case of changing
5712 * spte from present to present (changing the spte from present
5713 * to nonpresent will flush all the TLBs immediately), in other
5714 * words, the only case we care is mmu_spte_update() where we
5715 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5716 * instead of PT_WRITABLE_MASK, that means it does not depend
5717 * on PT_WRITABLE_MASK anymore.
5720 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5724 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5725 struct kvm_rmap_head *rmap_head)
5728 struct rmap_iterator iter;
5729 int need_tlb_flush = 0;
5731 struct kvm_mmu_page *sp;
5734 for_each_rmap_spte(rmap_head, &iter, sptep) {
5735 sp = page_header(__pa(sptep));
5736 pfn = spte_to_pfn(*sptep);
5739 * We cannot do huge page mapping for indirect shadow pages,
5740 * which are found on the last rmap (level = 1) when not using
5741 * tdp; such shadow pages are synced with the page table in
5742 * the guest, and the guest page table is using 4K page size
5743 * mapping if the indirect sp has level = 1.
5745 if (sp->role.direct &&
5746 !kvm_is_reserved_pfn(pfn) &&
5747 PageTransCompoundMap(pfn_to_page(pfn))) {
5748 pte_list_remove(rmap_head, sptep);
5750 if (kvm_available_flush_tlb_with_range())
5751 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5752 KVM_PAGES_PER_HPAGE(sp->role.level));
5760 return need_tlb_flush;
5763 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5764 const struct kvm_memory_slot *memslot)
5766 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5767 spin_lock(&kvm->mmu_lock);
5768 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5769 kvm_mmu_zap_collapsible_spte, true);
5770 spin_unlock(&kvm->mmu_lock);
5773 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5774 struct kvm_memory_slot *memslot)
5778 spin_lock(&kvm->mmu_lock);
5779 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5780 spin_unlock(&kvm->mmu_lock);
5782 lockdep_assert_held(&kvm->slots_lock);
5785 * It's also safe to flush TLBs out of mmu lock here as currently this
5786 * function is only used for dirty logging, in which case flushing TLB
5787 * out of mmu lock also guarantees no dirty pages will be lost in
5791 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5794 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5796 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5797 struct kvm_memory_slot *memslot)
5801 spin_lock(&kvm->mmu_lock);
5802 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5804 spin_unlock(&kvm->mmu_lock);
5806 /* see kvm_mmu_slot_remove_write_access */
5807 lockdep_assert_held(&kvm->slots_lock);
5810 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5813 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5815 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5816 struct kvm_memory_slot *memslot)
5820 spin_lock(&kvm->mmu_lock);
5821 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5822 spin_unlock(&kvm->mmu_lock);
5824 lockdep_assert_held(&kvm->slots_lock);
5826 /* see kvm_mmu_slot_leaf_clear_dirty */
5828 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5831 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5833 static void __kvm_mmu_zap_all(struct kvm *kvm, bool mmio_only)
5835 struct kvm_mmu_page *sp, *node;
5836 LIST_HEAD(invalid_list);
5839 spin_lock(&kvm->mmu_lock);
5841 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5842 if (mmio_only && !sp->mmio_cached)
5844 if (sp->role.invalid && sp->root_count)
5846 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) {
5847 WARN_ON_ONCE(mmio_only);
5850 if (cond_resched_lock(&kvm->mmu_lock))
5854 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5855 spin_unlock(&kvm->mmu_lock);
5858 void kvm_mmu_zap_all(struct kvm *kvm)
5860 return __kvm_mmu_zap_all(kvm, false);
5863 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5865 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5867 gen &= MMIO_SPTE_GEN_MASK;
5870 * Generation numbers are incremented in multiples of the number of
5871 * address spaces in order to provide unique generations across all
5872 * address spaces. Strip what is effectively the address space
5873 * modifier prior to checking for a wrap of the MMIO generation so
5874 * that a wrap in any address space is detected.
5876 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5879 * The very rare case: if the MMIO generation number has wrapped,
5880 * zap all shadow pages.
5882 if (unlikely(gen == 0)) {
5883 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5884 __kvm_mmu_zap_all(kvm, true);
5888 static unsigned long
5889 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5892 int nr_to_scan = sc->nr_to_scan;
5893 unsigned long freed = 0;
5895 spin_lock(&kvm_lock);
5897 list_for_each_entry(kvm, &vm_list, vm_list) {
5899 LIST_HEAD(invalid_list);
5902 * Never scan more than sc->nr_to_scan VM instances.
5903 * Will not hit this condition practically since we do not try
5904 * to shrink more than one VM and it is very unlikely to see
5905 * !n_used_mmu_pages so many times.
5910 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5911 * here. We may skip a VM instance errorneosly, but we do not
5912 * want to shrink a VM that only started to populate its MMU
5915 if (!kvm->arch.n_used_mmu_pages)
5918 idx = srcu_read_lock(&kvm->srcu);
5919 spin_lock(&kvm->mmu_lock);
5921 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5923 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5925 spin_unlock(&kvm->mmu_lock);
5926 srcu_read_unlock(&kvm->srcu, idx);
5929 * unfair on small ones
5930 * per-vm shrinkers cry out
5931 * sadness comes quickly
5933 list_move_tail(&kvm->vm_list, &vm_list);
5937 spin_unlock(&kvm_lock);
5941 static unsigned long
5942 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5944 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5947 static struct shrinker mmu_shrinker = {
5948 .count_objects = mmu_shrink_count,
5949 .scan_objects = mmu_shrink_scan,
5950 .seeks = DEFAULT_SEEKS * 10,
5953 static void mmu_destroy_caches(void)
5955 kmem_cache_destroy(pte_list_desc_cache);
5956 kmem_cache_destroy(mmu_page_header_cache);
5959 int kvm_mmu_module_init(void)
5964 * MMU roles use union aliasing which is, generally speaking, an
5965 * undefined behavior. However, we supposedly know how compilers behave
5966 * and the current status quo is unlikely to change. Guardians below are
5967 * supposed to let us know if the assumption becomes false.
5969 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5970 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5971 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5973 kvm_mmu_reset_all_pte_masks();
5975 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5976 sizeof(struct pte_list_desc),
5977 0, SLAB_ACCOUNT, NULL);
5978 if (!pte_list_desc_cache)
5981 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5982 sizeof(struct kvm_mmu_page),
5983 0, SLAB_ACCOUNT, NULL);
5984 if (!mmu_page_header_cache)
5987 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5990 ret = register_shrinker(&mmu_shrinker);
5997 mmu_destroy_caches();
6002 * Calculate mmu pages needed for kvm.
6004 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
6006 unsigned int nr_mmu_pages;
6007 unsigned int nr_pages = 0;
6008 struct kvm_memslots *slots;
6009 struct kvm_memory_slot *memslot;
6012 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6013 slots = __kvm_memslots(kvm, i);
6015 kvm_for_each_memslot(memslot, slots)
6016 nr_pages += memslot->npages;
6019 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6020 nr_mmu_pages = max(nr_mmu_pages,
6021 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
6023 return nr_mmu_pages;
6026 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6028 kvm_mmu_unload(vcpu);
6029 free_mmu_pages(vcpu);
6030 mmu_free_memory_caches(vcpu);
6033 void kvm_mmu_module_exit(void)
6035 mmu_destroy_caches();
6036 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6037 unregister_shrinker(&mmu_shrinker);
6038 mmu_audit_disable();