1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Scene Change Detection driver
5 * Copyright (C) 2018 Xilinx, Inc.
7 * Authors: Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
8 * Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
11 #ifndef _XILINX_SCENECHANGE_H_
12 #define _XILINX_SCENECHANGE_H_
14 #include <linux/bitops.h>
15 #include <linux/dmaengine.h>
16 #include <linux/interrupt.h>
18 #include <linux/mutex.h>
19 #include <linux/spinlock.h>
21 #include <media/v4l2-subdev.h>
28 /* Register/Descriptor Offsets */
29 #define XSCD_CTRL_OFFSET 0x000
30 #define XSCD_CTRL_AP_START BIT(0)
31 #define XSCD_CTRL_AP_DONE BIT(1)
32 #define XSCD_CTRL_AP_IDLE BIT(2)
33 #define XSCD_CTRL_AP_READY BIT(3)
34 #define XSCD_CTRL_AUTO_RESTART BIT(7)
36 #define XSCD_GIE_OFFSET 0x004
37 #define XSCD_GIE_EN BIT(0)
39 #define XSCD_IE_OFFSET 0x008
40 #define XSCD_IE_AP_DONE BIT(0)
41 #define XSCD_IE_AP_READY BIT(1)
43 #define XSCD_ISR_OFFSET 0x00c
44 #define XSCD_WIDTH_OFFSET 0x010
45 #define XSCD_HEIGHT_OFFSET 0x018
46 #define XSCD_STRIDE_OFFSET 0x020
47 #define XSCD_VID_FMT_OFFSET 0x028
48 #define XSCD_VID_FMT_RGB 0
49 #define XSCD_VID_FMT_YUV_444 1
50 #define XSCD_VID_FMT_YUV_422 2
51 #define XSCD_VID_FMT_YUV_420 3
52 #define XSCD_VID_FMT_Y8 24
53 #define XSCD_VID_FMT_Y10 25
55 #define XSCD_SUBSAMPLE_OFFSET 0x030
56 #define XSCD_SAD_OFFSET 0x038
57 #define XSCD_ADDR_OFFSET 0x040
58 #define XSCD_CHAN_OFFSET 0x100
59 #define XSCD_CHAN_EN_OFFSET 0x780
61 #define XSCD_MAX_CHANNELS 8
63 /****************************** PROTOTYPES ************************************/
68 * struct xscd_dma_desc - DMA channel
69 * @luma_plane_addr: Luma plane buffer address
70 * @vsize: width of the luma frame
71 * @hsize: height of the luma frame
72 * @stride: stride of the luma frame
74 struct xscd_dma_desc {
75 dma_addr_t luma_plane_addr;
82 * struct xscd_dma_tx_descriptor - Per Transaction structure
83 * @async_tx: Async transaction descriptor
84 * @sw: Software Descriptor
85 * @node: Node in the channel descriptor list
87 struct xscd_dma_tx_descriptor {
88 struct dma_async_tx_descriptor async_tx;
89 struct xscd_dma_desc sw;
90 struct list_head node;
93 static inline struct xscd_dma_tx_descriptor *
94 to_xscd_dma_tx_descriptor(struct dma_async_tx_descriptor *tx)
96 return container_of(tx, struct xscd_dma_tx_descriptor, async_tx);
100 * struct xscd_dma_chan - DMA Channel structure
102 * @iomem: I/O memory address of the channel registers
103 * @lock: Descriptor operation lock
104 * @chan_node: Member of a list of framebuffer channel instances
105 * @pending_list: Descriptors waiting
106 * @done_list: Complete descriptors
107 * @staged_desc: Next buffer to be programmed
108 * @active_desc: Currently active buffer being read/written to
109 * @common: DMA common channel
110 * @idle: Channel idle state
111 * @tasklet: Cleanup work after irq
112 * @id: scene change channel ID
113 * @en: Channel is enabled
114 * @valid_interrupt: Valid interrupt for the channel
116 struct xscd_dma_chan {
117 struct xscd_device *xscd;
120 /* Descriptor operation Lock */
122 struct list_head chan_node;
123 struct list_head pending_list;
124 struct list_head done_list;
125 struct xscd_dma_tx_descriptor *staged_desc;
126 struct xscd_dma_tx_descriptor *active_desc;
127 struct dma_chan common;
129 struct tasklet_struct tasklet;
132 bool valid_interrupt;
135 static inline struct xscd_dma_chan *to_xscd_dma_chan(struct dma_chan *chan)
137 return container_of(chan, struct xscd_dma_chan, common);
141 * struct xscd_chan - Video Stream structure
142 * @id: scene change channel ID
143 * @iomem: I/O memory address of the channel registers
145 * @subdev: V4L2 subdevice
147 * @format: active V4L2 media bus format for the pad
148 * @event: scene change event
149 * @dmachan: dma channel part of the scenechange stream
150 * @lock: lock to protect active stream count variable
155 struct xscd_device *xscd;
156 struct v4l2_subdev subdev;
157 struct media_pad pads[2];
158 struct v4l2_mbus_framefmt format;
159 struct v4l2_event event;
160 struct xscd_dma_chan dmachan;
162 /* Lock to protect active stream count */
166 static inline struct xscd_chan *to_xscd_chan(struct v4l2_subdev *subdev)
168 return container_of(subdev, struct xscd_chan, subdev);
172 * struct xscd_device - Xilinx Scene Change Detection device structure
174 * @iomem: device I/O register space remapped to kernel virtual memory
175 * @rst_gpio: reset GPIO
176 * @clk: video core clock
178 * @memory_based: Flag to identify memory based mode
179 * @num_streams: Number of streams in the design
180 * @chans: video stream instances
181 * @dma_device: DMA device structure
182 * @channels: DMA channels
183 * @active_streams: Number of active streams
188 struct gpio_desc *rst_gpio;
195 struct xscd_chan *chans;
197 struct dma_device dma_device;
198 struct xscd_dma_chan *channels[XSCD_MAX_CHANNELS];
203 * Register related operations
205 static inline u32 xscd_read(void __iomem *iomem, u32 addr)
207 return ioread32(iomem + addr);
210 static inline void xscd_write(void __iomem *iomem, u32 addr, u32 value)
212 iowrite32(value, iomem + addr);
215 static inline void xscd_clr(void __iomem *iomem, u32 addr, u32 clr)
217 xscd_write(iomem, addr, xscd_read(iomem, addr) & ~clr);
220 static inline void xscd_set(void __iomem *iomem, u32 addr, u32 set)
222 xscd_write(iomem, addr, xscd_read(iomem, addr) | set);
225 void xscd_dma_start_transfer(struct xscd_dma_chan *chan);
226 void xscd_dma_start(struct xscd_dma_chan *chan);
227 void xscd_dma_chan_enable(struct xscd_dma_chan *chan, int chan_en);
228 void xscd_dma_reset(struct xscd_dma_chan *chan);
229 void xscd_dma_halt(struct xscd_dma_chan *chan);
230 void xscd_dma_irq_handler(struct xscd_device *xscd);
231 int xscd_dma_init(struct xscd_device *xscd);
232 void xscd_dma_cleanup(struct xscd_device *xscd);
234 void xscd_chan_irq_handler(struct xscd_chan *chan);
235 int xscd_chan_init(struct xscd_device *xscd, unsigned int chan_id,
236 struct device_node *node);