arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU106
   4  *
   5  * (C) Copyright 2016, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU106 RevA";
  20         compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <108>; /* down */
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &can1 {
  71         status = "okay";
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_can1_default>;
  74 };
  75
  76 &dcc {
  77         status = "okay";
  78 };
  79
  80 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  81 &fpd_dma_chan1 {
  82         status = "okay";
  83 };
  84
  85 &fpd_dma_chan2 {
  86         status = "okay";
  87 };
  88
  89 &fpd_dma_chan3 {
  90         status = "okay";
  91 };
  92
  93 &fpd_dma_chan4 {
  94         status = "okay";
  95 };
  96
  97 &fpd_dma_chan5 {
  98         status = "okay";
  99 };
 100
 101 &fpd_dma_chan6 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan7 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan8 {
 110         status = "okay";
 111 };
 112
 113 &gem3 {
 114         status = "okay";
 115         phy-handle = <&phy0>;
 116         phy-mode = "rgmii-id";
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gem3_default>;
 119         phy0: phy@c {
 120                 reg = <0xc>;
 121                 ti,rx-internal-delay = <0x8>;
 122                 ti,tx-internal-delay = <0xa>;
 123                 ti,fifo-depth = <0x1>;
 124                 ti,rxctrl-strap-worka;
 125         };
 126 };
 127
 128 &gpio {
 129         status = "okay";
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_gpio_default>;
 132 };
 133
 134 &gpu {
 135         status = "okay";
 136 };
 137
 138 &i2c0 {
 139         status = "okay";
 140         clock-frequency = <400000>;
 141         pinctrl-names = "default", "gpio";
 142         pinctrl-0 = <&pinctrl_i2c0_default>;
 143         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 144         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 145         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 146
 147         tca6416_u97: gpio@20 {
 148                 compatible = "ti,tca6416";
 149                 reg = <0x20>;
 150                 gpio-controller; /* interrupt not connected */
 151                 #gpio-cells = <2>;
 152                 /*
 153                  * IRQ not connected
 154                  * Lines:
 155                  * 0 - SFP_SI5328_INT_ALM
 156                  * 1 - HDMI_SI5328_INT_ALM
 157                  * 5 - IIC_MUX_RESET_B
 158                  * 6 - GEM3_EXP_RESET_B
 159                  * 10 - FMC_HPC0_PRSNT_M2C_B
 160                  * 11 - FMC_HPC1_PRSNT_M2C_B
 161                  * 2-4, 7, 12-17 - not connected
 162                  */
 163         };
 164
 165         tca6416_u61: gpio@21 {
 166                 compatible = "ti,tca6416";
 167                 reg = <0x21>;
 168                 gpio-controller;
 169                 #gpio-cells = <2>;
 170                 /*
 171                  * IRQ not connected
 172                  * Lines:
 173                  * 0 - VCCPSPLL_EN
 174                  * 1 - MGTRAVCC_EN
 175                  * 2 - MGTRAVTT_EN
 176                  * 3 - VCCPSDDRPLL_EN
 177                  * 4 - MIO26_PMU_INPUT_LS
 178                  * 5 - PL_PMBUS_ALERT
 179                  * 6 - PS_PMBUS_ALERT
 180                  * 7 - MAXIM_PMBUS_ALERT
 181                  * 10 - PL_DDR4_VTERM_EN
 182                  * 11 - PL_DDR4_VPP_2V5_EN
 183                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 184                  * 13 - PS_DIMM_SUSPEND_EN
 185                  * 14 - PS_DDR4_VTERM_EN
 186                  * 15 - PS_DDR4_VPP_2V5_EN
 187                  * 16 - 17 - not connected
 188                  */
 189         };
 190
 191         i2c-mux@75 { /* u60 */
 192                 compatible = "nxp,pca9544";
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195                 reg = <0x75>;
 196                 i2c@0 {
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                         reg = <0>;
 200                         /* PS_PMBUS */
 201                         ina226@40 { /* u76 */
 202                                 compatible = "ti,ina226";
 203                                 reg = <0x40>;
 204                                 shunt-resistor = <5000>;
 205                         };
 206                         ina226@41 { /* u77 */
 207                                 compatible = "ti,ina226";
 208                                 reg = <0x41>;
 209                                 shunt-resistor = <5000>;
 210                         };
 211                         ina226@42 { /* u78 */
 212                                 compatible = "ti,ina226";
 213                                 reg = <0x42>;
 214                                 shunt-resistor = <5000>;
 215                         };
 216                         ina226@43 { /* u87 */
 217                                 compatible = "ti,ina226";
 218                                 reg = <0x43>;
 219                                 shunt-resistor = <5000>;
 220                         };
 221                         ina226@44 { /* u85 */
 222                                 compatible = "ti,ina226";
 223                                 reg = <0x44>;
 224                                 shunt-resistor = <5000>;
 225                         };
 226                         ina226@45 { /* u86 */
 227                                 compatible = "ti,ina226";
 228                                 reg = <0x45>;
 229                                 shunt-resistor = <5000>;
 230                         };
 231                         ina226@46 { /* u93 */
 232                                 compatible = "ti,ina226";
 233                                 reg = <0x46>;
 234                                 shunt-resistor = <5000>;
 235                         };
 236                         ina226@47 { /* u88 */
 237                                 compatible = "ti,ina226";
 238                                 reg = <0x47>;
 239                                 shunt-resistor = <5000>;
 240                         };
 241                         ina226@4a { /* u15 */
 242                                 compatible = "ti,ina226";
 243                                 reg = <0x4a>;
 244                                 shunt-resistor = <5000>;
 245                         };
 246                         ina226@4b { /* u92 */
 247                                 compatible = "ti,ina226";
 248                                 reg = <0x4b>;
 249                                 shunt-resistor = <5000>;
 250                         };
 251                 };
 252                 i2c@1 {
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         reg = <1>;
 256                         /* PL_PMBUS */
 257                         ina226@40 { /* u79 */
 258                                 compatible = "ti,ina226";
 259                                 reg = <0x40>;
 260                                 shunt-resistor = <2000>;
 261                         };
 262                         ina226@41 { /* u81 */
 263                                 compatible = "ti,ina226";
 264                                 reg = <0x41>;
 265                                 shunt-resistor = <5000>;
 266                         };
 267                         ina226@42 { /* u80 */
 268                                 compatible = "ti,ina226";
 269                                 reg = <0x42>;
 270                                 shunt-resistor = <5000>;
 271                         };
 272                         ina226@43 { /* u84 */
 273                                 compatible = "ti,ina226";
 274                                 reg = <0x43>;
 275                                 shunt-resistor = <5000>;
 276                         };
 277                         ina226@44 { /* u16 */
 278                                 compatible = "ti,ina226";
 279                                 reg = <0x44>;
 280                                 shunt-resistor = <5000>;
 281                         };
 282                         ina226@45 { /* u65 */
 283                                 compatible = "ti,ina226";
 284                                 reg = <0x45>;
 285                                 shunt-resistor = <5000>;
 286                         };
 287                         ina226@46 { /* u74 */
 288                                 compatible = "ti,ina226";
 289                                 reg = <0x46>;
 290                                 shunt-resistor = <5000>;
 291                         };
 292                         ina226@47 { /* u75 */
 293                                 compatible = "ti,ina226";
 294                                 reg = <0x47>;
 295                                 shunt-resistor = <5000>;
 296                         };
 297                 };
 298                 i2c@2 {
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         reg = <2>;
 302                         /* MAXIM_PMBUS - 00 */
 303                         max15301@a { /* u46 */
 304                                 compatible = "maxim,max15301";
 305                                 reg = <0xa>;
 306                         };
 307                         max15303@b { /* u4 */
 308                                 compatible = "maxim,max15303";
 309                                 reg = <0xb>;
 310                         };
 311                         max15303@10 { /* u13 */
 312                                 compatible = "maxim,max15303";
 313                                 reg = <0x10>;
 314                         };
 315                         max15301@13 { /* u47 */
 316                                 compatible = "maxim,max15301";
 317                                 reg = <0x13>;
 318                         };
 319                         max15303@14 { /* u7 */
 320                                 compatible = "maxim,max15303";
 321                                 reg = <0x14>;
 322                         };
 323                         max15303@15 { /* u6 */
 324                                 compatible = "maxim,max15303";
 325                                 reg = <0x15>;
 326                         };
 327                         max15303@16 { /* u10 */
 328                                 compatible = "maxim,max15303";
 329                                 reg = <0x16>;
 330                         };
 331                         max15303@17 { /* u9 */
 332                                 compatible = "maxim,max15303";
 333                                 reg = <0x17>;
 334                         };
 335                         max15301@18 { /* u63 */
 336                                 compatible = "maxim,max15301";
 337                                 reg = <0x18>;
 338                         };
 339                         max15303@1a { /* u49 */
 340                                 compatible = "maxim,max15303";
 341                                 reg = <0x1a>;
 342                         };
 343                         max15303@1b { /* u8 */
 344                                 compatible = "maxim,max15303";
 345                                 reg = <0x1b>;
 346                         };
 347                         max15303@1d { /* u18 */
 348                                 compatible = "maxim,max15303";
 349                                 reg = <0x1d>;
 350                         };
 351
 352                         max20751@72 { /* u95 */
 353                                 compatible = "maxim,max20751";
 354                                 reg = <0x72>;
 355                         };
 356                         max20751@73 { /* u96 */
 357                                 compatible = "maxim,max20751";
 358                                 reg = <0x73>;
 359                         };
 360                 };
 361                 /* Bus 3 is not connected */
 362         };
 363
 364         /* FIXME PMOD - j160 */
 365         /* FIXME MSP430F - u41 - not detected */
 366 };
 367
 368 &i2c1 {
 369         status = "okay";
 370         clock-frequency = <400000>;
 371         pinctrl-names = "default", "gpio";
 372         pinctrl-0 = <&pinctrl_i2c1_default>;
 373         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 374         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 375         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 376
 377         /* FIXME PL i2c via PCA9306 - u45 */
 378         /* FIXME MSP430 - u41 - not detected */
 379         i2c-mux@74 { /* u34 */
 380                 compatible = "nxp,pca9548";
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 reg = <0x74>;
 384                 i2c@0 {
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         reg = <0>;
 388                         /*
 389                          * IIC_EEPROM 1kB memory which uses 256B blocks
 390                          * where every block has different address.
 391                          *    0 - 256B address 0x54
 392                          * 256B - 512B address 0x55
 393                          * 512B - 768B address 0x56
 394                          * 768B - 1024B address 0x57
 395                          */
 396                         eeprom@54 { /* u23 */
 397                                 compatible = "atmel,24c08";
 398                                 reg = <0x54>;
 399                         };
 400                 };
 401                 i2c@1 {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         reg = <1>;
 405                         si5341: clock-generator@36 { /* SI5341 - u69 */
 406                                 compatible = "si5341";
 407                                 reg = <0x36>;
 408                         };
 409
 410                 };
 411                 i2c@2 {
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         reg = <2>;
 415                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 416                                 #clock-cells = <0>;
 417                                 compatible = "silabs,si570";
 418                                 reg = <0x5d>;
 419                                 temperature-stability = <50>;
 420                                 factory-fout = <300000000>;
 421                                 clock-frequency = <300000000>;
 422                         };
 423                 };
 424                 i2c@3 {
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         reg = <3>;
 428                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 429                                 #clock-cells = <0>;
 430                                 compatible = "silabs,si570";
 431                                 reg = <0x5d>;
 432                                 temperature-stability = <50>; /* copy from zc702 */
 433                                 factory-fout = <156250000>;
 434                                 clock-frequency = <148500000>;
 435                         };
 436                 };
 437                 i2c@4 {
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         reg = <4>;
 441                         si5328: clock-generator@69 {/* SI5328 - u20 */
 442                                 compatible = "silabs,si5328";
 443                                 reg = <0x69>;
 444                         };
 445                 };
 446                 i2c@5 {
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <5>; /* FAN controller */
 450                         temp@4c {/* lm96163 - u128 */
 451                                 compatible = "national,lm96163";
 452                                 reg = <0x4c>; /* FIXME */
 453                         };
 454                 };
 455                 /* 6 - 7 unconnected */
 456         };
 457
 458         i2c-mux@75 {
 459                 compatible = "nxp,pca9548"; /* u135 */
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 reg = <0x75>;
 463
 464                 i2c@0 {
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         reg = <0>;
 468                         /* HPC0_IIC */
 469                 };
 470                 i2c@1 {
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         reg = <1>;
 474                         /* HPC1_IIC */
 475                 };
 476                 i2c@2 {
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         reg = <2>;
 480                         /* SYSMON */
 481                 };
 482                 i2c@3 {
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <3>;
 486                         /* DDR4 SODIMM */
 487                         dev@19 { /* u-boot detection */
 488                                 compatible = "xxx";
 489                                 reg = <0x19>;
 490                         };
 491                         dev@30 { /* u-boot detection */
 492                                 compatible = "xxx";
 493                                 reg = <0x30>;
 494                         };
 495                         dev@35 { /* u-boot detection */
 496                                 compatible = "xxx";
 497                                 reg = <0x35>;
 498                         };
 499                         dev@36 { /* u-boot detection */
 500                                 compatible = "xxx";
 501                                 reg = <0x36>;
 502                         };
 503                         dev@51 { /* u-boot detection - maybe SPD */
 504                                 compatible = "xxx";
 505                                 reg = <0x51>;
 506                         };
 507                 };
 508                 i2c@4 {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         reg = <4>;
 512                         /* SEP 3 */
 513                 };
 514                 i2c@5 {
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         reg = <5>;
 518                         /* SEP 2 */
 519                 };
 520                 i2c@6 {
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         reg = <6>;
 524                         /* SEP 1 */
 525                 };
 526                 i2c@7 {
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         reg = <7>;
 530                         /* SEP 0 */
 531                 };
 532         };
 533 };
 534
 535 &pinctrl0 {
 536         status = "okay";
 537         pinctrl_i2c0_default: i2c0-default {
 538                 mux {
 539                         groups = "i2c0_3_grp";
 540                         function = "i2c0";
 541                 };
 542
 543                 conf {
 544                         groups = "i2c0_3_grp";
 545                         bias-pull-up;
 546                         slew-rate = <SLEW_RATE_SLOW>;
 547                         io-standard = <IO_STANDARD_LVCMOS18>;
 548                 };
 549         };
 550
 551         pinctrl_i2c0_gpio: i2c0-gpio {
 552                 mux {
 553                         groups = "gpio0_14_grp", "gpio0_15_grp";
 554                         function = "gpio0";
 555                 };
 556
 557                 conf {
 558                         groups = "gpio0_14_grp", "gpio0_15_grp";
 559                         slew-rate = <SLEW_RATE_SLOW>;
 560                         io-standard = <IO_STANDARD_LVCMOS18>;
 561                 };
 562         };
 563
 564         pinctrl_i2c1_default: i2c1-default {
 565                 mux {
 566                         groups = "i2c1_4_grp";
 567                         function = "i2c1";
 568                 };
 569
 570                 conf {
 571                         groups = "i2c1_4_grp";
 572                         bias-pull-up;
 573                         slew-rate = <SLEW_RATE_SLOW>;
 574                         io-standard = <IO_STANDARD_LVCMOS18>;
 575                 };
 576         };
 577
 578         pinctrl_i2c1_gpio: i2c1-gpio {
 579                 mux {
 580                         groups = "gpio0_16_grp", "gpio0_17_grp";
 581                         function = "gpio0";
 582                 };
 583
 584                 conf {
 585                         groups = "gpio0_16_grp", "gpio0_17_grp";
 586                         slew-rate = <SLEW_RATE_SLOW>;
 587                         io-standard = <IO_STANDARD_LVCMOS18>;
 588                 };
 589         };
 590
 591         pinctrl_uart0_default: uart0-default {
 592                 mux {
 593                         groups = "uart0_4_grp";
 594                         function = "uart0";
 595                 };
 596
 597                 conf {
 598                         groups = "uart0_4_grp";
 599                         slew-rate = <SLEW_RATE_SLOW>;
 600                         io-standard = <IO_STANDARD_LVCMOS18>;
 601                 };
 602
 603                 conf-rx {
 604                         pins = "MIO18";
 605                         bias-high-impedance;
 606                 };
 607
 608                 conf-tx {
 609                         pins = "MIO19";
 610                         bias-disable;
 611                 };
 612         };
 613
 614         pinctrl_uart1_default: uart1-default {
 615                 mux {
 616                         groups = "uart1_5_grp";
 617                         function = "uart1";
 618                 };
 619
 620                 conf {
 621                         groups = "uart1_5_grp";
 622                         slew-rate = <SLEW_RATE_SLOW>;
 623                         io-standard = <IO_STANDARD_LVCMOS18>;
 624                 };
 625
 626                 conf-rx {
 627                         pins = "MIO21";
 628                         bias-high-impedance;
 629                 };
 630
 631                 conf-tx {
 632                         pins = "MIO20";
 633                         bias-disable;
 634                 };
 635         };
 636
 637         pinctrl_usb0_default: usb0-default {
 638                 mux {
 639                         groups = "usb0_0_grp";
 640                         function = "usb0";
 641                 };
 642
 643                 conf {
 644                         groups = "usb0_0_grp";
 645                         slew-rate = <SLEW_RATE_SLOW>;
 646                         io-standard = <IO_STANDARD_LVCMOS18>;
 647                 };
 648
 649                 conf-rx {
 650                         pins = "MIO52", "MIO53", "MIO55";
 651                         bias-high-impedance;
 652                 };
 653
 654                 conf-tx {
 655                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 656                                "MIO60", "MIO61", "MIO62", "MIO63";
 657                         bias-disable;
 658                 };
 659         };
 660
 661         pinctrl_gem3_default: gem3-default {
 662                 mux {
 663                         function = "ethernet3";
 664                         groups = "ethernet3_0_grp";
 665                 };
 666
 667                 conf {
 668                         groups = "ethernet3_0_grp";
 669                         slew-rate = <SLEW_RATE_SLOW>;
 670                         io-standard = <IO_STANDARD_LVCMOS18>;
 671                 };
 672
 673                 conf-rx {
 674                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 675                                                                         "MIO75";
 676                         bias-high-impedance;
 677                         low-power-disable;
 678                 };
 679
 680                 conf-tx {
 681                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 682                                                                         "MIO69";
 683                         bias-disable;
 684                         low-power-enable;
 685                 };
 686
 687                 mux-mdio {
 688                         function = "mdio3";
 689                         groups = "mdio3_0_grp";
 690                 };
 691
 692                 conf-mdio {
 693                         groups = "mdio3_0_grp";
 694                         slew-rate = <SLEW_RATE_SLOW>;
 695                         io-standard = <IO_STANDARD_LVCMOS18>;
 696                         bias-disable;
 697                 };
 698         };
 699
 700         pinctrl_can1_default: can1-default {
 701                 mux {
 702                         function = "can1";
 703                         groups = "can1_6_grp";
 704                 };
 705
 706                 conf {
 707                         groups = "can1_6_grp";
 708                         slew-rate = <SLEW_RATE_SLOW>;
 709                         io-standard = <IO_STANDARD_LVCMOS18>;
 710                 };
 711
 712                 conf-rx {
 713                         pins = "MIO25";
 714                         bias-high-impedance;
 715                 };
 716
 717                 conf-tx {
 718                         pins = "MIO24";
 719                         bias-disable;
 720                 };
 721         };
 722
 723         pinctrl_sdhci1_default: sdhci1-default {
 724                 mux {
 725                         groups = "sdio1_0_grp";
 726                         function = "sdio1";
 727                 };
 728
 729                 conf {
 730                         groups = "sdio1_0_grp";
 731                         slew-rate = <SLEW_RATE_SLOW>;
 732                         io-standard = <IO_STANDARD_LVCMOS18>;
 733                         bias-disable;
 734                 };
 735
 736                 mux-cd {
 737                         groups = "sdio1_cd_0_grp";
 738                         function = "sdio1_cd";
 739                 };
 740
 741                 conf-cd {
 742                         groups = "sdio1_cd_0_grp";
 743                         bias-high-impedance;
 744                         bias-pull-up;
 745                         slew-rate = <SLEW_RATE_SLOW>;
 746                         io-standard = <IO_STANDARD_LVCMOS18>;
 747                 };
 748
 749                 mux-wp {
 750                         groups = "sdio1_wp_0_grp";
 751                         function = "sdio1_wp";
 752                 };
 753
 754                 conf-wp {
 755                         groups = "sdio1_wp_0_grp";
 756                         bias-high-impedance;
 757                         bias-pull-up;
 758                         slew-rate = <SLEW_RATE_SLOW>;
 759                         io-standard = <IO_STANDARD_LVCMOS18>;
 760                 };
 761         };
 762
 763         pinctrl_gpio_default: gpio-default {
 764                 mux {
 765                         function = "gpio0";
 766                         groups = "gpio0_22_grp", "gpio0_23_grp";
 767                 };
 768
 769                 conf {
 770                         groups = "gpio0_22_grp", "gpio0_23_grp";
 771                         slew-rate = <SLEW_RATE_SLOW>;
 772                         io-standard = <IO_STANDARD_LVCMOS18>;
 773                 };
 774
 775                 mux-msp {
 776                         function = "gpio0";
 777                         groups = "gpio0_13_grp", "gpio0_38_grp";
 778                 };
 779
 780                 conf-msp {
 781                         groups = "gpio0_13_grp", "gpio0_38_grp";
 782                         slew-rate = <SLEW_RATE_SLOW>;
 783                         io-standard = <IO_STANDARD_LVCMOS18>;
 784                 };
 785
 786                 conf-pull-up {
 787                         pins = "MIO22";
 788                         bias-pull-up;
 789                 };
 790
 791                 conf-pull-none {
 792                         pins = "MIO13", "MIO23", "MIO38";
 793                         bias-disable;
 794                 };
 795         };
 796 };
 797
 798 &qspi {
 799         status = "okay";
 800         is-dual = <1>;
 801         flash@0 {
 802                 compatible = "m25p80"; /* 32MB */
 803                 #address-cells = <1>;
 804                 #size-cells = <1>;
 805                 reg = <0x0>;
 806                 spi-tx-bus-width = <1>;
 807                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 808                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 809                 partition@qspi-fsbl-uboot { /* for testing purpose */
 810                         label = "qspi-fsbl-uboot";
 811                         reg = <0x0 0x100000>;
 812                 };
 813                 partition@qspi-linux { /* for testing purpose */
 814                         label = "qspi-linux";
 815                         reg = <0x100000 0x500000>;
 816                 };
 817                 partition@qspi-device-tree { /* for testing purpose */
 818                         label = "qspi-device-tree";
 819                         reg = <0x600000 0x20000>;
 820                 };
 821                 partition@qspi-rootfs { /* for testing purpose */
 822                         label = "qspi-rootfs";
 823                         reg = <0x620000 0x5E0000>;
 824                 };
 825         };
 826 };
 827
 828 &rtc {
 829         status = "okay";
 830 };
 831
 832 &sata {
 833         status = "okay";
 834         /* SATA OOB timing settings */
 835         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 836         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 837         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 838         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 839         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 840         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 841         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 842         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 843         phy-names = "sata-phy";
 844         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 845 };
 846
 847 /* SD1 with level shifter */
 848 &sdhci1 {
 849         status = "okay";
 850         pinctrl-names = "default";
 851         pinctrl-0 = <&pinctrl_sdhci1_default>;
 852         no-1-8-v;
 853         xlnx,mio_bank = <1>;
 854 };
 855
 856 &serdes {
 857         status = "okay";
 858 };
 859
 860 &uart0 {
 861         status = "okay";
 862         pinctrl-names = "default";
 863         pinctrl-0 = <&pinctrl_uart0_default>;
 864 };
 865
 866 &uart1 {
 867         status = "okay";
 868         pinctrl-names = "default";
 869         pinctrl-0 = <&pinctrl_uart1_default>;
 870 };
 871
 872 /* ULPI SMSC USB3320 */
 873 &usb0 {
 874         status = "okay";
 875         pinctrl-names = "default";
 876         pinctrl-0 = <&pinctrl_usb0_default>;
 877 };
 878
 879 &dwc3_0 {
 880         status = "okay";
 881         dr_mode = "host";
 882         snps,usb3_lpm_capable;
 883         phy-names = "usb3-phy";
 884         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 885 };
 886
 887 &zynqmp_dpsub {
 888         status = "okay";
 889         phy-names = "dp-phy0", "dp-phy1";
 890         phys = <&lane1 PHY_TYPE_DP 0 3 27000000>, <&lane0 PHY_TYPE_DP 1 3 27000000>;
 891 };
 892
 893 &zynqmp_dp_snd_pcm0 {
 894         status = "okay";
 895 };
 896
 897 &zynqmp_dp_snd_pcm1 {
 898         status = "okay";
 899 };
 900
 901 &zynqmp_dp_snd_card0 {
 902         status = "okay";
 903 };
 904
 905 &zynqmp_dp_snd_codec0 {
 906         status = "okay";
 907 };
 908
 909 &xlnx_dpdma {
 910         status = "okay";
 911 };