4 * Copyright (C) 2016 - 2017 Xilinx, Inc.
7 * This driver is developed for SDFEC16 IP. It provides a char device
8 * in sysfs and supports file operations like open(), close() and ioctl().
10 * This program is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef __XILINX_SDFEC_H__
24 #define __XILINX_SDFEC_H__
26 /* Shared LDPC Tables */
27 #define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
28 #define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x103FC)
29 #define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
30 #define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x18FFC)
31 #define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
32 #define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x27FFC)
35 XSDFEC_CODE_INVALID = 0,
41 XSDFEC_INVALID_ORDER = 0,
42 XSDFEC_MAINTAIN_ORDER,
54 XSDFEC_UNKNOWN_MODE = 0,
60 * struct xsdfec_turbo - User data for Turbo Codes
61 * @alg: Algorithm used by Turbo Codes
62 * @scale: Scale Factor
63 * Turbo Code structure to communicate parameters to XSDFEC driver
71 * struct xsdfec_ldpc - User data for LDPC Codes
72 * @n: Number of code word bits
73 * @k: Number of information bits
74 * @psize: Size of sub-matrix
75 * @nlayers: Number of layers in code
76 * @nqc: Quasi Cyclic Number
77 * @nmqc: Number of M-sized QC operations in parity check matrix
78 * @nm: Number of M-size vectors in N
79 * @norm_type: Normalization required or not
80 * @no_packing: Determines if multiple QC ops should be performed
81 * @special_qc: Sub-Matrix property for Circulant weight > 0
82 * @no_final_parity: Decide if final parity check needs to be performed
83 * @max_schedule: Experimental code word scheduling limit
92 * This structure describes the LDPC code that is passed to the driver
111 u32 sc_table[XSDFEC_LDPC_SC_TABLE_ADDR_HIGH -
112 XSDFEC_LDPC_SC_TABLE_ADDR_BASE];
113 u32 la_table[XSDFEC_LDPC_LA_TABLE_ADDR_HIGH -
114 XSDFEC_LDPC_LA_TABLE_ADDR_BASE];
115 u32 qc_table[XSDFEC_LDPC_QC_TABLE_ADDR_HIGH -
116 XSDFEC_LDPC_QC_TABLE_ADDR_BASE];
121 * struct xsdfec_status - Status of SDFEC device
122 * @fec_id: ID of SDFEC instance
123 * @code: The codes being used by the SDFEC instance
124 * @order: Order of Operation
125 * @state: State of the SDFEC device
126 * @mode: Mode of Operation
127 * @activity: Describes if the SDFEC instance is Active
128 * @cecc_count: Count of the Correctable ECC Errors occurred
130 struct xsdfec_status {
132 enum xsdfec_code code;
133 enum xsdfec_order order;
134 enum xsdfec_state state;
135 enum xsdfec_op_mode mode;
141 * struct xsdfec_config - Configuration of SDFEC device
142 * @fec_id: ID of SDFEC instance
143 * @code: The codes being used by the SDFEC instance
144 * @mode: Mode that the SDFEC is operating
145 * @order: Order of Operation
146 * @state: State of the SDFEC device
148 struct xsdfec_config {
150 enum xsdfec_code code;
151 enum xsdfec_op_mode mode;
152 enum xsdfec_order order;
153 enum xsdfec_state state;
157 * struct xsdfec_irq - Enabling or Disabling Interrupts
158 * @enable_isr: If true enables the ISR
159 * @enable_ecc_isr: If true enables the ECC ISR
169 #define XSDFEC_MAGIC 'f'
170 /* ioctl to start sdfec device */
171 #define XSDFEC_START_DEV _IO(XSDFEC_MAGIC, 0)
172 /* ioctl to stop the device */
173 #define XSDFEC_STOP_DEV _IO(XSDFEC_MAGIC, 1)
174 /* ioctl to communicate to the driver that device has been reset */
175 #define XSDFEC_RESET_REQ _IO(XSDFEC_MAGIC, 2)
176 /* ioctl that returns status of sdfec device */
177 #define XSDFEC_GET_STATUS _IOR(XSDFEC_MAGIC, 3, struct xsdfec_status *)
178 /* ioctl to enable or disable irq */
179 #define XSDFEC_SET_IRQ _IOW(XSDFEC_MAGIC, 4, struct xsdfec_irq *)
180 /* ioctl to enable turbo params for sdfec device */
181 #define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 5, struct xsdfec_turbo *)
182 /* ioctl to add an LDPC code to the sdfec ldpc codes */
183 #define XSDFEC_ADD_LDPC _IOW(XSDFEC_MAGIC, 6, struct xsdfec_ldpc *)
184 /* ioctl that returns sdfec device configuration */
185 #define XSDFEC_GET_CONFIG _IOR(XSDFEC_MAGIC, 7, struct xsdfec_config *)
187 #endif /* __XILINX_SDFEC_H__ */