arch/arm64/boot/dts/xilinx/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 / {
  12         compatible = "xlnx,zynqmp";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         operating-points-v2 = <&cpu_opp_table>;
  25                         reg = <0x0>;
  26                         cpu-idle-states = <&CPU_SLEEP_0>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         reg = <0x1>;
  34                         operating-points-v2 = <&cpu_opp_table>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x2>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu3: cpu@3 {
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 idle-states {
  57                         entry-method = "arm,psci";
  58
  59                         CPU_SLEEP_0: cpu-sleep-0 {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x40000000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <300>;
  64                                 exit-latency-us = <600>;
  65                                 min-residency-us = <10000>;
  66                         };
  67                 };
  68         };
  69
  70         cpu_opp_table: cpu_opp_table {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73                 opp00 {
  74                         opp-hz = /bits/ 64 <1199999988>;
  75                         opp-microvolt = <1000000>;
  76                         clock-latency-ns = <500000>;
  77                 };
  78                 opp01 {
  79                         opp-hz = /bits/ 64 <599999994>;
  80                         opp-microvolt = <1000000>;
  81                         clock-latency-ns = <500000>;
  82                 };
  83                 opp02 {
  84                         opp-hz = /bits/ 64 <399999996>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <500000>;
  87                 };
  88                 opp03 {
  89                         opp-hz = /bits/ 64 <299999997>;
  90                         opp-microvolt = <1000000>;
  91                         clock-latency-ns = <500000>;
  92                 };
  93         };
  94
  95         dcc: dcc {
  96                 compatible = "arm,dcc";
  97                 status = "disabled";
  98                 u-boot,dm-pre-reloc;
  99         };
 100
 101         pinctrl0: pinctrl {
 102                 compatible = "xlnx,zynqmp-pinctrl";
 103                 status = "disabled";
 104         };
 105
 106         power-domains {
 107                 compatible = "xlnx,zynqmp-genpd";
 108
 109                 pd_usb0: pd-usb0 {
 110                         #power-domain-cells = <0x0>;
 111                         pd-id = <0x16>;
 112                 };
 113
 114                 pd_usb1: pd-usb1 {
 115                         #power-domain-cells = <0x0>;
 116                         pd-id = <0x17>;
 117                 };
 118
 119                 pd_sata: pd-sata {
 120                         #power-domain-cells = <0x0>;
 121                         pd-id = <0x1c>;
 122                 };
 123
 124                 pd_spi0: pd-spi0 {
 125                         #power-domain-cells = <0x0>;
 126                         pd-id = <0x23>;
 127                 };
 128
 129                 pd_spi1: pd-spi1 {
 130                         #power-domain-cells = <0x0>;
 131                         pd-id = <0x24>;
 132                 };
 133
 134                 pd_uart0: pd-uart0 {
 135                         #power-domain-cells = <0x0>;
 136                         pd-id = <0x21>;
 137                 };
 138
 139                 pd_uart1: pd-uart1 {
 140                         #power-domain-cells = <0x0>;
 141                         pd-id = <0x22>;
 142                 };
 143
 144                 pd_eth0: pd-eth0 {
 145                         #power-domain-cells = <0x0>;
 146                         pd-id = <0x1d>;
 147                 };
 148
 149                 pd_eth1: pd-eth1 {
 150                         #power-domain-cells = <0x0>;
 151                         pd-id = <0x1e>;
 152                 };
 153
 154                 pd_eth2: pd-eth2 {
 155                         #power-domain-cells = <0x0>;
 156                         pd-id = <0x1f>;
 157                 };
 158
 159                 pd_eth3: pd-eth3 {
 160                         #power-domain-cells = <0x0>;
 161                         pd-id = <0x20>;
 162                 };
 163
 164                 pd_i2c0: pd-i2c0 {
 165                         #power-domain-cells = <0x0>;
 166                         pd-id = <0x25>;
 167                 };
 168
 169                 pd_i2c1: pd-i2c1 {
 170                         #power-domain-cells = <0x0>;
 171                         pd-id = <0x26>;
 172                 };
 173
 174                 pd_dp: pd-dp {
 175                         #power-domain-cells = <0x0>;
 176                         pd-id = <0x29>;
 177                 };
 178
 179                 pd_gdma: pd-gdma {
 180                         #power-domain-cells = <0x0>;
 181                         pd-id = <0x2a>;
 182                 };
 183
 184                 pd_adma: pd-adma {
 185                         #power-domain-cells = <0x0>;
 186                         pd-id = <0x2b>;
 187                 };
 188
 189                 pd_ttc0: pd-ttc0 {
 190                         #power-domain-cells = <0x0>;
 191                         pd-id = <0x18>;
 192                 };
 193
 194                 pd_ttc1: pd-ttc1 {
 195                         #power-domain-cells = <0x0>;
 196                         pd-id = <0x19>;
 197                 };
 198
 199                 pd_ttc2: pd-ttc2 {
 200                         #power-domain-cells = <0x0>;
 201                         pd-id = <0x1a>;
 202                 };
 203
 204                 pd_ttc3: pd-ttc3 {
 205                         #power-domain-cells = <0x0>;
 206                         pd-id = <0x1b>;
 207                 };
 208
 209                 pd_sd0: pd-sd0 {
 210                         #power-domain-cells = <0x0>;
 211                         pd-id = <0x27>;
 212                 };
 213
 214                 pd_sd1: pd-sd1 {
 215                         #power-domain-cells = <0x0>;
 216                         pd-id = <0x28>;
 217                 };
 218
 219                 pd_nand: pd-nand {
 220                         #power-domain-cells = <0x0>;
 221                         pd-id = <0x2c>;
 222                 };
 223
 224                 pd_qspi: pd-qspi {
 225                         #power-domain-cells = <0x0>;
 226                         pd-id = <0x2d>;
 227                 };
 228
 229                 pd_gpio: pd-gpio {
 230                         #power-domain-cells = <0x0>;
 231                         pd-id = <0x2e>;
 232                 };
 233
 234                 pd_can0: pd-can0 {
 235                         #power-domain-cells = <0x0>;
 236                         pd-id = <0x2f>;
 237                 };
 238
 239                 pd_can1: pd-can1 {
 240                         #power-domain-cells = <0x0>;
 241                         pd-id = <0x30>;
 242                 };
 243
 244                 pd_pcie: pd-pcie {
 245                         #power-domain-cells = <0x0>;
 246                         pd-id = <0x3b>;
 247                 };
 248
 249                 pd_gpu: pd-gpu {
 250                         #power-domain-cells = <0x0>;
 251                         pd-id = <0x3a 0x14 0x15>;
 252                 };
 253         };
 254
 255         /* PMU1<->APU IPI mailbox controller */
 256         ipi_mailbox_pmu1: mailbox@ff990400 {
 257                 compatible = "xlnx,zynqmp-ipi-mailbox";
 258                 reg = <0x0 0xff9905c0 0x0 0x20>,
 259                       <0x0 0xff9905e0 0x0 0x20>,
 260                       <0x0 0xff990e80 0x0 0x20>,
 261                       <0x0 0xff990ea0 0x0 0x20>;
 262                 reg-names = "local_request_region", "local_response_region",
 263                             "remote_request_region", "remote_response_region";
 264                 #mbox-cells = <1>;
 265                 xlnx,ipi-ids = <0 4>;
 266                 interrupt-parent = <&gic>;
 267                 interrupts = <0 35 4>;
 268         };
 269
 270         pmu {
 271                 compatible = "arm,armv8-pmuv3";
 272                 interrupt-parent = <&gic>;
 273                 interrupts = <0 143 4>,
 274                              <0 144 4>,
 275                              <0 145 4>,
 276                              <0 146 4>;
 277         };
 278
 279         psci {
 280                 compatible = "arm,psci-0.2";
 281                 method = "smc";
 282         };
 283
 284         firmware {
 285                 zynqmp_firmware: zynqmp-firmware {
 286                         compatible = "xlnx,zynqmp-firmware";
 287                         method = "smc";
 288                 };
 289         };
 290
 291         zynqmp_power: zynqmp-power {
 292                 compatible = "xlnx,zynqmp-power";
 293                 mboxes = <&ipi_mailbox_pmu1 0>,
 294                          <&ipi_mailbox_pmu1 1>;
 295                 mbox-names = "tx", "rx";
 296         };
 297
 298         timer {
 299                 compatible = "arm,armv8-timer";
 300                 interrupt-parent = <&gic>;
 301                 interrupts = <1 13 0xf08>,
 302                              <1 14 0xf08>,
 303                              <1 11 0xf08>,
 304                              <1 10 0xf08>;
 305         };
 306
 307         edac {
 308                 compatible = "arm,cortex-a53-edac";
 309         };
 310
 311         fpga_full: fpga-full {
 312                 compatible = "fpga-region";
 313                 fpga-mgr = <&pcap>;
 314                 #address-cells = <2>;
 315                 #size-cells = <2>;
 316         };
 317
 318         nvmem_firmware {
 319                 compatible = "xlnx,zynqmp-nvmem-fw";
 320                 #address-cells = <1>;
 321                 #size-cells = <1>;
 322
 323                 soc_revision: soc_revision@0 {
 324                         reg = <0x0 0x4>;
 325                 };
 326         };
 327
 328         pcap: pcap {
 329                 compatible = "xlnx,zynqmp-pcap-fpga";
 330         };
 331
 332         rst: reset-controller {
 333                 compatible = "xlnx,zynqmp-reset";
 334                 #reset-cells = <1>;
 335         };
 336
 337         xlnx_rsa: zynqmp_rsa {
 338                 compatible = "xlnx,zynqmp-rsa";
 339         };
 340
 341         xlnx_keccak_384: sha384 {
 342                 compatible = "xlnx,zynqmp-keccak-384";
 343         };
 344
 345         amba_apu: amba_apu@0 {
 346                 compatible = "simple-bus";
 347                 #address-cells = <2>;
 348                 #size-cells = <1>;
 349                 ranges = <0 0 0 0 0xffffffff>;
 350
 351                 gic: interrupt-controller@f9010000 {
 352                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 353                         #interrupt-cells = <3>;
 354                         reg = <0x0 0xf9010000 0x10000>,
 355                               <0x0 0xf9020000 0x20000>,
 356                               <0x0 0xf9040000 0x20000>,
 357                               <0x0 0xf9060000 0x20000>;
 358                         interrupt-controller;
 359                         interrupt-parent = <&gic>;
 360                         interrupts = <1 9 0xf04>;
 361                 };
 362         };
 363
 364         amba: amba {
 365                 compatible = "simple-bus";
 366                 u-boot,dm-pre-reloc;
 367                 #address-cells = <2>;
 368                 #size-cells = <2>;
 369                 ranges;
 370
 371                 can0: can@ff060000 {
 372                         compatible = "xlnx,zynq-can-1.0";
 373                         status = "disabled";
 374                         clock-names = "can_clk", "pclk";
 375                         reg = <0x0 0xff060000 0x0 0x1000>;
 376                         interrupts = <0 23 4>;
 377                         interrupt-parent = <&gic>;
 378                         tx-fifo-depth = <0x40>;
 379                         rx-fifo-depth = <0x40>;
 380                         power-domains = <&pd_can0>;
 381                 };
 382
 383                 can1: can@ff070000 {
 384                         compatible = "xlnx,zynq-can-1.0";
 385                         status = "disabled";
 386                         clock-names = "can_clk", "pclk";
 387                         reg = <0x0 0xff070000 0x0 0x1000>;
 388                         interrupts = <0 24 4>;
 389                         interrupt-parent = <&gic>;
 390                         tx-fifo-depth = <0x40>;
 391                         rx-fifo-depth = <0x40>;
 392                         power-domains = <&pd_can1>;
 393                 };
 394
 395                 cci: cci@fd6e0000 {
 396                         compatible = "arm,cci-400";
 397                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 398                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 399                         #address-cells = <1>;
 400                         #size-cells = <1>;
 401
 402                         pmu@9000 {
 403                                 compatible = "arm,cci-400-pmu,r1";
 404                                 reg = <0x9000 0x5000>;
 405                                 interrupt-parent = <&gic>;
 406                                 interrupts = <0 123 4>,
 407                                              <0 123 4>,
 408                                              <0 123 4>,
 409                                              <0 123 4>,
 410                                              <0 123 4>;
 411                         };
 412                 };
 413
 414                 /* GDMA */
 415                 fpd_dma_chan1: dma@fd500000 {
 416                         status = "disabled";
 417                         compatible = "xlnx,zynqmp-dma-1.0";
 418                         reg = <0x0 0xfd500000 0x0 0x1000>;
 419                         interrupt-parent = <&gic>;
 420                         interrupts = <0 124 4>;
 421                         clock-names = "clk_main", "clk_apb";
 422                         xlnx,bus-width = <128>;
 423                         #stream-id-cells = <1>;
 424                         iommus = <&smmu 0x14e8>;
 425                         power-domains = <&pd_gdma>;
 426                 };
 427
 428                 fpd_dma_chan2: dma@fd510000 {
 429                         status = "disabled";
 430                         compatible = "xlnx,zynqmp-dma-1.0";
 431                         reg = <0x0 0xfd510000 0x0 0x1000>;
 432                         interrupt-parent = <&gic>;
 433                         interrupts = <0 125 4>;
 434                         clock-names = "clk_main", "clk_apb";
 435                         xlnx,bus-width = <128>;
 436                         #stream-id-cells = <1>;
 437                         iommus = <&smmu 0x14e9>;
 438                         power-domains = <&pd_gdma>;
 439                 };
 440
 441                 fpd_dma_chan3: dma@fd520000 {
 442                         status = "disabled";
 443                         compatible = "xlnx,zynqmp-dma-1.0";
 444                         reg = <0x0 0xfd520000 0x0 0x1000>;
 445                         interrupt-parent = <&gic>;
 446                         interrupts = <0 126 4>;
 447                         clock-names = "clk_main", "clk_apb";
 448                         xlnx,bus-width = <128>;
 449                         #stream-id-cells = <1>;
 450                         iommus = <&smmu 0x14ea>;
 451                         power-domains = <&pd_gdma>;
 452                 };
 453
 454                 fpd_dma_chan4: dma@fd530000 {
 455                         status = "disabled";
 456                         compatible = "xlnx,zynqmp-dma-1.0";
 457                         reg = <0x0 0xfd530000 0x0 0x1000>;
 458                         interrupt-parent = <&gic>;
 459                         interrupts = <0 127 4>;
 460                         clock-names = "clk_main", "clk_apb";
 461                         xlnx,bus-width = <128>;
 462                         #stream-id-cells = <1>;
 463                         iommus = <&smmu 0x14eb>;
 464                         power-domains = <&pd_gdma>;
 465                 };
 466
 467                 fpd_dma_chan5: dma@fd540000 {
 468                         status = "disabled";
 469                         compatible = "xlnx,zynqmp-dma-1.0";
 470                         reg = <0x0 0xfd540000 0x0 0x1000>;
 471                         interrupt-parent = <&gic>;
 472                         interrupts = <0 128 4>;
 473                         clock-names = "clk_main", "clk_apb";
 474                         xlnx,bus-width = <128>;
 475                         #stream-id-cells = <1>;
 476                         iommus = <&smmu 0x14ec>;
 477                         power-domains = <&pd_gdma>;
 478                 };
 479
 480                 fpd_dma_chan6: dma@fd550000 {
 481                         status = "disabled";
 482                         compatible = "xlnx,zynqmp-dma-1.0";
 483                         reg = <0x0 0xfd550000 0x0 0x1000>;
 484                         interrupt-parent = <&gic>;
 485                         interrupts = <0 129 4>;
 486                         clock-names = "clk_main", "clk_apb";
 487                         xlnx,bus-width = <128>;
 488                         #stream-id-cells = <1>;
 489                         iommus = <&smmu 0x14ed>;
 490                         power-domains = <&pd_gdma>;
 491                 };
 492
 493                 fpd_dma_chan7: dma@fd560000 {
 494                         status = "disabled";
 495                         compatible = "xlnx,zynqmp-dma-1.0";
 496                         reg = <0x0 0xfd560000 0x0 0x1000>;
 497                         interrupt-parent = <&gic>;
 498                         interrupts = <0 130 4>;
 499                         clock-names = "clk_main", "clk_apb";
 500                         xlnx,bus-width = <128>;
 501                         #stream-id-cells = <1>;
 502                         iommus = <&smmu 0x14ee>;
 503                         power-domains = <&pd_gdma>;
 504                 };
 505
 506                 fpd_dma_chan8: dma@fd570000 {
 507                         status = "disabled";
 508                         compatible = "xlnx,zynqmp-dma-1.0";
 509                         reg = <0x0 0xfd570000 0x0 0x1000>;
 510                         interrupt-parent = <&gic>;
 511                         interrupts = <0 131 4>;
 512                         clock-names = "clk_main", "clk_apb";
 513                         xlnx,bus-width = <128>;
 514                         #stream-id-cells = <1>;
 515                         iommus = <&smmu 0x14ef>;
 516                         power-domains = <&pd_gdma>;
 517                 };
 518
 519                 gpu: gpu@fd4b0000 {
 520                         status = "disabled";
 521                         compatible = "arm,mali-400", "arm,mali-utgard";
 522                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 523                         interrupt-parent = <&gic>;
 524                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 525                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 526                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 527                         power-domains = <&pd_gpu>;
 528                 };
 529
 530                 /* LPDDMA default allows only secured access. inorder to enable
 531                  * These dma channels, Users should ensure that these dma
 532                  * Channels are allowed for non secure access.
 533                  */
 534                 lpd_dma_chan1: dma@ffa80000 {
 535                         status = "disabled";
 536                         compatible = "xlnx,zynqmp-dma-1.0";
 537                         reg = <0x0 0xffa80000 0x0 0x1000>;
 538                         interrupt-parent = <&gic>;
 539                         interrupts = <0 77 4>;
 540                         clock-names = "clk_main", "clk_apb";
 541                         xlnx,bus-width = <64>;
 542                         #stream-id-cells = <1>;
 543                         /* iommus = <&smmu 0x868>; */
 544                         power-domains = <&pd_adma>;
 545                 };
 546
 547                 lpd_dma_chan2: dma@ffa90000 {
 548                         status = "disabled";
 549                         compatible = "xlnx,zynqmp-dma-1.0";
 550                         reg = <0x0 0xffa90000 0x0 0x1000>;
 551                         interrupt-parent = <&gic>;
 552                         interrupts = <0 78 4>;
 553                         clock-names = "clk_main", "clk_apb";
 554                         xlnx,bus-width = <64>;
 555                         #stream-id-cells = <1>;
 556                         /* iommus = <&smmu 0x869>; */
 557                         power-domains = <&pd_adma>;
 558                 };
 559
 560                 lpd_dma_chan3: dma@ffaa0000 {
 561                         status = "disabled";
 562                         compatible = "xlnx,zynqmp-dma-1.0";
 563                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 564                         interrupt-parent = <&gic>;
 565                         interrupts = <0 79 4>;
 566                         clock-names = "clk_main", "clk_apb";
 567                         xlnx,bus-width = <64>;
 568                         #stream-id-cells = <1>;
 569                         /* iommus = <&smmu 0x86a>; */
 570                         power-domains = <&pd_adma>;
 571                 };
 572
 573                 lpd_dma_chan4: dma@ffab0000 {
 574                         status = "disabled";
 575                         compatible = "xlnx,zynqmp-dma-1.0";
 576                         reg = <0x0 0xffab0000 0x0 0x1000>;
 577                         interrupt-parent = <&gic>;
 578                         interrupts = <0 80 4>;
 579                         clock-names = "clk_main", "clk_apb";
 580                         xlnx,bus-width = <64>;
 581                         #stream-id-cells = <1>;
 582                         /* iommus = <&smmu 0x86b>; */
 583                         power-domains = <&pd_adma>;
 584                 };
 585
 586                 lpd_dma_chan5: dma@ffac0000 {
 587                         status = "disabled";
 588                         compatible = "xlnx,zynqmp-dma-1.0";
 589                         reg = <0x0 0xffac0000 0x0 0x1000>;
 590                         interrupt-parent = <&gic>;
 591                         interrupts = <0 81 4>;
 592                         clock-names = "clk_main", "clk_apb";
 593                         xlnx,bus-width = <64>;
 594                         #stream-id-cells = <1>;
 595                         /* iommus = <&smmu 0x86c>; */
 596                         power-domains = <&pd_adma>;
 597                 };
 598
 599                 lpd_dma_chan6: dma@ffad0000 {
 600                         status = "disabled";
 601                         compatible = "xlnx,zynqmp-dma-1.0";
 602                         reg = <0x0 0xffad0000 0x0 0x1000>;
 603                         interrupt-parent = <&gic>;
 604                         interrupts = <0 82 4>;
 605                         clock-names = "clk_main", "clk_apb";
 606                         xlnx,bus-width = <64>;
 607                         #stream-id-cells = <1>;
 608                         /* iommus = <&smmu 0x86d>; */
 609                         power-domains = <&pd_adma>;
 610                 };
 611
 612                 lpd_dma_chan7: dma@ffae0000 {
 613                         status = "disabled";
 614                         compatible = "xlnx,zynqmp-dma-1.0";
 615                         reg = <0x0 0xffae0000 0x0 0x1000>;
 616                         interrupt-parent = <&gic>;
 617                         interrupts = <0 83 4>;
 618                         clock-names = "clk_main", "clk_apb";
 619                         xlnx,bus-width = <64>;
 620                         #stream-id-cells = <1>;
 621                         /* iommus = <&smmu 0x86e>; */
 622                         power-domains = <&pd_adma>;
 623                 };
 624
 625                 lpd_dma_chan8: dma@ffaf0000 {
 626                         status = "disabled";
 627                         compatible = "xlnx,zynqmp-dma-1.0";
 628                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 629                         interrupt-parent = <&gic>;
 630                         interrupts = <0 84 4>;
 631                         clock-names = "clk_main", "clk_apb";
 632                         xlnx,bus-width = <64>;
 633                         #stream-id-cells = <1>;
 634                         /* iommus = <&smmu 0x86f>; */
 635                         power-domains = <&pd_adma>;
 636                 };
 637
 638                 mc: memory-controller@fd070000 {
 639                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 640                         reg = <0x0 0xfd070000 0x0 0x30000>;
 641                         interrupt-parent = <&gic>;
 642                         interrupts = <0 112 4>;
 643                 };
 644
 645                 nand0: nand@ff100000 {
 646                         compatible = "arasan,nfc-v3p10";
 647                         status = "disabled";
 648                         reg = <0x0 0xff100000 0x0 0x1000>;
 649                         clock-names = "clk_sys", "clk_flash";
 650                         interrupt-parent = <&gic>;
 651                         interrupts = <0 14 4>;
 652                         #address-cells = <1>;
 653                         #size-cells = <0>;
 654                         #stream-id-cells = <1>;
 655                         iommus = <&smmu 0x872>;
 656                         power-domains = <&pd_nand>;
 657                 };
 658
 659                 gem0: ethernet@ff0b0000 {
 660                         compatible = "cdns,zynqmp-gem";
 661                         status = "disabled";
 662                         interrupt-parent = <&gic>;
 663                         interrupts = <0 57 4>, <0 57 4>;
 664                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 665                         clock-names = "pclk", "hclk", "tx_clk";
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                         #stream-id-cells = <1>;
 669                         iommus = <&smmu 0x874>;
 670                         power-domains = <&pd_eth0>;
 671                 };
 672
 673                 gem1: ethernet@ff0c0000 {
 674                         compatible = "cdns,zynqmp-gem";
 675                         status = "disabled";
 676                         interrupt-parent = <&gic>;
 677                         interrupts = <0 59 4>, <0 59 4>;
 678                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 679                         clock-names = "pclk", "hclk", "tx_clk";
 680                         #address-cells = <1>;
 681                         #size-cells = <0>;
 682                         #stream-id-cells = <1>;
 683                         iommus = <&smmu 0x875>;
 684                         power-domains = <&pd_eth1>;
 685                 };
 686
 687                 gem2: ethernet@ff0d0000 {
 688                         compatible = "cdns,zynqmp-gem";
 689                         status = "disabled";
 690                         interrupt-parent = <&gic>;
 691                         interrupts = <0 61 4>, <0 61 4>;
 692                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 693                         clock-names = "pclk", "hclk", "tx_clk";
 694                         #address-cells = <1>;
 695                         #size-cells = <0>;
 696                         #stream-id-cells = <1>;
 697                         iommus = <&smmu 0x876>;
 698                         power-domains = <&pd_eth2>;
 699                 };
 700
 701                 gem3: ethernet@ff0e0000 {
 702                         compatible = "cdns,zynqmp-gem";
 703                         status = "disabled";
 704                         interrupt-parent = <&gic>;
 705                         interrupts = <0 63 4>, <0 63 4>;
 706                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 707                         clock-names = "pclk", "hclk", "tx_clk";
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                         #stream-id-cells = <1>;
 711                         iommus = <&smmu 0x877>;
 712                         power-domains = <&pd_eth3>;
 713                 };
 714
 715                 gpio: gpio@ff0a0000 {
 716                         compatible = "xlnx,zynqmp-gpio-1.0";
 717                         status = "disabled";
 718                         #gpio-cells = <0x2>;
 719                         interrupt-parent = <&gic>;
 720                         interrupts = <0 16 4>;
 721                         interrupt-controller;
 722                         #interrupt-cells = <2>;
 723                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 724                         gpio-controller;
 725                         power-domains = <&pd_gpio>;
 726                 };
 727
 728                 i2c0: i2c@ff020000 {
 729                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 730                         status = "disabled";
 731                         interrupt-parent = <&gic>;
 732                         interrupts = <0 17 4>;
 733                         reg = <0x0 0xff020000 0x0 0x1000>;
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736                         power-domains = <&pd_i2c0>;
 737                 };
 738
 739                 i2c1: i2c@ff030000 {
 740                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 741                         status = "disabled";
 742                         interrupt-parent = <&gic>;
 743                         interrupts = <0 18 4>;
 744                         reg = <0x0 0xff030000 0x0 0x1000>;
 745                         #address-cells = <1>;
 746                         #size-cells = <0>;
 747                         power-domains = <&pd_i2c1>;
 748                 };
 749
 750                 ocm: memory-controller@ff960000 {
 751                         compatible = "xlnx,zynqmp-ocmc-1.0";
 752                         reg = <0x0 0xff960000 0x0 0x1000>;
 753                         interrupt-parent = <&gic>;
 754                         interrupts = <0 10 4>;
 755                 };
 756
 757                 perf_monitor_ocm: perf-monitor@ffa00000 {
 758                         compatible = "xlnx,axi-perf-monitor";
 759                         reg = <0x0 0xffa00000 0x0 0x10000>;
 760                         interrupts = <0 25 4>;
 761                         interrupt-parent = <&gic>;
 762                         xlnx,enable-profile = <0>;
 763                         xlnx,enable-trace = <0>;
 764                         xlnx,num-monitor-slots = <4>;
 765                         xlnx,enable-event-count = <1>;
 766                         xlnx,enable-event-log = <1>;
 767                         xlnx,have-sampled-metric-cnt = <1>;
 768                         xlnx,num-of-counters = <8>;
 769                         xlnx,metric-count-width = <32>;
 770                         xlnx,metrics-sample-count-width = <32>;
 771                         xlnx,global-count-width = <32>;
 772                         xlnx,metric-count-scale = <1>;
 773                 };
 774
 775                 pcie: pcie@fd0e0000 {
 776                         compatible = "xlnx,nwl-pcie-2.11";
 777                         status = "disabled";
 778                         #address-cells = <3>;
 779                         #size-cells = <2>;
 780                         #interrupt-cells = <1>;
 781                         msi-controller;
 782                         device_type = "pci";
 783                         interrupt-parent = <&gic>;
 784                         interrupts = <0 118 4>,
 785                                      <0 117 4>,
 786                                      <0 116 4>,
 787                                      <0 115 4>, /* MSI_1 [63...32] */
 788                                      <0 114 4>; /* MSI_0 [31...0] */
 789                         interrupt-names = "misc", "dummy", "intx",
 790                                           "msi1", "msi0";
 791                         msi-parent = <&pcie>;
 792                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 793                               <0x0 0xfd480000 0x0 0x1000>,
 794                               <0x80 0x00000000 0x0 0x1000000>;
 795                         reg-names = "breg", "pcireg", "cfg";
 796                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 797                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 798                         bus-range = <0x00 0xff>;
 799                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 800                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 801                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 802                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 803                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 804                         power-domains = <&pd_pcie>;
 805                         pcie_intc: legacy-interrupt-controller {
 806                                 interrupt-controller;
 807                                 #address-cells = <0>;
 808                                 #interrupt-cells = <1>;
 809                         };
 810                 };
 811
 812                 qspi: spi@ff0f0000 {
 813                         u-boot,dm-pre-reloc;
 814                         compatible = "xlnx,zynqmp-qspi-1.0";
 815                         status = "disabled";
 816                         clock-names = "ref_clk", "pclk";
 817                         interrupts = <0 15 4>;
 818                         interrupt-parent = <&gic>;
 819                         num-cs = <1>;
 820                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 821                               <0x0 0xc0000000 0x0 0x8000000>;
 822                         #address-cells = <1>;
 823                         #size-cells = <0>;
 824                         #stream-id-cells = <1>;
 825                         iommus = <&smmu 0x873>;
 826                         power-domains = <&pd_qspi>;
 827                 };
 828
 829                 rtc: rtc@ffa60000 {
 830                         compatible = "xlnx,zynqmp-rtc";
 831                         status = "disabled";
 832                         reg = <0x0 0xffa60000 0x0 0x100>;
 833                         interrupt-parent = <&gic>;
 834                         interrupts = <0 26 4>, <0 27 4>;
 835                         interrupt-names = "alarm", "sec";
 836                         calibration = <0x8000>;
 837                 };
 838
 839                 serdes: zynqmp_phy@fd400000 {
 840                         compatible = "xlnx,zynqmp-psgtr-v1.1";
 841                         status = "disabled";
 842                         reg = <0x0 0xfd400000 0x0 0x40000>,
 843                               <0x0 0xfd3d0000 0x0 0x1000>;
 844                         reg-names = "serdes", "siou";
 845                         nvmem-cells = <&soc_revision>;
 846                         nvmem-cell-names = "soc_revision";
 847                         resets = <&rst 16>, <&rst 59>, <&rst 60>,
 848                                  <&rst 61>, <&rst 62>, <&rst 63>,
 849                                  <&rst 64>, <&rst 3>, <&rst 29>,
 850                                  <&rst 30>, <&rst 31>, <&rst 32>;
 851                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 852                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 853                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 854                                       "gem1_rst", "gem2_rst", "gem3_rst";
 855                         lane0: lane0 {
 856                                 #phy-cells = <4>;
 857                         };
 858                         lane1: lane1 {
 859                                 #phy-cells = <4>;
 860                         };
 861                         lane2: lane2 {
 862                                 #phy-cells = <4>;
 863                         };
 864                         lane3: lane3 {
 865                                 #phy-cells = <4>;
 866                         };
 867                 };
 868
 869                 sata: ahci@fd0c0000 {
 870                         compatible = "ceva,ahci-1v84";
 871                         status = "disabled";
 872                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 873                         interrupt-parent = <&gic>;
 874                         interrupts = <0 133 4>;
 875                         power-domains = <&pd_sata>;
 876                         #stream-id-cells = <4>;
 877                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 878                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 879                         /* dma-coherent; */
 880                 };
 881
 882                 sdhci0: sdhci@ff160000 {
 883                         u-boot,dm-pre-reloc;
 884                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 885                         status = "disabled";
 886                         interrupt-parent = <&gic>;
 887                         interrupts = <0 48 4>;
 888                         reg = <0x0 0xff160000 0x0 0x1000>;
 889                         clock-names = "clk_xin", "clk_ahb";
 890                         xlnx,device_id = <0>;
 891                         #stream-id-cells = <1>;
 892                         iommus = <&smmu 0x870>;
 893                         power-domains = <&pd_sd0>;
 894                         nvmem-cells = <&soc_revision>;
 895                         nvmem-cell-names = "soc_revision";
 896                 };
 897
 898                 sdhci1: sdhci@ff170000 {
 899                         u-boot,dm-pre-reloc;
 900                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 901                         status = "disabled";
 902                         interrupt-parent = <&gic>;
 903                         interrupts = <0 49 4>;
 904                         reg = <0x0 0xff170000 0x0 0x1000>;
 905                         clock-names = "clk_xin", "clk_ahb";
 906                         xlnx,device_id = <1>;
 907                         #stream-id-cells = <1>;
 908                         iommus = <&smmu 0x871>;
 909                         power-domains = <&pd_sd1>;
 910                         nvmem-cells = <&soc_revision>;
 911                         nvmem-cell-names = "soc_revision";
 912                 };
 913
 914                 smmu: smmu@fd800000 {
 915                         compatible = "arm,mmu-500";
 916                         reg = <0x0 0xfd800000 0x0 0x20000>;
 917                         #iommu-cells = <1>;
 918                         status = "disabled";
 919                         #global-interrupts = <1>;
 920                         interrupt-parent = <&gic>;
 921                         interrupts = <0 155 4>,
 922                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 923                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 924                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 925                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 926                 };
 927
 928                 spi0: spi@ff040000 {
 929                         compatible = "cdns,spi-r1p6";
 930                         status = "disabled";
 931                         interrupt-parent = <&gic>;
 932                         interrupts = <0 19 4>;
 933                         reg = <0x0 0xff040000 0x0 0x1000>;
 934                         clock-names = "ref_clk", "pclk";
 935                         #address-cells = <1>;
 936                         #size-cells = <0>;
 937                         power-domains = <&pd_spi0>;
 938                 };
 939
 940                 spi1: spi@ff050000 {
 941                         compatible = "cdns,spi-r1p6";
 942                         status = "disabled";
 943                         interrupt-parent = <&gic>;
 944                         interrupts = <0 20 4>;
 945                         reg = <0x0 0xff050000 0x0 0x1000>;
 946                         clock-names = "ref_clk", "pclk";
 947                         #address-cells = <1>;
 948                         #size-cells = <0>;
 949                         power-domains = <&pd_spi1>;
 950                 };
 951
 952                 ttc0: timer@ff110000 {
 953                         compatible = "cdns,ttc";
 954                         status = "disabled";
 955                         interrupt-parent = <&gic>;
 956                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 957                         reg = <0x0 0xff110000 0x0 0x1000>;
 958                         timer-width = <32>;
 959                         power-domains = <&pd_ttc0>;
 960                 };
 961
 962                 ttc1: timer@ff120000 {
 963                         compatible = "cdns,ttc";
 964                         status = "disabled";
 965                         interrupt-parent = <&gic>;
 966                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 967                         reg = <0x0 0xff120000 0x0 0x1000>;
 968                         timer-width = <32>;
 969                         power-domains = <&pd_ttc1>;
 970                 };
 971
 972                 ttc2: timer@ff130000 {
 973                         compatible = "cdns,ttc";
 974                         status = "disabled";
 975                         interrupt-parent = <&gic>;
 976                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 977                         reg = <0x0 0xff130000 0x0 0x1000>;
 978                         timer-width = <32>;
 979                         power-domains = <&pd_ttc2>;
 980                 };
 981
 982                 ttc3: timer@ff140000 {
 983                         compatible = "cdns,ttc";
 984                         status = "disabled";
 985                         interrupt-parent = <&gic>;
 986                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 987                         reg = <0x0 0xff140000 0x0 0x1000>;
 988                         timer-width = <32>;
 989                         power-domains = <&pd_ttc3>;
 990                 };
 991
 992                 uart0: serial@ff000000 {
 993                         u-boot,dm-pre-reloc;
 994                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 995                         status = "disabled";
 996                         interrupt-parent = <&gic>;
 997                         interrupts = <0 21 4>;
 998                         reg = <0x0 0xff000000 0x0 0x1000>;
 999                         clock-names = "uart_clk", "pclk";
1000                         power-domains = <&pd_uart0>;
1001                 };
1002
1003                 uart1: serial@ff010000 {
1004                         u-boot,dm-pre-reloc;
1005                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
1006                         status = "disabled";
1007                         interrupt-parent = <&gic>;
1008                         interrupts = <0 22 4>;
1009                         reg = <0x0 0xff010000 0x0 0x1000>;
1010                         clock-names = "uart_clk", "pclk";
1011                         power-domains = <&pd_uart1>;
1012                 };
1013
1014                 usb0: usb0@ff9d0000 {
1015                         #address-cells = <2>;
1016                         #size-cells = <2>;
1017                         status = "disabled";
1018                         compatible = "xlnx,zynqmp-dwc3";
1019                         reg = <0x0 0xff9d0000 0x0 0x100>;
1020                         clock-names = "bus_clk", "ref_clk";
1021                         power-domains = <&pd_usb0>;
1022                         ranges;
1023                         nvmem-cells = <&soc_revision>;
1024                         nvmem-cell-names = "soc_revision";
1025
1026                         dwc3_0: dwc3@fe200000 {
1027                                 compatible = "snps,dwc3";
1028                                 status = "disabled";
1029                                 reg = <0x0 0xfe200000 0x0 0x40000>;
1030                                 interrupt-parent = <&gic>;
1031                                 interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
1032                                 #stream-id-cells = <1>;
1033                                 iommus = <&smmu 0x860>;
1034                                 snps,quirk-frame-length-adjustment = <0x20>;
1035                                 snps,refclk_fladj;
1036                                 snps,enable_guctl1_resume_quirk;
1037                                 snps,enable_guctl1_ipd_quirk;
1038                                 snps,xhci-stream-quirk;
1039                                 /* dma-coherent; */
1040                                 /* snps,enable-hibernation; */
1041                         };
1042                 };
1043
1044                 usb1: usb1@ff9e0000 {
1045                         #address-cells = <2>;
1046                         #size-cells = <2>;
1047                         status = "disabled";
1048                         compatible = "xlnx,zynqmp-dwc3";
1049                         reg = <0x0 0xff9e0000 0x0 0x100>;
1050                         clock-names = "bus_clk", "ref_clk";
1051                         power-domains = <&pd_usb1>;
1052                         ranges;
1053                         nvmem-cells = <&soc_revision>;
1054                         nvmem-cell-names = "soc_revision";
1055
1056                         dwc3_1: dwc3@fe300000 {
1057                                 compatible = "snps,dwc3";
1058                                 status = "disabled";
1059                                 reg = <0x0 0xfe300000 0x0 0x40000>;
1060                                 interrupt-parent = <&gic>;
1061                                 interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
1062                                 #stream-id-cells = <1>;
1063                                 iommus = <&smmu 0x861>;
1064                                 snps,quirk-frame-length-adjustment = <0x20>;
1065                                 snps,refclk_fladj;
1066                                 snps,enable_guctl1_resume_quirk;
1067                                 snps,enable_guctl1_ipd_quirk;
1068                                 snps,xhci-stream-quirk;
1069                                 /* dma-coherent; */
1070                         };
1071                 };
1072
1073                 watchdog0: watchdog@fd4d0000 {
1074                         compatible = "cdns,wdt-r1p2";
1075                         status = "disabled";
1076                         interrupt-parent = <&gic>;
1077                         interrupts = <0 113 1>;
1078                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
1079                         timeout-sec = <10>;
1080                 };
1081
1082                 xilinx_ams: ams@ffa50000 {
1083                         compatible = "xlnx,zynqmp-ams";
1084                         status = "disabled";
1085                         interrupt-parent = <&gic>;
1086                         interrupts = <0 56 4>;
1087                         interrupt-names = "ams-irq";
1088                         reg = <0x0 0xffa50000 0x0 0x800>;
1089                         reg-names = "ams-base";
1090                         #address-cells = <2>;
1091                         #size-cells = <2>;
1092                         #io-channel-cells = <1>;
1093                         ranges;
1094
1095                         ams_ps: ams_ps@ffa50800 {
1096                                 compatible = "xlnx,zynqmp-ams-ps";
1097                                 status = "disabled";
1098                                 reg = <0x0 0xffa50800 0x0 0x400>;
1099                         };
1100
1101                         ams_pl: ams_pl@ffa50c00 {
1102                                 compatible = "xlnx,zynqmp-ams-pl";
1103                                 status = "disabled";
1104                                 reg = <0x0 0xffa50c00 0x0 0x400>;
1105                         };
1106                 };
1107
1108                 xlnx_dpdma: dma@fd4c0000 {
1109                         compatible = "xlnx,dpdma";
1110                         status = "disabled";
1111                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1112                         interrupts = <0 122 4>;
1113                         interrupt-parent = <&gic>;
1114                         clock-names = "axi_clk";
1115                         power-domains = <&pd_dp>;
1116                         dma-channels = <6>;
1117                         #dma-cells = <1>;
1118                         dma-video0channel {
1119                                 compatible = "xlnx,video0";
1120                         };
1121                         dma-video1channel {
1122                                 compatible = "xlnx,video1";
1123                         };
1124                         dma-video2channel {
1125                                 compatible = "xlnx,video2";
1126                         };
1127                         dma-graphicschannel {
1128                                 compatible = "xlnx,graphics";
1129                         };
1130                         dma-audio0channel {
1131                                 compatible = "xlnx,audio0";
1132                         };
1133                         dma-audio1channel {
1134                                 compatible = "xlnx,audio1";
1135                         };
1136                 };
1137
1138                 zynqmp_dpsub: zynqmp-display@fd4a0000 {
1139                         compatible = "xlnx,zynqmp-dpsub-1.7";
1140                         status = "disabled";
1141                         reg = <0x0 0xfd4a0000 0x0 0x1000>,
1142                               <0x0 0xfd4aa000 0x0 0x1000>,
1143                               <0x0 0xfd4ab000 0x0 0x1000>,
1144                               <0x0 0xfd4ac000 0x0 0x1000>;
1145                         reg-names = "dp", "blend", "av_buf", "aud";
1146                         interrupts = <0 119 4>;
1147                         interrupt-parent = <&gic>;
1148
1149                         clock-names = "dp_apb_clk", "dp_aud_clk",
1150                                       "dp_vtc_pixel_clk_in";
1151
1152                         power-domains = <&pd_dp>;
1153
1154                         vid-layer {
1155                                 dma-names = "vid0", "vid1", "vid2";
1156                                 dmas = <&xlnx_dpdma 0>,
1157                                        <&xlnx_dpdma 1>,
1158                                        <&xlnx_dpdma 2>;
1159                         };
1160
1161                         gfx-layer {
1162                                 dma-names = "gfx0";
1163                                 dmas = <&xlnx_dpdma 3>;
1164                         };
1165
1166                         /* dummy node to indicate there's no child i2c device */
1167                         i2c-bus {
1168                         };
1169
1170                         zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
1171                                 compatible = "xlnx,dp-snd-codec";
1172                                 clock-names = "aud_clk";
1173                         };
1174
1175                         zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
1176                                 compatible = "xlnx,dp-snd-pcm";
1177                                 dmas = <&xlnx_dpdma 4>;
1178                                 dma-names = "tx";
1179                         };
1180
1181                         zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
1182                                 compatible = "xlnx,dp-snd-pcm";
1183                                 dmas = <&xlnx_dpdma 5>;
1184                                 dma-names = "tx";
1185                         };
1186
1187                         zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
1188                                 compatible = "xlnx,dp-snd-card";
1189                                 xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
1190                                                   <&zynqmp_dp_snd_pcm1>;
1191                                 xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
1192                         };
1193                 };
1194         };
1195 };