4 * Copyright (C) 2016 - 2017 Xilinx, Inc.
7 * This driver is developed for SDFEC16 IP. It provides a char device
8 * in sysfs and supports file operations like open(), close() and ioctl().
10 * This program is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef __XILINX_SDFEC_H__
24 #define __XILINX_SDFEC_H__
26 /* Shared LDPC Tables */
27 #define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
28 #define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x103FC)
29 #define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
30 #define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x18FFC)
31 #define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
32 #define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x27FFC)
35 XSDFEC_CODE_INVALID = 0,
41 XSDFEC_INVALID_ORDER = 0,
42 XSDFEC_MAINTAIN_ORDER,
54 enum xsdfec_axis_width {
60 enum xsdfec_axis_word_include {
61 XSDFEC_FIXED_VALUE = 0,
63 XSDFEC_PER_AXI_TRANSACTION,
64 XSDFEC_AXIS_WORDS_INCLUDE_MAX,
68 * struct xsdfec_turbo - User data for Turbo Codes
69 * @alg: Algorithm used by Turbo Codes
70 * @scale: Scale Factor
71 * Turbo Code structure to communicate parameters to XSDFEC driver
79 * struct xsdfec_ldpc_params - User data for LDPC Codes
80 * @n: Number of code word bits
81 * @k: Number of information bits
82 * @psize: Size of sub-matrix
83 * @nlayers: Number of layers in code
84 * @nqc: Quasi Cyclic Number
85 * @nmqc: Number of M-sized QC operations in parity check matrix
86 * @nm: Number of M-size vectors in N
87 * @norm_type: Normalization required or not
88 * @no_packing: Determines if multiple QC ops should be performed
89 * @special_qc: Sub-Matrix property for Circulant weight > 0
90 * @no_final_parity: Decide if final parity check needs to be performed
91 * @max_schedule: Experimental code word scheduling limit
100 * This structure describes the LDPC code that is passed to the driver
101 * by the application.
103 struct xsdfec_ldpc_params {
119 u32 sc_table[XSDFEC_LDPC_SC_TABLE_ADDR_HIGH -
120 XSDFEC_LDPC_SC_TABLE_ADDR_BASE];
121 u32 la_table[XSDFEC_LDPC_LA_TABLE_ADDR_HIGH -
122 XSDFEC_LDPC_LA_TABLE_ADDR_BASE];
123 u32 qc_table[XSDFEC_LDPC_QC_TABLE_ADDR_HIGH -
124 XSDFEC_LDPC_QC_TABLE_ADDR_BASE];
129 * struct xsdfec_status - Status of SDFEC device
130 * @fec_id: ID of SDFEC instance
131 * @state: State of the SDFEC device
132 * @activity: Describes if the SDFEC instance is Active
134 struct xsdfec_status {
136 enum xsdfec_state state;
141 * struct xsdfec_config - Configuration of SDFEC device
142 * @fec_id: ID of SDFEC instance
143 * @code: The codes being used by the SDFEC instance
144 * @order: Order of Operation
145 * @din_width: Width of the DIN AXI Stream
146 * @din_word_include: How DIN_WORDS are inputted
147 * @dout_width: Width of the DOUT AXI Stream
148 * @dout_word_include: HOW DOUT_WORDS are outputted
150 struct xsdfec_config {
152 enum xsdfec_code code;
153 enum xsdfec_order order;
154 enum xsdfec_axis_width din_width;
155 enum xsdfec_axis_word_include din_word_include;
156 enum xsdfec_axis_width dout_width;
157 enum xsdfec_axis_word_include dout_word_include;
161 * struct xsdfec_irq - Enabling or Disabling Interrupts
162 * @enable_isr: If true enables the ISR
163 * @enable_ecc_isr: If true enables the ECC ISR
173 #define XSDFEC_MAGIC 'f'
174 /* ioctl to start sdfec device */
175 #define XSDFEC_START_DEV _IO(XSDFEC_MAGIC, 0)
176 /* ioctl to stop the device */
177 #define XSDFEC_STOP_DEV _IO(XSDFEC_MAGIC, 1)
178 /* ioctl to communicate to the driver that device has been reset */
179 #define XSDFEC_RESET_REQ _IO(XSDFEC_MAGIC, 2)
180 /* ioctl that returns status of sdfec device */
181 #define XSDFEC_GET_STATUS _IOR(XSDFEC_MAGIC, 3, struct xsdfec_status *)
182 /* ioctl to enable or disable irq */
183 #define XSDFEC_SET_IRQ _IOW(XSDFEC_MAGIC, 4, struct xsdfec_irq *)
184 /* ioctl to enable turbo params for sdfec device */
185 #define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 5, struct xsdfec_turbo *)
186 /* ioctl to add an LDPC code to the sdfec ldpc codes */
187 #define XSDFEC_ADD_LDPC_CODE_PARAMS \
188 _IOW(XSDFEC_MAGIC, 6, struct xsdfec_ldpc_params *)
189 /* ioctl that returns sdfec device configuration */
190 #define XSDFEC_GET_CONFIG _IOR(XSDFEC_MAGIC, 7, struct xsdfec_config *)
191 /* ioctl that returns sdfec turbo param values */
192 #define XSDFEC_GET_TURBO _IOR(XSDFEC_MAGIC, 8, struct xsdfec_turbo *)
193 /* ioctl that returns sdfec LDPC code param values, code_id must be specified */
194 #define XSDFEC_GET_LDPC_CODE_PARAMS \
195 _IOWR(XSDFEC_MAGIC, 9, struct xsdfec_ldpc_params *)
196 /* ioctl that sets order, if order of blocks can change from input to output */
197 #define XSDFEC_SET_ORDER _IOW(XSDFEC_MAGIC, 10, unsigned long *)
199 * ioctl that sets bypass.
200 * setting a value of 0 results in normal operation.
201 * setting a value of 1 results in the sdfec performing the configured
202 * operations (same number of cycles) but output data matches the input data
204 #define XSDFEC_SET_BYPASS _IOW(XSDFEC_MAGIC, 11, unsigned long *)
205 /* ioctl that determines if sdfec is processing data */
206 #define XSDFEC_IS_ACTIVE _IOR(XSDFEC_MAGIC, 12, bool *)
208 #endif /* __XILINX_SDFEC_H__ */