drivers/media/platform/xilinx/xilinx-sdirxss.c

   1 /*
   2  * Xilinx SDI Rx Subsystem
   3  *
   4  * Copyright (C) 2017 Xilinx, Inc.
   5  *
   6  * Contacts: Vishal Sagar <vsagar@xilinx.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <dt-bindings/media/xilinx-vip.h>
  19 #include <linux/bitops.h>
  20 #include <linux/compiler.h>
  21 #include <linux/delay.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/of.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm.h>
  31 #include <linux/slab.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/spinlock_types.h>
  34 #include <linux/types.h>
  35 #include <linux/v4l2-subdev.h>
  36 #include <linux/xilinx-sdirxss.h>
  37 #include <linux/xilinx-v4l2-controls.h>
  38 #include <media/media-entity.h>
  39 #include <media/v4l2-common.h>
  40 #include <media/v4l2-ctrls.h>
  41 #include <media/v4l2-event.h>
  42 #include <media/v4l2-of.h>
  43 #include <media/v4l2-subdev.h>
  44 #include "xilinx-vip.h"
  45
  46 /*
  47  * SDI Rx register map, bitmask and offsets
  48  */
  49 #define XSDIRX_RST_CTRL_REG             0x00
  50 #define XSDIRX_MDL_CTRL_REG             0x04
  51 #define XSDIRX_GLBL_IER_REG             0x0C
  52 #define XSDIRX_ISR_REG                  0x10
  53 #define XSDIRX_IER_REG                  0x14
  54 #define XSDIRX_ST352_VALID_REG          0x18
  55 #define XSDIRX_ST352_DS1_REG            0x1C
  56 #define XSDIRX_ST352_DS3_REG            0x20
  57 #define XSDIRX_ST352_DS5_REG            0x24
  58 #define XSDIRX_ST352_DS7_REG            0x28
  59 #define XSDIRX_ST352_DS9_REG            0x2C
  60 #define XSDIRX_ST352_DS11_REG           0x30
  61 #define XSDIRX_ST352_DS13_REG           0x34
  62 #define XSDIRX_ST352_DS15_REG           0x38
  63 #define XSDIRX_VERSION_REG              0x3C
  64 #define XSDIRX_SS_CONFIG_REG            0x40
  65 #define XSDIRX_MODE_DET_STAT_REG        0x44
  66 #define XSDIRX_TS_DET_STAT_REG          0x48
  67 #define XSDIRX_EDH_STAT_REG             0x4C
  68 #define XSDIRX_EDH_ERRCNT_EN_REG        0x50
  69 #define XSDIRX_EDH_ERRCNT_REG           0x54
  70 #define XSDIRX_CRC_ERRCNT_REG           0x58
  71 #define XSDIRX_VID_LOCK_WINDOW_REG      0x5C
  72 #define XSDIRX_SB_RX_STS_REG            0x60
  73
  74 #define XSDIRX_RST_CTRL_SS_EN_MASK                      BIT(0)
  75 #define XSDIRX_RST_CTRL_SRST_MASK                       BIT(1)
  76 #define XSDIRX_RST_CTRL_RST_CRC_ERRCNT_MASK             BIT(2)
  77 #define XSDIRX_RST_CTRL_RST_EDH_ERRCNT_MASK             BIT(3)
  78 #define XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK           BIT(8)
  79 #define XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK        BIT(9)
  80
  81 #define XSDIRX_MDL_CTRL_FRM_EN_MASK             BIT(4)
  82 #define XSDIRX_MDL_CTRL_MODE_DET_EN_MASK        BIT(5)
  83 #define XSDIRX_MDL_CTRL_MODE_HD_EN_MASK         BIT(8)
  84 #define XSDIRX_MDL_CTRL_MODE_SD_EN_MASK         BIT(9)
  85 #define XSDIRX_MDL_CTRL_MODE_3G_EN_MASK         BIT(10)
  86 #define XSDIRX_MDL_CTRL_MODE_6G_EN_MASK         BIT(11)
  87 #define XSDIRX_MDL_CTRL_MODE_12GI_EN_MASK       BIT(12)
  88 #define XSDIRX_MDL_CTRL_MODE_12GF_EN_MASK       BIT(13)
  89 #define XSDIRX_MDL_CTRL_MODE_AUTO_DET_MASK      GENMASK(13, 8)
  90
  91 #define XSDIRX_MDL_CTRL_FORCED_MODE_OFFSET      16
  92 #define XSDIRX_MDL_CTRL_FORCED_MODE_MASK        GENMASK(18, 16)
  93
  94 #define XSDIRX_GLBL_INTR_EN_MASK        BIT(0)
  95
  96 #define XSDIRX_INTR_VIDLOCK_MASK        BIT(0)
  97 #define XSDIRX_INTR_VIDUNLOCK_MASK      BIT(1)
  98 #define XSDIRX_INTR_OVERFLOW_MASK       BIT(9)
  99 #define XSDIRX_INTR_UNDERFLOW_MASK      BIT(10)
 100
 101 #define XSDIRX_INTR_ALL_MASK    (XSDIRX_INTR_VIDLOCK_MASK |\
 102                                 XSDIRX_INTR_VIDUNLOCK_MASK |\
 103                                 XSDIRX_INTR_OVERFLOW_MASK |\
 104                                 XSDIRX_INTR_UNDERFLOW_MASK)
 105
 106 #define XSDIRX_ST352_VALID_DS1_MASK     BIT(0)
 107 #define XSDIRX_ST352_VALID_DS3_MASK     BIT(1)
 108 #define XSDIRX_ST352_VALID_DS5_MASK     BIT(2)
 109 #define XSDIRX_ST352_VALID_DS7_MASK     BIT(3)
 110 #define XSDIRX_ST352_VALID_DS9_MASK     BIT(4)
 111 #define XSDIRX_ST352_VALID_DS11_MASK    BIT(5)
 112 #define XSDIRX_ST352_VALID_DS13_MASK    BIT(6)
 113 #define XSDIRX_ST352_VALID_DS15_MASK    BIT(7)
 114
 115 #define XSDIRX_MODE_DET_STAT_RX_MODE_MASK       GENMASK(2, 0)
 116 #define XSDIRX_MODE_DET_STAT_MODE_LOCK_MASK     BIT(3)
 117 #define XSDIRX_MODE_DET_STAT_ACT_STREAM_MASK    GENMASK(6, 4)
 118 #define XSDIRX_MODE_DET_STAT_LVLB_3G_MASK       BIT(7)
 119
 120 #define XSDIRX_ACTIVE_STREAMS_1         0x0
 121 #define XSDIRX_ACTIVE_STREAMS_2         0x1
 122 #define XSDIRX_ACTIVE_STREAMS_4         0x2
 123 #define XSDIRX_ACTIVE_STREAMS_8         0x3
 124 #define XSDIRX_ACTIVE_STREAMS_16        0x4
 125
 126 #define XSDIRX_TS_DET_STAT_LOCKED_MASK          BIT(0)
 127 #define XSDIRX_TS_DET_STAT_SCAN_MASK            BIT(1)
 128 #define XSDIRX_TS_DET_STAT_SCAN_OFFSET          (1)
 129 #define XSDIRX_TS_DET_STAT_FAMILY_MASK          GENMASK(7, 4)
 130 #define XSDIRX_TS_DET_STAT_FAMILY_OFFSET        (4)
 131 #define XSDIRX_TS_DET_STAT_RATE_MASK            GENMASK(11, 8)
 132 #define XSDIRX_TS_DET_STAT_RATE_OFFSET          (8)
 133
 134 #define XSDIRX_TS_DET_STAT_RATE_NONE            0x0
 135 #define XSDIRX_TS_DET_STAT_RATE_23_98HZ         0x2
 136 #define XSDIRX_TS_DET_STAT_RATE_24HZ            0x3
 137 #define XSDIRX_TS_DET_STAT_RATE_47_95HZ         0x4
 138 #define XSDIRX_TS_DET_STAT_RATE_25HZ            0x5
 139 #define XSDIRX_TS_DET_STAT_RATE_29_97HZ         0x6
 140 #define XSDIRX_TS_DET_STAT_RATE_30HZ            0x7
 141 #define XSDIRX_TS_DET_STAT_RATE_48HZ            0x8
 142 #define XSDIRX_TS_DET_STAT_RATE_50HZ            0x9
 143 #define XSDIRX_TS_DET_STAT_RATE_59_94HZ         0xA
 144 #define XSDIRX_TS_DET_STAT_RATE_60HZ            0xB
 145
 146 #define XSDIRX_EDH_STAT_EDH_AP_MASK     BIT(0)
 147 #define XSDIRX_EDH_STAT_EDH_FF_MASK     BIT(1)
 148 #define XSDIRX_EDH_STAT_EDH_ANC_MASK    BIT(2)
 149 #define XSDIRX_EDH_STAT_AP_FLAG_MASK    GENMASK(8, 4)
 150 #define XSDIRX_EDH_STAT_FF_FLAG_MASK    GENMASK(13, 9)
 151 #define XSDIRX_EDH_STAT_ANC_FLAG_MASK   GENMASK(18, 14)
 152 #define XSDIRX_EDH_STAT_PKT_FLAG_MASK   GENMASK(22, 19)
 153
 154 #define XSDIRX_EDH_ERRCNT_COUNT_MASK    GENMASK(15, 0)
 155
 156 #define XSDIRX_CRC_ERRCNT_COUNT_MASK    GENMASK(31, 16)
 157 #define XSDIRX_CRC_ERRCNT_DS_CRC_MASK   GENMASK(15, 0)
 158
 159 #define XSDIRX_VERSION_REV_MASK         GENMASK(7, 0)
 160 #define XSDIRX_VERSION_PATCHID_MASK     GENMASK(11, 8)
 161 #define XSDIRX_VERSION_VER_REV_MASK     GENMASK(15, 12)
 162 #define XSDIRX_VERSION_VER_MIN_MASK     GENMASK(23, 16)
 163 #define XSDIRX_VERSION_VER_MAJ_MASK     GENMASK(31, 24)
 164
 165 #define XSDIRX_SS_CONFIG_EDH_INCLUDED_MASK              BIT(1)
 166
 167 #define XSDIRX_STAT_SB_RX_TDATA_CHANGE_DONE_MASK        BIT(0)
 168 #define XSDIRX_STAT_SB_RX_TDATA_CHANGE_FAIL_MASK        BIT(1)
 169 #define XSDIRX_STAT_SB_RX_TDATA_GT_RESETDONE_MASK       BIT(2)
 170 #define XSDIRX_STAT_SB_RX_TDATA_GT_BITRATE_MASK         BIT(3)
 171
 172 #define XSDIRX_VID_LOCK_WINDOW_VAL_MASK                 GENMASK(15, 0)
 173
 174 /* Number of media pads */
 175 #define XSDIRX_MEDIA_PADS       (1)
 176
 177 #define XSDIRX_DEFAULT_WIDTH    (1920)
 178 #define XSDIRX_DEFAULT_HEIGHT   (1080)
 179
 180 #define XSDIRX_MAX_STR_LENGTH   16
 181
 182 #define XSDIRXSS_SDI_STD_3G             0
 183 #define XSDIRXSS_SDI_STD_6G             1
 184 #define XSDIRXSS_SDI_STD_12G_8DS        2
 185
 186 #define XSDIRX_DEFAULT_VIDEO_LOCK_WINDOW        0x3000
 187
 188 #define XSDIRX_MODE_HD_MASK     0x0
 189 #define XSDIRX_MODE_SD_MASK     0x1
 190 #define XSDIRX_MODE_3G_MASK     0x2
 191 #define XSDIRX_MODE_6G_MASK     0x4
 192 #define XSDIRX_MODE_12GI_MASK   0x5
 193 #define XSDIRX_MODE_12GF_MASK   0x6
 194
 195 /*
 196  * Maximum number of events per file handle.
 197  */
 198 #define XSDIRX_MAX_EVENTS       (128)
 199
 200 /* ST352 related macros */
 201 #define XST352_PAYLOAD_BYTE_MASK        0xFF
 202 #define XST352_PAYLOAD_BYTE1_SHIFT      0
 203 #define XST352_PAYLOAD_BYTE2_SHIFT      8
 204 #define XST352_PAYLOAD_BYTE3_SHIFT      16
 205 #define XST352_PAYLOAD_BYTE4_SHIFT      24
 206
 207 #define XST352_BYTE1_ST292_1x720L_1_5G          0x84
 208 #define XST352_BYTE1_ST292_1x1080L_1_5G         0x85
 209 #define XST352_BYTE1_ST425_2008_750L_3GB        0x88
 210 #define XST352_BYTE1_ST425_2008_1125L_3GA       0x89
 211 #define XST352_BYTE1_ST372_DL_3GB               0x8A
 212 #define XST352_BYTE1_ST372_2x720L_3GB           0x8B
 213 #define XST352_BYTE1_ST372_2x1080L_3GB          0x8C
 214 #define XST352_BYTE1_ST2081_10_2160L_6G         0xC0
 215 #define XST352_BYTE1_ST2081_10_DL_2160L_6G      0xC2
 216 #define XST352_BYTE1_ST2082_10_2160L_12G        0xCE
 217
 218 #define XST352_BYTE2_TS_TYPE_MASK               BIT(15)
 219 #define XST352_BYTE2_TS_TYPE_OFFSET             15
 220 #define XST352_BYTE2_PIC_TYPE_MASK              BIT(14)
 221 #define XST352_BYTE2_PIC_TYPE_OFFSET            14
 222 #define XST352_BYTE2_TS_PIC_TYPE_INTERLACED     0
 223 #define XST352_BYTE2_TS_PIC_TYPE_PROGRESSIVE    1
 224
 225 #define XST352_BYTE2_FPS_MASK                   0xF
 226 #define XST352_BYTE2_FPS_SHIFT                  8
 227 #define XST352_BYTE2_FPS_24F                    0x2
 228 #define XST352_BYTE2_FPS_24                     0x3
 229 #define XST352_BYTE2_FPS_48F                    0x4
 230 #define XST352_BYTE2_FPS_25                     0x5
 231 #define XST352_BYTE2_FPS_30F                    0x6
 232 #define XST352_BYTE2_FPS_30                     0x7
 233 #define XST352_BYTE2_FPS_48                     0x8
 234 #define XST352_BYTE2_FPS_50                     0x9
 235 #define XST352_BYTE2_FPS_60F                    0xA
 236 #define XST352_BYTE2_FPS_60                     0xB
 237 /* Table 4 ST 2081-10:2015 */
 238 #define XST352_BYTE2_FPS_96                     0xC
 239 #define XST352_BYTE2_FPS_100                    0xD
 240 #define XST352_BYTE2_FPS_120                    0xE
 241 #define XST352_BYTE2_FPS_120F                   0xF
 242
 243 #define XST352_BYTE3_ACT_LUMA_COUNT_MASK        BIT(22)
 244 #define XST352_BYTE3_ACT_LUMA_COUNT_OFFSET      22
 245
 246 /**
 247  * enum sdi_family_enc - SDI Transport Video Format Detected with Active Pixels
 248  * @XSDIRX_SMPTE_ST_274: SMPTE ST 274 detected with AP 1920x1080
 249  * @XSDIRX_SMPTE_ST_296: SMPTE ST 296 detected with AP 1280x720
 250  * @XSDIRX_SMPTE_ST_2048_2: SMPTE ST 2048-2 detected with AP 2048x1080
 251  * @XSDIRX_SMPTE_ST_295: SMPTE ST 295 detected with AP 1920x1080
 252  * @XSDIRX_NTSC: NTSC encoding detected with AP 720x480
 253  * @XSDIRX_PAL: PAL encoding detected with AP 720x576
 254  * @XSDIRX_TS_UNKNOWN: Unknown SMPTE Transport family type
 255  */
 256 enum sdi_family_enc {
 257         XSDIRX_SMPTE_ST_274     = 0,
 258         XSDIRX_SMPTE_ST_296     = 1,
 259         XSDIRX_SMPTE_ST_2048_2  = 2,
 260         XSDIRX_SMPTE_ST_295     = 3,
 261         XSDIRX_NTSC             = 8,
 262         XSDIRX_PAL              = 9,
 263         XSDIRX_TS_UNKNOWN       = 15
 264 };
 265
 266 /**
 267  * struct xsdirxss_core - Core configuration SDI Rx Subsystem device structure
 268  * @dev: Platform structure
 269  * @iomem: Base address of subsystem
 270  * @irq: requested irq number
 271  * @include_edh: EDH processor presence
 272  * @mode: 3G/6G/12G mode
 273  */
 274 struct xsdirxss_core {
 275         struct device *dev;
 276         void __iomem *iomem;
 277         int irq;
 278         bool include_edh;
 279         int mode;
 280 };
 281
 282 /**
 283  * struct xsdirxss_state - SDI Rx Subsystem device structure
 284  * @core: Core structure for MIPI SDI Rx Subsystem
 285  * @subdev: The v4l2 subdev structure
 286  * @ctrl_handler: control handler
 287  * @event: Holds the video unlock event
 288  * @formats: Active V4L2 formats on each pad
 289  * @default_format: default V4L2 media bus format
 290  * @frame_interval: Captures the frame rate
 291  * @vip_format: format information corresponding to the active format
 292  * @pads: media pads
 293  * @streaming: Flag for storing streaming state
 294  * @vidlocked: Flag indicating SDI Rx has locked onto video stream
 295  * @ts_is_interlaced: Flag indicating Transport Stream is interlaced.
 296  *
 297  * This structure contains the device driver related parameters
 298  */
 299 struct xsdirxss_state {
 300         struct xsdirxss_core core;
 301         struct v4l2_subdev subdev;
 302         struct v4l2_ctrl_handler ctrl_handler;
 303         struct v4l2_event event;
 304         struct v4l2_mbus_framefmt formats[XSDIRX_MEDIA_PADS];
 305         struct v4l2_mbus_framefmt default_format;
 306         struct v4l2_fract frame_interval;
 307         const struct xvip_video_format *vip_format;
 308         struct media_pad pads[XSDIRX_MEDIA_PADS];
 309         bool streaming;
 310         bool vidlocked;
 311         bool ts_is_interlaced;
 312 };
 313
 314 static inline struct xsdirxss_state *
 315 to_xsdirxssstate(struct v4l2_subdev *subdev)
 316 {
 317         return container_of(subdev, struct xsdirxss_state, subdev);
 318 }
 319
 320 /*
 321  * Register related operations
 322  */
 323 static inline u32 xsdirxss_read(struct xsdirxss_core *xsdirxss, u32 addr)
 324 {
 325         return ioread32(xsdirxss->iomem + addr);
 326 }
 327
 328 static inline void xsdirxss_write(struct xsdirxss_core *xsdirxss, u32 addr,
 329                                   u32 value)
 330 {
 331         iowrite32(value, xsdirxss->iomem + addr);
 332 }
 333
 334 static inline void xsdirxss_clr(struct xsdirxss_core *xsdirxss, u32 addr,
 335                                 u32 clr)
 336 {
 337         xsdirxss_write(xsdirxss, addr, xsdirxss_read(xsdirxss, addr) & ~clr);
 338 }
 339
 340 static inline void xsdirxss_set(struct xsdirxss_core *xsdirxss, u32 addr,
 341                                 u32 set)
 342 {
 343         xsdirxss_write(xsdirxss, addr, xsdirxss_read(xsdirxss, addr) | set);
 344 }
 345
 346 static void xsdirx_core_disable(struct xsdirxss_core *core)
 347 {
 348         xsdirxss_clr(core, XSDIRX_RST_CTRL_REG, XSDIRX_RST_CTRL_SS_EN_MASK);
 349 }
 350
 351 static void xsdirx_core_enable(struct xsdirxss_core *core)
 352 {
 353         xsdirxss_set(core, XSDIRX_RST_CTRL_REG, XSDIRX_RST_CTRL_SS_EN_MASK);
 354 }
 355
 356 static int xsdirx_set_modedetect(struct xsdirxss_core *core, u16 mask)
 357 {
 358         u32 i, val;
 359
 360         mask &= XSDIRX_DETECT_ALL_MODES;
 361         if (!mask) {
 362                 dev_err(core->dev, "Invalid bit mask = 0x%08x\n", mask);
 363                 return -EINVAL;
 364         }
 365
 366         dev_dbg(core->dev, "mask = 0x%x\n", mask);
 367
 368         val = xsdirxss_read(core, XSDIRX_MDL_CTRL_REG);
 369         val &= ~(XSDIRX_MDL_CTRL_MODE_DET_EN_MASK);
 370         val &= ~(XSDIRX_MDL_CTRL_MODE_AUTO_DET_MASK);
 371         val &= ~(XSDIRX_MDL_CTRL_FORCED_MODE_MASK);
 372
 373         if (hweight16(mask) > 1) {
 374                 /* Multi mode detection as more than 1 bit set in mask */
 375                 dev_dbg(core->dev, "Detect multiple modes\n");
 376                 for (i = 0; i < XSDIRX_MODE_NUM_SUPPORTED; i++) {
 377                         switch (mask & (1 << i)) {
 378                         case BIT(XSDIRX_MODE_SD_OFFSET):
 379                                 val |= XSDIRX_MDL_CTRL_MODE_SD_EN_MASK;
 380                                 break;
 381                         case BIT(XSDIRX_MODE_HD_OFFSET):
 382                                 val |= XSDIRX_MDL_CTRL_MODE_HD_EN_MASK;
 383                                 break;
 384                         case BIT(XSDIRX_MODE_3G_OFFSET):
 385                                 val |= XSDIRX_MDL_CTRL_MODE_3G_EN_MASK;
 386                                 break;
 387                         case BIT(XSDIRX_MODE_6G_OFFSET):
 388                                 val |= XSDIRX_MDL_CTRL_MODE_6G_EN_MASK;
 389                                 break;
 390                         case BIT(XSDIRX_MODE_12GI_OFFSET):
 391                                 val |= XSDIRX_MDL_CTRL_MODE_12GI_EN_MASK;
 392                                 break;
 393                         case BIT(XSDIRX_MODE_12GF_OFFSET):
 394                                 val |= XSDIRX_MDL_CTRL_MODE_12GF_EN_MASK;
 395                                 break;
 396                         }
 397                 }
 398                 val |= XSDIRX_MDL_CTRL_MODE_DET_EN_MASK;
 399         } else {
 400                 /* Fixed Mode */
 401                 u32 forced_mode_mask = 0;
 402
 403                 dev_dbg(core->dev, "Detect fixed mode\n");
 404
 405                 /* Find offset of first bit set */
 406                 switch (__ffs(mask)) {
 407                 case XSDIRX_MODE_SD_OFFSET:
 408                         forced_mode_mask = XSDIRX_MODE_SD_MASK;
 409                         break;
 410                 case XSDIRX_MODE_HD_OFFSET:
 411                         forced_mode_mask = XSDIRX_MODE_HD_MASK;
 412                         break;
 413                 case XSDIRX_MODE_3G_OFFSET:
 414                         forced_mode_mask = XSDIRX_MODE_3G_MASK;
 415                         break;
 416                 case XSDIRX_MODE_6G_OFFSET:
 417                         forced_mode_mask = XSDIRX_MODE_6G_MASK;
 418                         break;
 419                 case XSDIRX_MODE_12GI_OFFSET:
 420                         forced_mode_mask = XSDIRX_MODE_12GI_MASK;
 421                         break;
 422                 case XSDIRX_MODE_12GF_OFFSET:
 423                         forced_mode_mask = XSDIRX_MODE_12GF_MASK;
 424                         break;
 425                 }
 426                 dev_dbg(core->dev, "Forced Mode Mask : 0x%x\n",
 427                         forced_mode_mask);
 428                 val |= forced_mode_mask << XSDIRX_MDL_CTRL_FORCED_MODE_OFFSET;
 429         }
 430
 431         dev_dbg(core->dev, "Modes to be detected : sdi ctrl reg = 0x%08x\n",
 432                 val);
 433         xsdirxss_write(core, XSDIRX_MDL_CTRL_REG, val);
 434
 435         return 0;
 436 }
 437
 438 static void xsdirx_framer(struct xsdirxss_core *core, bool flag)
 439 {
 440         if (flag)
 441                 xsdirxss_set(core, XSDIRX_MDL_CTRL_REG,
 442                              XSDIRX_MDL_CTRL_FRM_EN_MASK);
 443         else
 444                 xsdirxss_clr(core, XSDIRX_MDL_CTRL_REG,
 445                              XSDIRX_MDL_CTRL_FRM_EN_MASK);
 446 }
 447
 448 static void xsdirx_setedherrcnttrigger(struct xsdirxss_core *core, u32 enable)
 449 {
 450         u32 val = xsdirxss_read(core, XSDIRX_EDH_ERRCNT_EN_REG);
 451
 452         val = enable & XSDIRX_EDH_ALLERR_MASK;
 453
 454         xsdirxss_write(core, XSDIRX_EDH_ERRCNT_EN_REG, val);
 455 }
 456
 457 static void xsdirx_setvidlockwindow(struct xsdirxss_core *core, u32 val)
 458 {
 459         /*
 460          * The video lock window is the amount of time for which the
 461          * the mode and transport stream should be locked to get the
 462          * video lock interrupt.
 463          */
 464         xsdirxss_write(core, XSDIRX_VID_LOCK_WINDOW_REG,
 465                        val & XSDIRX_VID_LOCK_WINDOW_VAL_MASK);
 466 }
 467
 468 static void xsdirx_disableintr(struct xsdirxss_core *core, u32 mask)
 469 {
 470         xsdirxss_clr(core, XSDIRX_IER_REG, mask);
 471 }
 472
 473 static void xsdirx_enableintr(struct xsdirxss_core *core, u32 mask)
 474 {
 475         xsdirxss_set(core, XSDIRX_IER_REG, mask);
 476 }
 477
 478 static void xsdirx_globalintr(struct xsdirxss_core *core, bool flag)
 479 {
 480         if (flag)
 481                 xsdirxss_set(core, XSDIRX_GLBL_IER_REG,
 482                              XSDIRX_GLBL_INTR_EN_MASK);
 483         else
 484                 xsdirxss_clr(core, XSDIRX_GLBL_IER_REG,
 485                              XSDIRX_GLBL_INTR_EN_MASK);
 486 }
 487
 488 static void xsdirx_clearintr(struct xsdirxss_core *core, u32 mask)
 489 {
 490         xsdirxss_set(core, XSDIRX_ISR_REG, mask);
 491 }
 492
 493 static void xsdirx_vid_bridge_control(struct xsdirxss_core *core, bool enable)
 494 {
 495         if (enable)
 496                 xsdirxss_set(core, XSDIRX_RST_CTRL_REG,
 497                              XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK);
 498         else
 499                 xsdirxss_clr(core, XSDIRX_RST_CTRL_REG,
 500                              XSDIRX_RST_CTRL_SDIRX_BRIDGE_ENB_MASK);
 501 }
 502
 503 static void xsdirx_axis4_bridge_control(struct xsdirxss_core *core, bool enable)
 504 {
 505         if (enable)
 506                 xsdirxss_set(core, XSDIRX_RST_CTRL_REG,
 507                              XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK);
 508         else
 509                 xsdirxss_clr(core, XSDIRX_RST_CTRL_REG,
 510                              XSDIRX_RST_CTRL_VIDIN_AXI4S_MOD_ENB_MASK);
 511 }
 512
 513 static void xsdirx_streamflow_control(struct xsdirxss_core *core, bool enable)
 514 {
 515         /* The sdi to native bridge is followed by native to axis4 bridge */
 516         if (enable) {
 517                 xsdirx_axis4_bridge_control(core, enable);
 518                 xsdirx_vid_bridge_control(core, enable);
 519         } else {
 520                 xsdirx_vid_bridge_control(core, enable);
 521                 xsdirx_axis4_bridge_control(core, enable);
 522         }
 523 }
 524
 525 static void xsdirx_streamdowncb(struct xsdirxss_core *core)
 526 {
 527         xsdirx_streamflow_control(core, false);
 528 }
 529
 530 static void xsdirxss_get_framerate(struct v4l2_fract *frame_interval,
 531                                    u32 framerate)
 532 {
 533         switch (framerate) {
 534         case XSDIRX_TS_DET_STAT_RATE_23_98HZ:
 535                 frame_interval->numerator = 1001;
 536                 frame_interval->denominator = 24000;
 537                 break;
 538         case XSDIRX_TS_DET_STAT_RATE_24HZ:
 539                 frame_interval->numerator = 1000;
 540                 frame_interval->denominator = 24000;
 541                 break;
 542         case XSDIRX_TS_DET_STAT_RATE_25HZ:
 543                 frame_interval->numerator = 1000;
 544                 frame_interval->denominator = 25000;
 545                 break;
 546         case XSDIRX_TS_DET_STAT_RATE_29_97HZ:
 547                 frame_interval->numerator = 1001;
 548                 frame_interval->denominator = 30000;
 549                 break;
 550         case XSDIRX_TS_DET_STAT_RATE_30HZ:
 551                 frame_interval->numerator = 1000;
 552                 frame_interval->denominator = 30000;
 553                 break;
 554         case XSDIRX_TS_DET_STAT_RATE_47_95HZ:
 555                 frame_interval->numerator = 1001;
 556                 frame_interval->denominator = 48000;
 557                 break;
 558         case XSDIRX_TS_DET_STAT_RATE_48HZ:
 559                 frame_interval->numerator = 1000;
 560                 frame_interval->denominator = 48000;
 561                 break;
 562         case XSDIRX_TS_DET_STAT_RATE_50HZ:
 563                 frame_interval->numerator = 1000;
 564                 frame_interval->denominator = 50000;
 565                 break;
 566         case XSDIRX_TS_DET_STAT_RATE_59_94HZ:
 567                 frame_interval->numerator = 1001;
 568                 frame_interval->denominator = 60000;
 569                 break;
 570         case XSDIRX_TS_DET_STAT_RATE_60HZ:
 571                 frame_interval->numerator = 1000;
 572                 frame_interval->denominator = 60000;
 573                 break;
 574         default:
 575                 frame_interval->numerator = 1;
 576                 frame_interval->denominator = 1;
 577         }
 578 }
 579
 580 /**
 581  * xsdirx_get_stream_properties - Get SDI Rx stream properties
 582  * @state: pointer to driver state
 583  *
 584  * This function decodes the stream's ST352 payload (if available) to get
 585  * stream properties like width, height, picture type (interlaced/progressive),
 586  * etc.
 587  *
 588  * Return: 0 for success else errors
 589  */
 590 static int xsdirx_get_stream_properties(struct xsdirxss_state *state)
 591 {
 592         struct xsdirxss_core *core = &state->core;
 593         u32 mode, payload = 0, val, family, valid, tscan;
 594         u8 byte1 = 0, active_luma = 0, pic_type = 0, framerate = 0;
 595         struct v4l2_mbus_framefmt *format = &state->formats[0];
 596
 597         mode = xsdirxss_read(core, XSDIRX_MODE_DET_STAT_REG);
 598         mode &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK;
 599
 600         valid = xsdirxss_read(core, XSDIRX_ST352_VALID_REG);
 601
 602         if ((mode >= XSDIRX_MODE_3G_MASK) && !valid) {
 603                 dev_err(core->dev, "No valid ST352 payload present even for 3G mode and above\n");
 604                 return -EINVAL;
 605         }
 606
 607         val = xsdirxss_read(core, XSDIRX_TS_DET_STAT_REG);
 608         if (valid & XSDIRX_ST352_VALID_DS1_MASK) {
 609                 payload = xsdirxss_read(core, XSDIRX_ST352_DS1_REG);
 610                 byte1 = (payload >> XST352_PAYLOAD_BYTE1_SHIFT) &
 611                                 XST352_PAYLOAD_BYTE_MASK;
 612                 active_luma = (payload & XST352_BYTE3_ACT_LUMA_COUNT_MASK) >>
 613                                 XST352_BYTE3_ACT_LUMA_COUNT_OFFSET;
 614                 pic_type = (payload & XST352_BYTE2_PIC_TYPE_MASK) >>
 615                                 XST352_BYTE2_PIC_TYPE_OFFSET;
 616                 framerate = (payload >> XST352_BYTE2_FPS_SHIFT) &
 617                                 XST352_BYTE2_FPS_MASK;
 618                 tscan = (payload & XST352_BYTE2_TS_TYPE_MASK) >>
 619                                 XST352_BYTE2_TS_TYPE_OFFSET;
 620         } else {
 621                 dev_dbg(core->dev, "No ST352 payload available : Mode = %d\n",
 622                         mode);
 623                 framerate = (val & XSDIRX_TS_DET_STAT_RATE_MASK) >>
 624                                 XSDIRX_TS_DET_STAT_RATE_OFFSET;
 625                 tscan = (val & XSDIRX_TS_DET_STAT_SCAN_MASK) >>
 626                                 XSDIRX_TS_DET_STAT_SCAN_OFFSET;
 627         }
 628
 629         family = (val & XSDIRX_TS_DET_STAT_FAMILY_MASK) >>
 630                   XSDIRX_TS_DET_STAT_FAMILY_OFFSET;
 631         state->ts_is_interlaced = tscan ? false : true;
 632
 633         dev_dbg(core->dev, "ts_is_interlaced = %d, family = %d\n",
 634                 state->ts_is_interlaced, family);
 635
 636         switch (mode) {
 637         case XSDIRX_MODE_HD_MASK:
 638                 if (!valid) {
 639                         /* No payload obtained */
 640                         dev_dbg(core->dev, "frame rate : %d, tscan = %d\n",
 641                                 framerate, tscan);
 642                         /*
 643                          * NOTE : A progressive segmented frame pSF will be
 644                          * reported incorrectly as Interlaced as we rely on IP's
 645                          * transport scan locked bit.
 646                          */
 647                         dev_warn(core->dev, "pSF will be incorrectly reported as Interlaced\n");
 648
 649                         switch (framerate) {
 650                         case XSDIRX_TS_DET_STAT_RATE_23_98HZ:
 651                         case XSDIRX_TS_DET_STAT_RATE_24HZ:
 652                         case XSDIRX_TS_DET_STAT_RATE_25HZ:
 653                         case XSDIRX_TS_DET_STAT_RATE_29_97HZ:
 654                         case XSDIRX_TS_DET_STAT_RATE_30HZ:
 655                                 if (family == XSDIRX_SMPTE_ST_296) {
 656                                         format->width = 1280;
 657                                         format->height = 720;
 658                                         format->field = V4L2_FIELD_NONE;
 659                                 } else if (family == XSDIRX_SMPTE_ST_2048_2) {
 660                                         format->width = 2048;
 661                                         format->height = 1080;
 662                                         if (tscan)
 663                                                 format->field = V4L2_FIELD_NONE;
 664                                         else
 665                                                 format->field =
 666                                                         V4L2_FIELD_INTERLACED;
 667                                 } else {
 668                                         format->width = 1920;
 669                                         format->height = 1080;
 670                                         if (tscan)
 671                                                 format->field = V4L2_FIELD_NONE;
 672                                         else
 673                                                 format->field =
 674                                                         V4L2_FIELD_INTERLACED;
 675                                 }
 676                                 break;
 677                         case XSDIRX_TS_DET_STAT_RATE_50HZ:
 678                         case XSDIRX_TS_DET_STAT_RATE_59_94HZ:
 679                         case XSDIRX_TS_DET_STAT_RATE_60HZ:
 680                                 if (family == XSDIRX_SMPTE_ST_274) {
 681                                         format->width = 1920;
 682                                         format->height = 1080;
 683                                 } else {
 684                                         format->width = 1280;
 685                                         format->height = 720;
 686                                 }
 687                                 format->field = V4L2_FIELD_NONE;
 688                                 break;
 689                         default:
 690                                 format->width = 1920;
 691                                 format->height = 1080;
 692                                 format->field = V4L2_FIELD_NONE;
 693                         }
 694                 } else {
 695                         dev_dbg(core->dev, "Got the payload\n");
 696                         switch (byte1) {
 697                         case XST352_BYTE1_ST292_1x720L_1_5G:
 698                                 /* SMPTE ST 292-1 for 720 line payloads */
 699                                 format->width = 1280;
 700                                 format->height = 720;
 701                                 break;
 702                         case XST352_BYTE1_ST292_1x1080L_1_5G:
 703                                 /* SMPTE ST 292-1 for 1080 line payloads */
 704                                 format->height = 1080;
 705                                 if (active_luma)
 706                                         format->width = 2048;
 707                                 else
 708                                         format->width = 1920;
 709                                 break;
 710                         default:
 711                                 dev_dbg(core->dev, "Unknown HD Mode SMPTE standard\n");
 712                                 return -EINVAL;
 713                         }
 714                 }
 715                 break;
 716         case XSDIRX_MODE_SD_MASK:
 717                 format->field = V4L2_FIELD_INTERLACED;
 718
 719                 switch (family) {
 720                 case XSDIRX_NTSC:
 721                         format->width = 720;
 722                         format->height = 480;
 723                         break;
 724                 case XSDIRX_PAL:
 725                         format->width = 720;
 726                         format->height = 576;
 727                         break;
 728                 default:
 729                         dev_dbg(core->dev, "Unknown SD Mode SMPTE standard\n");
 730                         return -EINVAL;
 731                 }
 732                 break;
 733         case XSDIRX_MODE_3G_MASK:
 734                 switch (byte1) {
 735                 case XST352_BYTE1_ST425_2008_750L_3GB:
 736                         /* Sec 4.1.6.1 SMPTE 425-2008 */
 737                 case XST352_BYTE1_ST372_2x720L_3GB:
 738                         /* Table 13 SMPTE 425-2008 */
 739                         format->width = 1280;
 740                         format->height = 720;
 741                         break;
 742                 case XST352_BYTE1_ST425_2008_1125L_3GA:
 743                         /* ST352 Table SMPTE 425-1 */
 744                 case XST352_BYTE1_ST372_DL_3GB:
 745                         /* Table 13 SMPTE 425-2008 */
 746                 case XST352_BYTE1_ST372_2x1080L_3GB:
 747                         /* Table 13 SMPTE 425-2008 */
 748                         format->height = 1080;
 749                         if (active_luma)
 750                                 format->width = 2048;
 751                         else
 752                                 format->width = 1920;
 753                         break;
 754                 default:
 755                         dev_dbg(core->dev, "Unknown 3G Mode SMPTE standard\n");
 756                         return -EINVAL;
 757                 }
 758                 break;
 759         case XSDIRX_MODE_6G_MASK:
 760                 switch (byte1) {
 761                 case XST352_BYTE1_ST2081_10_DL_2160L_6G:
 762                         /* Dual link 6G */
 763                 case XST352_BYTE1_ST2081_10_2160L_6G:
 764                         /* Table 3 SMPTE ST 2081-10 */
 765                         format->height = 2160;
 766                         if (active_luma)
 767                                 format->width = 4096;
 768                         else
 769                                 format->width = 3840;
 770                         break;
 771                 default:
 772                         dev_dbg(core->dev, "Unknown 6G Mode SMPTE standard\n");
 773                         return -EINVAL;
 774                 }
 775                 break;
 776         case XSDIRX_MODE_12GI_MASK:
 777         case XSDIRX_MODE_12GF_MASK:
 778                 switch (byte1) {
 779                 case XST352_BYTE1_ST2082_10_2160L_12G:
 780                         /* Section 4.3.1 SMPTE ST 2082-10 */
 781                         format->height = 2160;
 782                         if (active_luma)
 783                                 format->width = 4096;
 784                         else
 785                                 format->width = 3840;
 786                         break;
 787                 default:
 788                         dev_dbg(core->dev, "Unknown 12G Mode SMPTE standard\n");
 789                         return -EINVAL;
 790                 };
 791                 break;
 792         default:
 793                 dev_err(core->dev, "Invalid Mode\n");
 794                 return -EINVAL;
 795         }
 796
 797         if (valid) {
 798                 if (pic_type)
 799                         format->field = V4L2_FIELD_NONE;
 800                 else
 801                         format->field = V4L2_FIELD_INTERLACED;
 802         }
 803
 804         xsdirxss_get_framerate(&state->frame_interval, framerate);
 805
 806         dev_dbg(core->dev, "Stream width = %d height = %d Field = %d payload = 0x%08x ts = 0x%08x\n",
 807                 format->width, format->height, format->field, payload, val);
 808         dev_dbg(core->dev, "frame rate numerator = %d denominator = %d\n",
 809                 state->frame_interval.numerator,
 810                 state->frame_interval.denominator);
 811         return 0;
 812 }
 813
 814 /**
 815  * xsdirxss_irq_handler - Interrupt handler for SDI Rx
 816  * @irq: IRQ number
 817  * @dev_id: Pointer to device state
 818  *
 819  * The SDI Rx interrupts are cleared by first setting and then clearing the bits
 820  * in the interrupt clear register. The interrupt status register is read only.
 821  *
 822  * Return: IRQ_HANDLED after handling interrupts
 823  */
 824 static irqreturn_t xsdirxss_irq_handler(int irq, void *dev_id)
 825 {
 826         struct xsdirxss_state *state = (struct xsdirxss_state *)dev_id;
 827         struct xsdirxss_core *core = &state->core;
 828         u32 status;
 829
 830         status = xsdirxss_read(core, XSDIRX_ISR_REG);
 831         dev_dbg(core->dev, "interrupt status = 0x%08x\n", status);
 832
 833         if (!status)
 834                 return IRQ_NONE;
 835
 836         if (status & XSDIRX_INTR_VIDLOCK_MASK) {
 837                 u32 val1, val2;
 838
 839                 dev_dbg(core->dev, "video lock interrupt\n");
 840                 xsdirx_clearintr(core, XSDIRX_INTR_VIDLOCK_MASK);
 841
 842                 val1 = xsdirxss_read(core, XSDIRX_MODE_DET_STAT_REG);
 843                 val2 = xsdirxss_read(core, XSDIRX_TS_DET_STAT_REG);
 844
 845                 if ((val1 & XSDIRX_MODE_DET_STAT_MODE_LOCK_MASK) &&
 846                     (val2 & XSDIRX_TS_DET_STAT_LOCKED_MASK)) {
 847                         u32 mask = XSDIRX_RST_CTRL_RST_CRC_ERRCNT_MASK |
 848                                    XSDIRX_RST_CTRL_RST_EDH_ERRCNT_MASK;
 849
 850                         dev_dbg(core->dev, "mode & ts lock occurred\n");
 851
 852                         xsdirxss_set(core, XSDIRX_RST_CTRL_REG, mask);
 853                         xsdirxss_clr(core, XSDIRX_RST_CTRL_REG, mask);
 854
 855                         val1 = xsdirxss_read(core, XSDIRX_ST352_VALID_REG);
 856                         val2 = xsdirxss_read(core, XSDIRX_ST352_DS1_REG);
 857
 858                         dev_dbg(core->dev, "valid st352 mask = 0x%08x\n", val1);
 859                         dev_dbg(core->dev, "st352 payload = 0x%08x\n", val2);
 860
 861                         if (!xsdirx_get_stream_properties(state)) {
 862                                 memset(&state->event, 0, sizeof(state->event));
 863                                 state->event.type = V4L2_EVENT_SOURCE_CHANGE;
 864                                 state->event.u.src_change.changes =
 865                                         V4L2_EVENT_SRC_CH_RESOLUTION;
 866                                 v4l2_subdev_notify_event(&state->subdev,
 867                                                          &state->event);
 868
 869                                 state->vidlocked = true;
 870                         } else {
 871                                 dev_err(core->dev, "Unable to get stream properties!\n");
 872                                 state->vidlocked = false;
 873                         }
 874                 } else {
 875                         dev_dbg(core->dev, "video unlock before video lock!\n");
 876                         state->vidlocked = false;
 877                 }
 878         }
 879
 880         if (status & XSDIRX_INTR_VIDUNLOCK_MASK) {
 881                 dev_dbg(core->dev, "video unlock interrupt\n");
 882                 xsdirx_clearintr(core, XSDIRX_INTR_VIDUNLOCK_MASK);
 883                 xsdirx_streamdowncb(core);
 884
 885                 memset(&state->event, 0, sizeof(state->event));
 886                 state->event.type = V4L2_EVENT_XLNXSDIRX_VIDUNLOCK;
 887                 v4l2_subdev_notify_event(&state->subdev, &state->event);
 888
 889                 state->vidlocked = false;
 890         }
 891
 892         if (status & XSDIRX_INTR_UNDERFLOW_MASK) {
 893                 dev_dbg(core->dev, "Video in to AXI4 Stream core underflow interrupt\n");
 894                 xsdirx_clearintr(core, XSDIRX_INTR_UNDERFLOW_MASK);
 895
 896                 memset(&state->event, 0, sizeof(state->event));
 897                 state->event.type = V4L2_EVENT_XLNXSDIRX_UNDERFLOW;
 898                 v4l2_subdev_notify_event(&state->subdev, &state->event);
 899         }
 900
 901         if (status & XSDIRX_INTR_OVERFLOW_MASK) {
 902                 dev_dbg(core->dev, "Video in to AXI4 Stream core overflow interrupt\n");
 903                 xsdirx_clearintr(core, XSDIRX_INTR_OVERFLOW_MASK);
 904
 905                 memset(&state->event, 0, sizeof(state->event));
 906                 state->event.type = V4L2_EVENT_XLNXSDIRX_OVERFLOW;
 907                 v4l2_subdev_notify_event(&state->subdev, &state->event);
 908         }
 909         return IRQ_HANDLED;
 910 }
 911
 912 /**
 913  * xsdirxss_subscribe_event - Subscribe to video lock and unlock event
 914  * @sd: V4L2 Sub device
 915  * @fh: V4L2 File Handle
 916  * @sub: Subcribe event structure
 917  *
 918  * Return: 0 on success, errors otherwise
 919  */
 920 static int xsdirxss_subscribe_event(struct v4l2_subdev *sd,
 921                                     struct v4l2_fh *fh,
 922                                     struct v4l2_event_subscription *sub)
 923 {
 924         int ret;
 925         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
 926         struct xsdirxss_core *core = &xsdirxss->core;
 927
 928         switch (sub->type) {
 929         case V4L2_EVENT_XLNXSDIRX_VIDUNLOCK:
 930         case V4L2_EVENT_XLNXSDIRX_UNDERFLOW:
 931         case V4L2_EVENT_XLNXSDIRX_OVERFLOW:
 932                 ret = v4l2_event_subscribe(fh, sub, XSDIRX_MAX_EVENTS, NULL);
 933                 break;
 934         case V4L2_EVENT_SOURCE_CHANGE:
 935                 ret = v4l2_src_change_event_subscribe(fh, sub);
 936                 break;
 937         default:
 938                 return -EINVAL;
 939         }
 940         dev_dbg(core->dev, "Event subscribed : 0x%08x\n", sub->type);
 941         return ret;
 942 }
 943
 944 /**
 945  * xsdirxss_unsubscribe_event - Unsubscribe from all events registered
 946  * @sd: V4L2 Sub device
 947  * @fh: V4L2 file handle
 948  * @sub: pointer to Event unsubscription structure
 949  *
 950  * Return: zero on success, else a negative error code.
 951  */
 952 static int xsdirxss_unsubscribe_event(struct v4l2_subdev *sd,
 953                                       struct v4l2_fh *fh,
 954                                       struct v4l2_event_subscription *sub)
 955 {
 956         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
 957         struct xsdirxss_core *core = &xsdirxss->core;
 958
 959         dev_dbg(core->dev, "Event unsubscribe : 0x%08x\n", sub->type);
 960         return v4l2_event_unsubscribe(fh, sub);
 961 }
 962
 963 /**
 964  * xsdirxss_s_ctrl - This is used to set the Xilinx SDI Rx V4L2 controls
 965  * @ctrl: V4L2 control to be set
 966  *
 967  * This function is used to set the V4L2 controls for the Xilinx SDI Rx
 968  * Subsystem.
 969  *
 970  * Return: 0 on success, errors otherwise
 971  */
 972 static int xsdirxss_s_ctrl(struct v4l2_ctrl *ctrl)
 973 {
 974         int ret = 0;
 975         struct xsdirxss_state *xsdirxss =
 976                 container_of(ctrl->handler,
 977                              struct xsdirxss_state, ctrl_handler);
 978         struct xsdirxss_core *core = &xsdirxss->core;
 979
 980         dev_dbg(core->dev, "set ctrl id = 0x%08x val = 0x%08x\n",
 981                 ctrl->id, ctrl->val);
 982
 983         if (xsdirxss->streaming) {
 984                 dev_err(core->dev, "Cannot set controls while streaming\n");
 985                 return -EINVAL;
 986         }
 987
 988         xsdirx_core_disable(core);
 989         switch (ctrl->id) {
 990         case V4L2_CID_XILINX_SDIRX_FRAMER:
 991                 xsdirx_framer(core, ctrl->val);
 992                 break;
 993         case V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW:
 994                 xsdirx_setvidlockwindow(core, ctrl->val);
 995                 break;
 996         case V4L2_CID_XILINX_SDIRX_EDH_ERRCNT_ENABLE:
 997                 xsdirx_setedherrcnttrigger(core, ctrl->val);
 998                 break;
 999         case V4L2_CID_XILINX_SDIRX_SEARCH_MODES:
1000                 if (ctrl->val) {
1001                         if (core->mode == XSDIRXSS_SDI_STD_3G) {
1002                                 dev_dbg(core->dev, "Upto 3G supported\n");
1003                                 ctrl->val &= ~(BIT(XSDIRX_MODE_6G_OFFSET) |
1004                                                BIT(XSDIRX_MODE_12GI_OFFSET) |
1005                                                BIT(XSDIRX_MODE_12GF_OFFSET));
1006                         }
1007
1008                         if (core->mode == XSDIRXSS_SDI_STD_6G) {
1009                                 dev_dbg(core->dev, "Upto 6G supported\n");
1010                                 ctrl->val &= ~(BIT(XSDIRX_MODE_12GI_OFFSET) |
1011                                                BIT(XSDIRX_MODE_12GF_OFFSET));
1012                         }
1013
1014                         ret = xsdirx_set_modedetect(core, ctrl->val);
1015                 } else {
1016                         dev_err(core->dev, "Select at least one mode!\n");
1017                         return -EINVAL;
1018                 }
1019                 break;
1020         default:
1021                 xsdirxss_set(core, XSDIRX_RST_CTRL_REG,
1022                              XSDIRX_RST_CTRL_SS_EN_MASK);
1023                 return -EINVAL;
1024         }
1025         xsdirx_core_enable(core);
1026         return ret;
1027 }
1028
1029 /**
1030  * xsdirxss_g_volatile_ctrl - get the Xilinx SDI Rx controls
1031  * @ctrl: Pointer to V4L2 control
1032  *
1033  * Return: 0 on success, errors otherwise
1034  */
1035 static int xsdirxss_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1036 {
1037         u32 val;
1038         struct xsdirxss_state *xsdirxss =
1039                 container_of(ctrl->handler,
1040                              struct xsdirxss_state, ctrl_handler);
1041         struct xsdirxss_core *core = &xsdirxss->core;
1042
1043         switch (ctrl->id) {
1044         case V4L2_CID_XILINX_SDIRX_MODE_DETECT:
1045                 if (!xsdirxss->vidlocked) {
1046                         dev_err(core->dev, "Can't get values when video not locked!\n");
1047                         return -EINVAL;
1048                 }
1049                 val = xsdirxss_read(core, XSDIRX_MODE_DET_STAT_REG);
1050                 val &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK;
1051
1052                 switch (val) {
1053                 case XSDIRX_MODE_SD_MASK:
1054                         ctrl->val = XSDIRX_MODE_SD_OFFSET;
1055                         break;
1056                 case XSDIRX_MODE_HD_MASK:
1057                         ctrl->val = XSDIRX_MODE_HD_OFFSET;
1058                         break;
1059                 case XSDIRX_MODE_3G_MASK:
1060                         ctrl->val = XSDIRX_MODE_3G_OFFSET;
1061                         break;
1062                 case XSDIRX_MODE_6G_MASK:
1063                         ctrl->val = XSDIRX_MODE_6G_OFFSET;
1064                         break;
1065                 case XSDIRX_MODE_12GI_MASK:
1066                         ctrl->val = XSDIRX_MODE_12GI_OFFSET;
1067                         break;
1068                 case XSDIRX_MODE_12GF_MASK:
1069                         ctrl->val = XSDIRX_MODE_12GF_OFFSET;
1070                         break;
1071                 }
1072                 break;
1073         case V4L2_CID_XILINX_SDIRX_CRC:
1074                 ctrl->val = xsdirxss_read(core, XSDIRX_CRC_ERRCNT_REG);
1075                 xsdirxss_write(core, XSDIRX_CRC_ERRCNT_REG, 0xFFFF);
1076                 break;
1077         case V4L2_CID_XILINX_SDIRX_EDH_ERRCNT:
1078                 val = xsdirxss_read(core, XSDIRX_MODE_DET_STAT_REG);
1079                 val &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK;
1080                 if (val == XSDIRX_MODE_SD_MASK) {
1081                         ctrl->val = xsdirxss_read(core, XSDIRX_EDH_ERRCNT_REG);
1082                 } else {
1083                         dev_dbg(core->dev, "%d - not in SD mode\n", ctrl->id);
1084                         return -EINVAL;
1085                 }
1086                 break;
1087         case V4L2_CID_XILINX_SDIRX_EDH_STATUS:
1088                 val = xsdirxss_read(core, XSDIRX_MODE_DET_STAT_REG);
1089                 val &= XSDIRX_MODE_DET_STAT_RX_MODE_MASK;
1090                 if (val == XSDIRX_MODE_SD_MASK) {
1091                         ctrl->val = xsdirxss_read(core, XSDIRX_EDH_STAT_REG);
1092                 } else {
1093                         dev_dbg(core->dev, "%d - not in SD mode\n", ctrl->id);
1094                         return -EINVAL;
1095                 }
1096                 break;
1097         case V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED:
1098                 if (!xsdirxss->vidlocked) {
1099                         dev_err(core->dev, "Can't get values when video not locked!\n");
1100                         return -EINVAL;
1101                 }
1102                 ctrl->val = xsdirxss->ts_is_interlaced;
1103                 break;
1104         default:
1105                 dev_err(core->dev, "Get Invalid control id 0x%0x\n", ctrl->id);
1106                 return -EINVAL;
1107         }
1108         dev_dbg(core->dev, "Get ctrl id = 0x%08x val = 0x%08x\n",
1109                 ctrl->id, ctrl->val);
1110         return 0;
1111 }
1112
1113 /**
1114  * xsdirxss_log_status - Logs the status of the SDI Rx Subsystem
1115  * @sd: Pointer to V4L2 subdevice structure
1116  *
1117  * This function prints the current status of Xilinx SDI Rx Subsystem
1118  *
1119  * Return: 0 on success
1120  */
1121 static int xsdirxss_log_status(struct v4l2_subdev *sd)
1122 {
1123         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
1124         struct xsdirxss_core *core = &xsdirxss->core;
1125         u32 data, i;
1126
1127         v4l2_info(sd, "***** SDI Rx subsystem reg dump start *****\n");
1128         for (i = 0; i < 0x28; i++) {
1129                 data = xsdirxss_read(core, i * 4);
1130                 v4l2_info(sd, "offset 0x%08x data 0x%08x\n",
1131                           i * 4, data);
1132         }
1133         v4l2_info(sd, "***** SDI Rx subsystem reg dump end *****\n");
1134         return 0;
1135 }
1136
1137 static void xsdirxss_start_stream(struct xsdirxss_state *xsdirxss)
1138 {
1139         xsdirx_streamflow_control(&xsdirxss->core, true);
1140 }
1141
1142 static void xsdirxss_stop_stream(struct xsdirxss_state *xsdirxss)
1143 {
1144         xsdirx_streamflow_control(&xsdirxss->core, false);
1145 }
1146
1147 /**
1148  * xsdirxss_g_frame_interval - Get the frame interval
1149  * @sd: V4L2 Sub device
1150  * @fi: Pointer to V4l2 Sub device frame interval structure
1151  *
1152  * This function is used to get the frame interval.
1153  * The frame rate can be integral or fractional.
1154  * Integral frame rate e.g. numerator = 1000, denominator = 24000 => 24 fps
1155  * Fractional frame rate e.g. numerator = 1001, denominator = 24000 => 23.97 fps
1156  *
1157  * Return: 0 on success
1158  */
1159 static int xsdirxss_g_frame_interval(struct v4l2_subdev *sd,
1160                                      struct v4l2_subdev_frame_interval *fi)
1161 {
1162         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
1163         struct xsdirxss_core *core = &xsdirxss->core;
1164
1165         if (!xsdirxss->vidlocked) {
1166                 dev_err(core->dev, "Video not locked!\n");
1167                 return -EINVAL;
1168         }
1169
1170         fi->interval = xsdirxss->frame_interval;
1171
1172         dev_dbg(core->dev, "frame rate numerator = %d denominator = %d\n",
1173                 xsdirxss->frame_interval.numerator,
1174                 xsdirxss->frame_interval.denominator);
1175         return 0;
1176 }
1177
1178 /**
1179  * xsdirxss_s_stream - It is used to start/stop the streaming.
1180  * @sd: V4L2 Sub device
1181  * @enable: Flag (True / False)
1182  *
1183  * This function controls the start or stop of streaming for the
1184  * Xilinx SDI Rx Subsystem.
1185  *
1186  * Return: 0 on success, errors otherwise
1187  */
1188 static int xsdirxss_s_stream(struct v4l2_subdev *sd, int enable)
1189 {
1190         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
1191         struct xsdirxss_core *core = &xsdirxss->core;
1192
1193         if (enable) {
1194                 if (!xsdirxss->vidlocked) {
1195                         dev_dbg(core->dev, "Video is not locked\n");
1196                         return -EINVAL;
1197                 }
1198                 if (xsdirxss->streaming) {
1199                         dev_dbg(core->dev, "Already streaming\n");
1200                         return -EINVAL;
1201                 }
1202
1203                 xsdirxss_start_stream(xsdirxss);
1204                 xsdirxss->streaming = true;
1205                 dev_dbg(core->dev, "Streaming started\n");
1206         } else {
1207                 if (!xsdirxss->streaming) {
1208                         dev_dbg(core->dev, "Stopped streaming already\n");
1209                         return -EINVAL;
1210                 }
1211
1212                 xsdirxss_stop_stream(xsdirxss);
1213                 xsdirxss->streaming = false;
1214                 dev_dbg(core->dev, "Streaming stopped\n");
1215         }
1216
1217         return 0;
1218 }
1219
1220 static struct v4l2_mbus_framefmt *
1221 __xsdirxss_get_pad_format(struct xsdirxss_state *xsdirxss,
1222                           struct v4l2_subdev_pad_config *cfg,
1223                                 unsigned int pad, u32 which)
1224 {
1225         switch (which) {
1226         case V4L2_SUBDEV_FORMAT_TRY:
1227                 return v4l2_subdev_get_try_format(&xsdirxss->subdev, cfg, pad);
1228         case V4L2_SUBDEV_FORMAT_ACTIVE:
1229                 return &xsdirxss->formats[pad];
1230         default:
1231                 return NULL;
1232         }
1233 }
1234
1235 /**
1236  * xsdirxss_get_format - Get the pad format
1237  * @sd: Pointer to V4L2 Sub device structure
1238  * @cfg: Pointer to sub device pad information structure
1239  * @fmt: Pointer to pad level media bus format
1240  *
1241  * This function is used to get the pad format information.
1242  *
1243  * Return: 0 on success
1244  */
1245 static int xsdirxss_get_format(struct v4l2_subdev *sd,
1246                                struct v4l2_subdev_pad_config *cfg,
1247                                         struct v4l2_subdev_format *fmt)
1248 {
1249         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
1250         struct xsdirxss_core *core = &xsdirxss->core;
1251
1252         if (!xsdirxss->vidlocked) {
1253                 dev_err(core->dev, "Video not locked!\n");
1254                 return -EINVAL;
1255         }
1256
1257         fmt->format = *__xsdirxss_get_pad_format(xsdirxss, cfg,
1258                                                  fmt->pad, fmt->which);
1259
1260         dev_dbg(core->dev, "Stream width = %d height = %d Field = %d\n",
1261                 fmt->format.width, fmt->format.height, fmt->format.field);
1262
1263         return 0;
1264 }
1265
1266 /**
1267  * xsdirxss_set_format - This is used to set the pad format
1268  * @sd: Pointer to V4L2 Sub device structure
1269  * @cfg: Pointer to sub device pad information structure
1270  * @fmt: Pointer to pad level media bus format
1271  *
1272  * This function is used to set the pad format.
1273  * Since the pad format is fixed in hardware, it can't be
1274  * modified on run time.
1275  *
1276  * Return: 0 on success
1277  */
1278 static int xsdirxss_set_format(struct v4l2_subdev *sd,
1279                                struct v4l2_subdev_pad_config *cfg,
1280                                 struct v4l2_subdev_format *fmt)
1281 {
1282         struct v4l2_mbus_framefmt *__format;
1283         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
1284
1285         dev_dbg(xsdirxss->core.dev,
1286                 "set width %d height %d code %d field %d colorspace %d\n",
1287                 fmt->format.width, fmt->format.height,
1288                 fmt->format.code, fmt->format.field,
1289                 fmt->format.colorspace);
1290
1291         __format = __xsdirxss_get_pad_format(xsdirxss, cfg,
1292                                              fmt->pad, fmt->which);
1293
1294         /* Currently reset the code to one fixed in hardware */
1295         /* TODO : Add checks for width height */
1296         fmt->format.code = __format->code;
1297
1298         return 0;
1299 }
1300
1301 /**
1302  * xsdirxss_open - Called on v4l2_open()
1303  * @sd: Pointer to V4L2 sub device structure
1304  * @fh: Pointer to V4L2 File handle
1305  *
1306  * This function is called on v4l2_open(). It sets the default format for pad.
1307  *
1308  * Return: 0 on success
1309  */
1310 static int xsdirxss_open(struct v4l2_subdev *sd,
1311                          struct v4l2_subdev_fh *fh)
1312 {
1313         struct v4l2_mbus_framefmt *format;
1314         struct xsdirxss_state *xsdirxss = to_xsdirxssstate(sd);
1315
1316         format = v4l2_subdev_get_try_format(sd, fh->pad, 0);
1317         *format = xsdirxss->default_format;
1318
1319         return 0;
1320 }
1321
1322 /**
1323  * xsdirxss_close - Called on v4l2_close()
1324  * @sd: Pointer to V4L2 sub device structure
1325  * @fh: Pointer to V4L2 File handle
1326  *
1327  * This function is called on v4l2_close().
1328  *
1329  * Return: 0 on success
1330  */
1331 static int xsdirxss_close(struct v4l2_subdev *sd,
1332                           struct v4l2_subdev_fh *fh)
1333 {
1334         return 0;
1335 }
1336
1337 /* -----------------------------------------------------------------------------
1338  * Media Operations
1339  */
1340
1341 static const struct media_entity_operations xsdirxss_media_ops = {
1342         .link_validate = v4l2_subdev_link_validate
1343 };
1344
1345 static const struct v4l2_ctrl_ops xsdirxss_ctrl_ops = {
1346         .g_volatile_ctrl = xsdirxss_g_volatile_ctrl,
1347         .s_ctrl = xsdirxss_s_ctrl
1348 };
1349
1350 static struct v4l2_ctrl_config xsdirxss_edh_ctrls[] = {
1351         {
1352                 .ops    = &xsdirxss_ctrl_ops,
1353                 .id     = V4L2_CID_XILINX_SDIRX_EDH_ERRCNT_ENABLE,
1354                 .name   = "SDI Rx : EDH Error Count Enable",
1355                 .type   = V4L2_CTRL_TYPE_BITMASK,
1356                 .min    = 0,
1357                 .max    = XSDIRX_EDH_ALLERR_MASK,
1358                 .def    = 0,
1359         }, {
1360                 .ops    = &xsdirxss_ctrl_ops,
1361                 .id     = V4L2_CID_XILINX_SDIRX_EDH_ERRCNT,
1362                 .name   = "SDI Rx : EDH Error Count",
1363                 .type   = V4L2_CTRL_TYPE_INTEGER,
1364                 .min    = 0,
1365                 .max    = 0xFFFF,
1366                 .step   = 1,
1367                 .def    = 0,
1368                 .flags  = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY,
1369         }, {
1370                 .ops    = &xsdirxss_ctrl_ops,
1371                 .id     = V4L2_CID_XILINX_SDIRX_EDH_STATUS,
1372                 .name   = "SDI Rx : EDH Status",
1373                 .type   = V4L2_CTRL_TYPE_INTEGER,
1374                 .min    = 0,
1375                 .max    = 0xFFFFFFFF,
1376                 .step   = 1,
1377                 .def    = 0,
1378                 .flags  = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY,
1379         }
1380 };
1381
1382 static struct v4l2_ctrl_config xsdirxss_ctrls[] = {
1383         {
1384                 .ops    = &xsdirxss_ctrl_ops,
1385                 .id     = V4L2_CID_XILINX_SDIRX_FRAMER,
1386                 .name   = "SDI Rx : Enable Framer",
1387                 .type   = V4L2_CTRL_TYPE_BOOLEAN,
1388                 .min    = false,
1389                 .max    = true,
1390                 .step   = 1,
1391                 .def    = true,
1392         }, {
1393                 .ops    = &xsdirxss_ctrl_ops,
1394                 .id     = V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW,
1395                 .name   = "SDI Rx : Video Lock Window",
1396                 .type   = V4L2_CTRL_TYPE_INTEGER,
1397                 .min    = 0,
1398                 .max    = 0xFFFF,
1399                 .step   = 1,
1400                 .def    = XSDIRX_DEFAULT_VIDEO_LOCK_WINDOW,
1401         }, {
1402                 .ops    = &xsdirxss_ctrl_ops,
1403                 .id     = V4L2_CID_XILINX_SDIRX_SEARCH_MODES,
1404                 .name   = "SDI Rx : Modes search Mask",
1405                 .type   = V4L2_CTRL_TYPE_BITMASK,
1406                 .min    = 0,
1407                 .max    = XSDIRX_DETECT_ALL_MODES,
1408                 .def    = XSDIRX_DETECT_ALL_MODES,
1409         }, {
1410                 .ops    = &xsdirxss_ctrl_ops,
1411                 .id     = V4L2_CID_XILINX_SDIRX_MODE_DETECT,
1412                 .name   = "SDI Rx : Mode Detect Status",
1413                 .type   = V4L2_CTRL_TYPE_INTEGER,
1414                 .min    = XSDIRX_MODE_SD_OFFSET,
1415                 .max    = XSDIRX_MODE_12GF_OFFSET,
1416                 .step   = 1,
1417                 .flags  = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY,
1418         }, {
1419                 .ops    = &xsdirxss_ctrl_ops,
1420                 .id     = V4L2_CID_XILINX_SDIRX_CRC,
1421                 .name   = "SDI Rx : CRC Error status",
1422                 .type   = V4L2_CTRL_TYPE_INTEGER,
1423                 .min    = 0,
1424                 .max    = 0xFFFFFFFF,
1425                 .step   = 1,
1426                 .def    = 0,
1427                 .flags  = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY,
1428         }, {
1429                 .ops    = &xsdirxss_ctrl_ops,
1430                 .id     = V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED,
1431                 .name   = "SDI Rx : TS is Interlaced",
1432                 .type   = V4L2_CTRL_TYPE_BOOLEAN,
1433                 .min    = false,
1434                 .max    = true,
1435                 .def    = false,
1436                 .step   = 1,
1437                 .flags  = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY,
1438         }
1439 };
1440
1441 static const struct v4l2_subdev_core_ops xsdirxss_core_ops = {
1442         .log_status = xsdirxss_log_status,
1443         .subscribe_event = xsdirxss_subscribe_event,
1444         .unsubscribe_event = xsdirxss_unsubscribe_event
1445 };
1446
1447 static struct v4l2_subdev_video_ops xsdirxss_video_ops = {
1448         .g_frame_interval = xsdirxss_g_frame_interval,
1449         .s_stream = xsdirxss_s_stream
1450 };
1451
1452 static struct v4l2_subdev_pad_ops xsdirxss_pad_ops = {
1453         .get_fmt = xsdirxss_get_format,
1454         .set_fmt = xsdirxss_set_format,
1455 };
1456
1457 static struct v4l2_subdev_ops xsdirxss_ops = {
1458         .core = &xsdirxss_core_ops,
1459         .video = &xsdirxss_video_ops,
1460         .pad = &xsdirxss_pad_ops
1461 };
1462
1463 static const struct v4l2_subdev_internal_ops xsdirxss_internal_ops = {
1464         .open = xsdirxss_open,
1465         .close = xsdirxss_close
1466 };
1467
1468 /* -----------------------------------------------------------------------------
1469  * Platform Device Driver
1470  */
1471
1472 static int xsdirxss_parse_of(struct xsdirxss_state *xsdirxss)
1473 {
1474         struct device_node *node = xsdirxss->core.dev->of_node;
1475         struct device_node *ports = NULL;
1476         struct device_node *port = NULL;
1477         unsigned int nports = 0;
1478         struct xsdirxss_core *core = &xsdirxss->core;
1479         int ret;
1480         const char *sdi_std;
1481
1482         core->include_edh = of_property_read_bool(node, "xlnx,include-edh");
1483         dev_dbg(core->dev, "EDH property = %s\n",
1484                 core->include_edh ? "Present" : "Absent");
1485
1486         ret = of_property_read_string(node, "xlnx,line-rate",
1487                                       &sdi_std);
1488         if (ret < 0) {
1489                 dev_err(core->dev, "xlnx,line-rate property not found\n");
1490                 return ret;
1491         }
1492
1493         if (!strncmp(sdi_std, "12G_SDI_8DS", XSDIRX_MAX_STR_LENGTH)) {
1494                 core->mode = XSDIRXSS_SDI_STD_12G_8DS;
1495         } else if (!strncmp(sdi_std, "6G_SDI", XSDIRX_MAX_STR_LENGTH)) {
1496                 core->mode = XSDIRXSS_SDI_STD_6G;
1497         } else if (!strncmp(sdi_std, "3G_SDI", XSDIRX_MAX_STR_LENGTH)) {
1498                 core->mode = XSDIRXSS_SDI_STD_3G;
1499         } else {
1500                 dev_err(core->dev, "Invalid Line Rate\n");
1501                 return -EINVAL;
1502         }
1503         dev_dbg(core->dev, "SDI Rx Line Rate = %s, mode = %d\n", sdi_std,
1504                 core->mode);
1505
1506         ports = of_get_child_by_name(node, "ports");
1507         if (!ports)
1508                 ports = node;
1509
1510         for_each_child_of_node(ports, port) {
1511                 const struct xvip_video_format *format;
1512                 struct device_node *endpoint;
1513
1514                 if (!port->name || of_node_cmp(port->name, "port"))
1515                         continue;
1516
1517                 format = xvip_of_get_format(port);
1518                 if (IS_ERR(format)) {
1519                         dev_err(core->dev, "invalid format in DT");
1520                         return PTR_ERR(format);
1521                 }
1522
1523                 dev_dbg(core->dev, "vf_code = %d bpc = %d bpp = %d\n",
1524                         format->vf_code, format->width, format->bpp);
1525
1526                 if (format->vf_code != XVIP_VF_YUV_422) {
1527                         dev_err(core->dev, "Incorrect UG934 video format set. Accepts only YUV422\n");
1528                         return -EINVAL;
1529                 }
1530                 xsdirxss->vip_format = format;
1531
1532                 endpoint = of_get_next_child(port, NULL);
1533                 if (!endpoint) {
1534                         dev_err(core->dev, "No port at\n");
1535                         return -EINVAL;
1536                 }
1537
1538                 /* Count the number of ports. */
1539                 nports++;
1540         }
1541
1542         if (nports != 1) {
1543                 dev_err(core->dev, "invalid number of ports %u\n", nports);
1544                 return -EINVAL;
1545         }
1546
1547         /* Register interrupt handler */
1548         core->irq = irq_of_parse_and_map(node, 0);
1549
1550         ret = devm_request_irq(core->dev, core->irq, xsdirxss_irq_handler,
1551                                IRQF_SHARED, "xilinx-sdirxss", xsdirxss);
1552         if (ret) {
1553                 dev_err(core->dev, "Err = %d Interrupt handler reg failed!\n",
1554                         ret);
1555                 return ret;
1556         }
1557
1558         return 0;
1559 }
1560
1561 static int xsdirxss_probe(struct platform_device *pdev)
1562 {
1563         struct v4l2_subdev *subdev;
1564         struct xsdirxss_state *xsdirxss;
1565         struct xsdirxss_core *core;
1566         struct resource *res;
1567         int ret;
1568         unsigned int num_ctrls, num_edh_ctrls = 0, i;
1569
1570         xsdirxss = devm_kzalloc(&pdev->dev, sizeof(*xsdirxss), GFP_KERNEL);
1571         if (!xsdirxss)
1572                 return -ENOMEM;
1573
1574         xsdirxss->core.dev = &pdev->dev;
1575         core = &xsdirxss->core;
1576
1577         ret = xsdirxss_parse_of(xsdirxss);
1578         if (ret < 0)
1579                 return ret;
1580
1581         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1582         xsdirxss->core.iomem = devm_ioremap_resource(xsdirxss->core.dev, res);
1583         if (IS_ERR(xsdirxss->core.iomem))
1584                 return PTR_ERR(xsdirxss->core.iomem);
1585
1586         /* Reset the core */
1587         xsdirx_streamflow_control(core, false);
1588         xsdirx_core_disable(core);
1589         xsdirx_clearintr(core, XSDIRX_INTR_ALL_MASK);
1590         xsdirx_disableintr(core, XSDIRX_INTR_ALL_MASK);
1591         xsdirx_enableintr(core, XSDIRX_INTR_ALL_MASK);
1592         xsdirx_globalintr(core, true);
1593         xsdirxss_write(core, XSDIRX_CRC_ERRCNT_REG, 0xFFFF);
1594
1595         /* Initialize V4L2 subdevice and media entity */
1596         xsdirxss->pads[0].flags = MEDIA_PAD_FL_SOURCE;
1597
1598         /* Initialize the default format */
1599         xsdirxss->default_format.code = xsdirxss->vip_format->code;
1600         xsdirxss->default_format.field = V4L2_FIELD_NONE;
1601         xsdirxss->default_format.colorspace = V4L2_COLORSPACE_DEFAULT;
1602         xsdirxss->default_format.width = XSDIRX_DEFAULT_WIDTH;
1603         xsdirxss->default_format.height = XSDIRX_DEFAULT_HEIGHT;
1604
1605         xsdirxss->formats[0] = xsdirxss->default_format;
1606
1607         /* Initialize V4L2 subdevice and media entity */
1608         subdev = &xsdirxss->subdev;
1609         v4l2_subdev_init(subdev, &xsdirxss_ops);
1610
1611         subdev->dev = &pdev->dev;
1612         subdev->internal_ops = &xsdirxss_internal_ops;
1613         strlcpy(subdev->name, dev_name(&pdev->dev), sizeof(subdev->name));
1614
1615         subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
1616
1617         subdev->entity.ops = &xsdirxss_media_ops;
1618
1619         v4l2_set_subdevdata(subdev, xsdirxss);
1620
1621         ret = media_entity_pads_init(&subdev->entity, 1, xsdirxss->pads);
1622         if (ret < 0)
1623                 goto error;
1624
1625         /* Initialise and register the controls */
1626         num_ctrls = ARRAY_SIZE(xsdirxss_ctrls);
1627
1628         if (xsdirxss->core.include_edh)
1629                 num_edh_ctrls = ARRAY_SIZE(xsdirxss_edh_ctrls);
1630
1631         v4l2_ctrl_handler_init(&xsdirxss->ctrl_handler,
1632                                (num_ctrls + num_edh_ctrls));
1633
1634         for (i = 0; i < num_ctrls; i++) {
1635                 struct v4l2_ctrl *ctrl;
1636
1637                 dev_dbg(xsdirxss->core.dev, "%d %s ctrl = 0x%x\n",
1638                         i, xsdirxss_ctrls[i].name, xsdirxss_ctrls[i].id);
1639
1640                 ctrl = v4l2_ctrl_new_custom(&xsdirxss->ctrl_handler,
1641                                             &xsdirxss_ctrls[i], NULL);
1642                 if (!ctrl) {
1643                         dev_dbg(xsdirxss->core.dev, "Failed to add %s ctrl\n",
1644                                 xsdirxss_ctrls[i].name);
1645                         goto error;
1646                 }
1647         }
1648
1649         if (xsdirxss->core.include_edh) {
1650                 for (i = 0; i < num_edh_ctrls; i++) {
1651                         struct v4l2_ctrl *ctrl;
1652
1653                         dev_dbg(xsdirxss->core.dev, "%d %s ctrl = 0x%x\n",
1654                                 i, xsdirxss_edh_ctrls[i].name,
1655                                 xsdirxss_edh_ctrls[i].id);
1656
1657                         ctrl = v4l2_ctrl_new_custom(&xsdirxss->ctrl_handler,
1658                                                     &xsdirxss_edh_ctrls[i],
1659                                                     NULL);
1660                         if (!ctrl) {
1661                                 dev_dbg(xsdirxss->core.dev, "Failed to add %s ctrl\n",
1662                                         xsdirxss_edh_ctrls[i].name);
1663                                 goto error;
1664                         }
1665                 }
1666         } else {
1667                 dev_dbg(xsdirxss->core.dev, "Not registering the EDH controls as EDH is disabled in IP\n");
1668         }
1669
1670         if (xsdirxss->ctrl_handler.error) {
1671                 dev_err(&pdev->dev, "failed to add controls\n");
1672                 ret = xsdirxss->ctrl_handler.error;
1673                 goto error;
1674         }
1675
1676         subdev->ctrl_handler = &xsdirxss->ctrl_handler;
1677
1678         ret = v4l2_ctrl_handler_setup(&xsdirxss->ctrl_handler);
1679         if (ret < 0) {
1680                 dev_err(&pdev->dev, "failed to set controls\n");
1681                 goto error;
1682         }
1683
1684         platform_set_drvdata(pdev, xsdirxss);
1685
1686         ret = v4l2_async_register_subdev(subdev);
1687         if (ret < 0) {
1688                 dev_err(&pdev->dev, "failed to register subdev\n");
1689                 goto error;
1690         }
1691
1692         xsdirxss->streaming = false;
1693
1694         dev_info(xsdirxss->core.dev, "Xilinx SDI Rx Subsystem device found!\n");
1695
1696         xsdirx_core_enable(core);
1697
1698         return 0;
1699 error:
1700         v4l2_ctrl_handler_free(&xsdirxss->ctrl_handler);
1701         media_entity_cleanup(&subdev->entity);
1702
1703         return ret;
1704 }
1705
1706 static int xsdirxss_remove(struct platform_device *pdev)
1707 {
1708         struct xsdirxss_state *xsdirxss = platform_get_drvdata(pdev);
1709         struct v4l2_subdev *subdev = &xsdirxss->subdev;
1710
1711         v4l2_async_unregister_subdev(subdev);
1712         v4l2_ctrl_handler_free(&xsdirxss->ctrl_handler);
1713         media_entity_cleanup(&subdev->entity);
1714
1715         return 0;
1716 }
1717
1718 static const struct of_device_id xsdirxss_of_id_table[] = {
1719         { .compatible = "xlnx,v-smpte-uhdsdi-rx-ss" },
1720         { }
1721 };
1722 MODULE_DEVICE_TABLE(of, xsdirxss_of_id_table);
1723
1724 static struct platform_driver xsdirxss_driver = {
1725         .driver = {
1726                 .name           = "xilinx-sdirxss",
1727                 .of_match_table = xsdirxss_of_id_table,
1728         },
1729         .probe                  = xsdirxss_probe,
1730         .remove                 = xsdirxss_remove,
1731 };
1732
1733 module_platform_driver(xsdirxss_driver);
1734
1735 MODULE_AUTHOR("Vishal Sagar <vsagar@xilinx.com>");
1736 MODULE_DESCRIPTION("Xilinx SDI Rx Subsystem Driver");
1737 MODULE_LICENSE("GPL v2");