drivers/mmc/host/sdhci-of-arasan.c

   1 /*
   2  * Arasan Secure Digital Host Controller Interface.
   3  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
   4  * Copyright (c) 2012 Wind River Systems, Inc.
   5  * Copyright (C) 2013 Pengutronix e.K.
   6  * Copyright (C) 2013 Xilinx Inc.
   7  *
   8  * Based on sdhci-of-esdhc.c
   9  *
  10  * Copyright (c) 2007 Freescale Semiconductor, Inc.
  11  * Copyright (c) 2009 MontaVista Software, Inc.
  12  *
  13  * Authors: Xiaobo Xie <X.Xie@freescale.com>
  14  *          Anton Vorontsov <avorontsov@ru.mvista.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or (at
  19  * your option) any later version.
  20  */
  21
  22 #include <linux/clk-provider.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/module.h>
  25 #include <linux/delay.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/phy/phy.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/soc/xilinx/zynqmp/tap_delays.h>
  31 #include <linux/soc/xilinx/zynqmp/fw.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/regmap.h>
  34 #include "sdhci-pltfm.h"
  35 #include <linux/of.h>
  36 #include <linux/slab.h>
  37
  38 #define SDHCI_ARASAN_VENDOR_REGISTER    0x78
  39
  40 #define VENDOR_ENHANCED_STROBE          BIT(0)
  41 #define CLK_CTRL_TIMEOUT_SHIFT          16
  42 #define CLK_CTRL_TIMEOUT_MASK           (0xf << CLK_CTRL_TIMEOUT_SHIFT)
  43 #define CLK_CTRL_TIMEOUT_MIN_EXP        13
  44 #define SD_CLK_25_MHZ                           25000000
  45 #define SD_CLK_19_MHZ                           19000000
  46 #define MAX_TUNING_LOOP 40
  47
  48 #define PHY_CLK_TOO_SLOW_HZ             400000
  49
  50 /*
  51  * On some SoCs the syscon area has a feature where the upper 16-bits of
  52  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
  53  * atomic updates of the register without locking.  This macro is used on SoCs
  54  * that have that feature.
  55  */
  56 #define HIWORD_UPDATE(val, mask, shift) \
  57                 ((val) << (shift) | (mask) << ((shift) + 16))
  58
  59 /**
  60  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
  61  *
  62  * @reg:        Offset within the syscon of the register containing this field
  63  * @width:      Number of bits for this field
  64  * @shift:      Bit offset within @reg of this field (or -1 if not avail)
  65  */
  66 struct sdhci_arasan_soc_ctl_field {
  67         u32 reg;
  68         u16 width;
  69         s16 shift;
  70 };
  71
  72 /**
  73  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
  74  *
  75  * It's up to the licensee of the Arsan IP block to make these available
  76  * somewhere if needed.  Presumably these will be scattered somewhere that's
  77  * accessible via the syscon API.
  78  *
  79  * @baseclkfreq:        Where to find corecfg_baseclkfreq
  80  * @clockmultiplier:    Where to find corecfg_clockmultiplier
  81  * @hiword_update:      If true, use HIWORD_UPDATE to access the syscon
  82  */
  83 struct sdhci_arasan_soc_ctl_map {
  84         struct sdhci_arasan_soc_ctl_field       baseclkfreq;
  85         struct sdhci_arasan_soc_ctl_field       clockmultiplier;
  86         bool                                    hiword_update;
  87 };
  88
  89 /**
  90  * struct sdhci_arasan_data
  91  * @host:               Pointer to the main SDHCI host structure.
  92  * @clk_ahb:            Pointer to the AHB clock
  93  * @phy:                Pointer to the generic phy
  94  * @is_phy_on:          True if the PHY is on; false if not.
  95  * @sdcardclk_hw:       Struct for the clock we might provide to a PHY.
  96  * @sdcardclk:          Pointer to normal 'struct clock' for sdcardclk_hw.
  97  * @soc_ctl_base:       Pointer to regmap for syscon for soc_ctl registers.
  98  * @soc_ctl_map:        Map to get offsets into soc_ctl registers.
  99  */
 100 struct sdhci_arasan_data {
 101         struct sdhci_host *host;
 102         struct clk      *clk_ahb;
 103         struct phy      *phy;
 104         u32 mio_bank;
 105         u32 device_id;
 106         bool            is_phy_on;
 107
 108         struct clk_hw   sdcardclk_hw;
 109         struct clk      *sdcardclk;
 110
 111         struct regmap   *soc_ctl_base;
 112         struct pinctrl *pinctrl;
 113         struct pinctrl_state *pins_default;
 114         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
 115         unsigned int    quirks; /* Arasan deviations from spec */
 116
 117 /* Controller does not have CD wired and will not function normally without */
 118 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
 119 };
 120
 121 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
 122         .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
 123         .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
 124         .hiword_update = true,
 125 };
 126
 127 /**
 128  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
 129  *
 130  * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
 131  * Note that if a field is specified as not available (shift < 0) then
 132  * this function will silently return an error code.  It will be noisy
 133  * and print errors for any other (unexpected) errors.
 134  *
 135  * @host:       The sdhci_host
 136  * @fld:        The field to write to
 137  * @val:        The value to write
 138  */
 139 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
 140                                    const struct sdhci_arasan_soc_ctl_field *fld,
 141                                    u32 val)
 142 {
 143         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 144         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 145         struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
 146         u32 reg = fld->reg;
 147         u16 width = fld->width;
 148         s16 shift = fld->shift;
 149         int ret;
 150
 151         /*
 152          * Silently return errors for shift < 0 so caller doesn't have
 153          * to check for fields which are optional.  For fields that
 154          * are required then caller needs to do something special
 155          * anyway.
 156          */
 157         if (shift < 0)
 158                 return -EINVAL;
 159
 160         if (sdhci_arasan->soc_ctl_map->hiword_update)
 161                 ret = regmap_write(soc_ctl_base, reg,
 162                                    HIWORD_UPDATE(val, GENMASK(width, 0),
 163                                                  shift));
 164         else
 165                 ret = regmap_update_bits(soc_ctl_base, reg,
 166                                          GENMASK(shift + width, shift),
 167                                          val << shift);
 168
 169         /* Yell about (unexpected) regmap errors */
 170         if (ret)
 171                 pr_warn("%s: Regmap write fail: %d\n",
 172                          mmc_hostname(host->mmc), ret);
 173
 174         return ret;
 175 }
 176
 177 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
 178 {
 179         u16 clk;
 180         unsigned long timeout;
 181
 182         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 183         clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
 184         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 185
 186         /* Issue DLL Reset */
 187         zynqmp_dll_reset(deviceid);
 188
 189         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 190         clk |= SDHCI_CLOCK_INT_EN;
 191         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 192
 193         /* Wait max 20 ms */
 194         timeout = 20;
 195         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 196                                 & SDHCI_CLOCK_INT_STABLE)) {
 197                 if (timeout == 0) {
 198                         dev_err(mmc_dev(host->mmc),
 199                                 ": Internal clock never stabilised.\n");
 200                         return;
 201                 }
 202                 timeout--;
 203                 mdelay(1);
 204         }
 205
 206         clk |= SDHCI_CLOCK_CARD_EN;
 207         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 208 }
 209
 210 static int arasan_zynqmp_execute_tuning(struct sdhci_host *host, u32 opcode)
 211 {
 212         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 213         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 214         struct mmc_host *mmc = host->mmc;
 215         u16 ctrl;
 216         int tuning_loop_counter = MAX_TUNING_LOOP;
 217         int err = 0;
 218         unsigned long flags;
 219         unsigned int tuning_count = 0;
 220
 221         spin_lock_irqsave(&host->lock, flags);
 222
 223         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
 224                 tuning_count = host->tuning_count;
 225
 226         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 227         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 228         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
 229                 ctrl |= SDHCI_CTRL_TUNED_CLK;
 230         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 231
 232         mdelay(1);
 233
 234         arasan_zynqmp_dll_reset(host, sdhci_arasan->device_id);
 235
 236         /*
 237          * As per the Host Controller spec v3.00, tuning command
 238          * generates Buffer Read Ready interrupt, so enable that.
 239          *
 240          * Note: The spec clearly says that when tuning sequence
 241          * is being performed, the controller does not generate
 242          * interrupts other than Buffer Read Ready interrupt. But
 243          * to make sure we don't hit a controller bug, we _only_
 244          * enable Buffer Read Ready interrupt here.
 245          */
 246         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 247         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 248
 249         /*
 250          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
 251          * of loops reaches 40 times or a timeout of 150ms occurs.
 252          */
 253         do {
 254                 struct mmc_command cmd = {0};
 255                 struct mmc_request mrq = {NULL};
 256
 257                 cmd.opcode = opcode;
 258                 cmd.arg = 0;
 259                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 260                 cmd.retries = 0;
 261                 cmd.data = NULL;
 262                 cmd.mrq = &mrq;
 263                 cmd.error = 0;
 264
 265                 if (tuning_loop_counter-- == 0)
 266                         break;
 267
 268                 mrq.cmd = &cmd;
 269
 270                 /*
 271                  * In response to CMD19, the card sends 64 bytes of tuning
 272                  * block to the Host Controller. So we set the block size
 273                  * to 64 here.
 274                  */
 275                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
 276                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 277                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
 278                                              SDHCI_BLOCK_SIZE);
 279                         } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
 280                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
 281                                              SDHCI_BLOCK_SIZE);
 282                         }
 283                 } else {
 284                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
 285                                      SDHCI_BLOCK_SIZE);
 286                 }
 287
 288                 /*
 289                  * The tuning block is sent by the card to the host controller.
 290                  * So we set the TRNS_READ bit in the Transfer Mode register.
 291                  * This also takes care of setting DMA Enable and Multi Block
 292                  * Select in the same register to 0.
 293                  */
 294                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 295
 296                 sdhci_send_command(host, &cmd);
 297
 298                 host->cmd = NULL;
 299
 300                 spin_unlock_irqrestore(&host->lock, flags);
 301                 /* Wait for Buffer Read Ready interrupt */
 302                 wait_event_interruptible_timeout(host->buf_ready_int,
 303                                         (host->tuning_done == 1),
 304                                         msecs_to_jiffies(50));
 305                 spin_lock_irqsave(&host->lock, flags);
 306
 307                 if (!host->tuning_done) {
 308                         dev_warn(mmc_dev(host->mmc),
 309                                  ": Timeout for Buffer Read Ready interrupt, back to fixed sampling clock\n");
 310                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 311                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 312                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
 313                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 314
 315                         err = -EIO;
 316                         goto out;
 317                 }
 318
 319                 host->tuning_done = 0;
 320
 321                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 322
 323                 /* eMMC spec does not require a delay between tuning cycles */
 324                 if (opcode == MMC_SEND_TUNING_BLOCK)
 325                         mdelay(1);
 326         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 327
 328         /*
 329          * The Host Driver has exhausted the maximum number of loops allowed,
 330          * so use fixed sampling frequency.
 331          */
 332         if (tuning_loop_counter < 0) {
 333                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 334                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 335         }
 336         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 337                 dev_warn(mmc_dev(host->mmc),
 338                          ": Tuning failed, back to fixed sampling clock\n");
 339                 err = -EIO;
 340         } else {
 341                 arasan_zynqmp_dll_reset(host, sdhci_arasan->device_id);
 342         }
 343
 344 out:
 345         /*
 346          * In case tuning fails, host controllers which support
 347          * re-tuning can try tuning again at a later time, when the
 348          * re-tuning timer expires.  So for these controllers, we
 349          * return 0. Since there might be other controllers who do not
 350          * have this capability, we return error for them.
 351          */
 352         if (tuning_count)
 353                 err = 0;
 354
 355         host->mmc->retune_period = err ? 0 : tuning_count;
 356
 357         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 358         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 359         spin_unlock_irqrestore(&host->lock, flags);
 360
 361         return err;
 362 }
 363
 364 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
 365 {
 366         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 367         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 368         bool ctrl_phy = false;
 369
 370         if (!IS_ERR(sdhci_arasan->phy)) {
 371                 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
 372                         /*
 373                          * If PHY off, set clock to max speed and power PHY on.
 374                          *
 375                          * Although PHY docs apparently suggest power cycling
 376                          * when changing the clock the PHY doesn't like to be
 377                          * powered on while at low speeds like those used in ID
 378                          * mode.  Even worse is powering the PHY on while the
 379                          * clock is off.
 380                          *
 381                          * To workaround the PHY limitations, the best we can
 382                          * do is to power it on at a faster speed and then slam
 383                          * through low speeds without power cycling.
 384                          */
 385                         sdhci_set_clock(host, host->max_clk);
 386                         phy_power_on(sdhci_arasan->phy);
 387                         sdhci_arasan->is_phy_on = true;
 388
 389                         /*
 390                          * We'll now fall through to the below case with
 391                          * ctrl_phy = false (so we won't turn off/on).  The
 392                          * sdhci_set_clock() will set the real clock.
 393                          */
 394                 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
 395                         /*
 396                          * At higher clock speeds the PHY is fine being power
 397                          * cycled and docs say you _should_ power cycle when
 398                          * changing clock speeds.
 399                          */
 400                         ctrl_phy = true;
 401                 }
 402         }
 403
 404         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN) &&
 405                 (host->version >= SDHCI_SPEC_300)) {
 406                 if (clock == SD_CLK_25_MHZ)
 407                         clock = SD_CLK_19_MHZ;
 408                 if ((host->timing != MMC_TIMING_LEGACY) &&
 409                         (host->timing != MMC_TIMING_UHS_SDR12))
 410                         arasan_zynqmp_set_tap_delay(sdhci_arasan->device_id,
 411                                                     host->timing,
 412                                                     sdhci_arasan->mio_bank);
 413         }
 414
 415         if (ctrl_phy && sdhci_arasan->is_phy_on) {
 416                 phy_power_off(sdhci_arasan->phy);
 417                 sdhci_arasan->is_phy_on = false;
 418         }
 419
 420         sdhci_set_clock(host, clock);
 421
 422         if (ctrl_phy) {
 423                 phy_power_on(sdhci_arasan->phy);
 424                 sdhci_arasan->is_phy_on = true;
 425         }
 426 }
 427
 428 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
 429                                         struct mmc_ios *ios)
 430 {
 431         u32 vendor;
 432         struct sdhci_host *host = mmc_priv(mmc);
 433
 434         vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
 435         if (ios->enhanced_strobe)
 436                 vendor |= VENDOR_ENHANCED_STROBE;
 437         else
 438                 vendor &= ~VENDOR_ENHANCED_STROBE;
 439
 440         sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
 441 }
 442
 443 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
 444 {
 445         u8 ctrl;
 446         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 447         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 448
 449         sdhci_reset(host, mask);
 450
 451         if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
 452                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 453                 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
 454                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 455         }
 456 }
 457
 458 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
 459                                        struct mmc_ios *ios)
 460 {
 461         switch (ios->signal_voltage) {
 462         case MMC_SIGNAL_VOLTAGE_180:
 463                 /*
 464                  * Plese don't switch to 1V8 as arasan,5.1 doesn't
 465                  * actually refer to this setting to indicate the
 466                  * signal voltage and the state machine will be broken
 467                  * actually if we force to enable 1V8. That's something
 468                  * like broken quirk but we could work around here.
 469                  */
 470                 return 0;
 471         case MMC_SIGNAL_VOLTAGE_330:
 472         case MMC_SIGNAL_VOLTAGE_120:
 473                 /* We don't support 3V3 and 1V2 */
 474                 break;
 475         }
 476
 477         return -EINVAL;
 478 }
 479
 480 static struct sdhci_ops sdhci_arasan_ops = {
 481         .set_clock = sdhci_arasan_set_clock,
 482         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 483         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 484         .set_bus_width = sdhci_set_bus_width,
 485         .reset = sdhci_arasan_reset,
 486         .set_uhs_signaling = sdhci_set_uhs_signaling,
 487 };
 488
 489 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
 490         .ops = &sdhci_arasan_ops,
 491         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 492         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 493                         SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
 494 };
 495
 496 #ifdef CONFIG_PM
 497 /**
 498  * sdhci_arasan_runtime_suspend - Suspend method for the driver
 499  * @dev:        Address of the device structure
 500  * Put the device in a low power state.
 501  *
 502  * Return: 0 on success and error value on error
 503  */
 504 static int sdhci_arasan_runtime_suspend(struct device *dev)
 505 {
 506         struct platform_device *pdev = to_platform_device(dev);
 507         struct sdhci_host *host = platform_get_drvdata(pdev);
 508         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 509         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 510         int ret;
 511
 512         ret = sdhci_runtime_suspend_host(host);
 513         if (ret)
 514                 return ret;
 515
 516         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 517                 mmc_retune_needed(host->mmc);
 518
 519         clk_disable(pltfm_host->clk);
 520         clk_disable(sdhci_arasan->clk_ahb);
 521
 522         return 0;
 523 }
 524
 525 /**
 526  * sdhci_arasan_runtime_resume - Resume method for the driver
 527  * @dev:        Address of the device structure
 528  * Resume operation after suspend
 529  *
 530  * Return: 0 on success and error value on error
 531  */
 532 static int sdhci_arasan_runtime_resume(struct device *dev)
 533 {
 534         struct platform_device *pdev = to_platform_device(dev);
 535         struct sdhci_host *host = platform_get_drvdata(pdev);
 536         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 537         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 538         int ret;
 539
 540         ret = clk_enable(sdhci_arasan->clk_ahb);
 541         if (ret) {
 542                 dev_err(dev, "Cannot enable AHB clock.\n");
 543                 return ret;
 544         }
 545
 546         ret = clk_enable(pltfm_host->clk);
 547         if (ret) {
 548                 dev_err(dev, "Cannot enable SD clock.\n");
 549                 return ret;
 550         }
 551
 552         ret = sdhci_runtime_resume_host(host);
 553         if (ret)
 554                 goto out;
 555
 556         return 0;
 557 out:
 558         clk_disable(pltfm_host->clk);
 559         clk_disable(sdhci_arasan->clk_ahb);
 560
 561         return ret;
 562 }
 563 #endif /* ! CONFIG_PM */
 564
 565 #ifdef CONFIG_PM_SLEEP
 566 /**
 567  * sdhci_arasan_suspend - Suspend method for the driver
 568  * @dev:        Address of the device structure
 569  * Returns 0 on success and error value on error
 570  *
 571  * Put the device in a low power state.
 572  */
 573 static int sdhci_arasan_suspend(struct device *dev)
 574 {
 575         struct platform_device *pdev = to_platform_device(dev);
 576         struct sdhci_host *host = platform_get_drvdata(pdev);
 577         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 578         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 579         int ret;
 580
 581         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 582                 mmc_retune_needed(host->mmc);
 583
 584         ret = sdhci_suspend_host(host);
 585         if (ret)
 586                 return ret;
 587
 588         if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
 589                 ret = phy_power_off(sdhci_arasan->phy);
 590                 if (ret) {
 591                         dev_err(dev, "Cannot power off phy.\n");
 592                         sdhci_resume_host(host);
 593                         return ret;
 594                 }
 595                 sdhci_arasan->is_phy_on = false;
 596         }
 597
 598         clk_disable(pltfm_host->clk);
 599         clk_disable(sdhci_arasan->clk_ahb);
 600
 601         return 0;
 602 }
 603
 604 /**
 605  * sdhci_arasan_resume - Resume method for the driver
 606  * @dev:        Address of the device structure
 607  * Returns 0 on success and error value on error
 608  *
 609  * Resume operation after suspend
 610  */
 611 static int sdhci_arasan_resume(struct device *dev)
 612 {
 613         struct platform_device *pdev = to_platform_device(dev);
 614         struct sdhci_host *host = platform_get_drvdata(pdev);
 615         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 616         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 617         int ret;
 618
 619         ret = clk_enable(sdhci_arasan->clk_ahb);
 620         if (ret) {
 621                 dev_err(dev, "Cannot enable AHB clock.\n");
 622                 return ret;
 623         }
 624
 625         ret = clk_enable(pltfm_host->clk);
 626         if (ret) {
 627                 dev_err(dev, "Cannot enable SD clock.\n");
 628                 return ret;
 629         }
 630
 631         if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
 632                 ret = phy_power_on(sdhci_arasan->phy);
 633                 if (ret) {
 634                         dev_err(dev, "Cannot power on phy.\n");
 635                         return ret;
 636                 }
 637                 sdhci_arasan->is_phy_on = true;
 638         }
 639
 640         return sdhci_resume_host(host);
 641 }
 642 #endif /* ! CONFIG_PM_SLEEP */
 643
 644 static const struct dev_pm_ops sdhci_arasan_dev_pm_ops = {
 645         SET_SYSTEM_SLEEP_PM_OPS(sdhci_arasan_suspend, sdhci_arasan_resume)
 646         SET_RUNTIME_PM_OPS(sdhci_arasan_runtime_suspend,
 647                            sdhci_arasan_runtime_resume, NULL)
 648 };
 649
 650 static const struct of_device_id sdhci_arasan_of_match[] = {
 651         /* SoC-specific compatible strings w/ soc_ctl_map */
 652         {
 653                 .compatible = "rockchip,rk3399-sdhci-5.1",
 654                 .data = &rk3399_soc_ctl_map,
 655         },
 656
 657         /* Generic compatible below here */
 658         { .compatible = "arasan,sdhci-8.9a" },
 659         { .compatible = "arasan,sdhci-5.1" },
 660         { .compatible = "arasan,sdhci-4.9a" },
 661         { .compatible = "xlnx,zynqmp-8.9a" },
 662
 663         { /* sentinel */ }
 664 };
 665 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
 666
 667 /**
 668  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
 669  *
 670  * Return the current actual rate of the SD card clock.  This can be used
 671  * to communicate with out PHY.
 672  *
 673  * @hw:                 Pointer to the hardware clock structure.
 674  * @parent_rate         The parent rate (should be rate of clk_xin).
 675  * Returns the card clock rate.
 676  */
 677 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
 678                                                       unsigned long parent_rate)
 679
 680 {
 681         struct sdhci_arasan_data *sdhci_arasan =
 682                 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
 683         struct sdhci_host *host = sdhci_arasan->host;
 684
 685         return host->mmc->actual_clock;
 686 }
 687
 688 static const struct clk_ops arasan_sdcardclk_ops = {
 689         .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
 690 };
 691
 692 /**
 693  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
 694  *
 695  * The corecfg_clockmultiplier is supposed to contain clock multiplier
 696  * value of programmable clock generator.
 697  *
 698  * NOTES:
 699  * - Many existing devices don't seem to do this and work fine.  To keep
 700  *   compatibility for old hardware where the device tree doesn't provide a
 701  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
 702  *   for this platform.
 703  * - The value of corecfg_clockmultiplier should sync with that of corresponding
 704  *   value reading from sdhci_capability_register. So this function is called
 705  *   once at probe time and never called again.
 706  *
 707  * @host:               The sdhci_host
 708  */
 709 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
 710                                                 u32 value)
 711 {
 712         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 713         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 714         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
 715                 sdhci_arasan->soc_ctl_map;
 716
 717         /* Having a map is optional */
 718         if (!soc_ctl_map)
 719                 return;
 720
 721         /* If we have a map, we expect to have a syscon */
 722         if (!sdhci_arasan->soc_ctl_base) {
 723                 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
 724                         mmc_hostname(host->mmc));
 725                 return;
 726         }
 727
 728         sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
 729 }
 730
 731 /**
 732  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
 733  *
 734  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
 735  * function can be used to make that happen.
 736  *
 737  * NOTES:
 738  * - Many existing devices don't seem to do this and work fine.  To keep
 739  *   compatibility for old hardware where the device tree doesn't provide a
 740  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
 741  *   for this platform.
 742  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
 743  *   to achieve lower clock rates.  That means that this function is called once
 744  *   at probe time and never called again.
 745  *
 746  * @host:               The sdhci_host
 747  */
 748 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
 749 {
 750         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 751         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 752         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
 753                 sdhci_arasan->soc_ctl_map;
 754         u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
 755
 756         /* Having a map is optional */
 757         if (!soc_ctl_map)
 758                 return;
 759
 760         /* If we have a map, we expect to have a syscon */
 761         if (!sdhci_arasan->soc_ctl_base) {
 762                 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
 763                         mmc_hostname(host->mmc));
 764                 return;
 765         }
 766
 767         sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
 768 }
 769
 770 /**
 771  * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
 772  *
 773  * Some PHY devices need to know what the actual card clock is.  In order for
 774  * them to find out, we'll provide a clock through the common clock framework
 775  * for them to query.
 776  *
 777  * Note: without seriously re-architecting SDHCI's clock code and testing on
 778  * all platforms, there's no way to create a totally beautiful clock here
 779  * with all clock ops implemented.  Instead, we'll just create a clock that can
 780  * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
 781  * framework that we're doing things behind its back.  This should be sufficient
 782  * to create nice clean device tree bindings and later (if needed) we can try
 783  * re-architecting SDHCI if we see some benefit to it.
 784  *
 785  * @sdhci_arasan:       Our private data structure.
 786  * @clk_xin:            Pointer to the functional clock
 787  * @dev:                Pointer to our struct device.
 788  * Returns 0 on success and error value on error
 789  */
 790 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
 791                                        struct clk *clk_xin,
 792                                        struct device *dev)
 793 {
 794         struct device_node *np = dev->of_node;
 795         struct clk_init_data sdcardclk_init;
 796         const char *parent_clk_name;
 797         int ret;
 798
 799         /* Providing a clock to the PHY is optional; no error if missing */
 800         if (!of_find_property(np, "#clock-cells", NULL))
 801                 return 0;
 802
 803         ret = of_property_read_string_index(np, "clock-output-names", 0,
 804                                             &sdcardclk_init.name);
 805         if (ret) {
 806                 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
 807                 return ret;
 808         }
 809
 810         parent_clk_name = __clk_get_name(clk_xin);
 811         sdcardclk_init.parent_names = &parent_clk_name;
 812         sdcardclk_init.num_parents = 1;
 813         sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
 814         sdcardclk_init.ops = &arasan_sdcardclk_ops;
 815
 816         sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
 817         sdhci_arasan->sdcardclk =
 818                 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
 819         sdhci_arasan->sdcardclk_hw.init = NULL;
 820
 821         ret = of_clk_add_provider(np, of_clk_src_simple_get,
 822                                   sdhci_arasan->sdcardclk);
 823         if (ret)
 824                 dev_err(dev, "Failed to add clock provider\n");
 825
 826         return ret;
 827 }
 828
 829 /**
 830  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
 831  *
 832  * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
 833  * returned success.
 834  *
 835  * @dev:                Pointer to our struct device.
 836  */
 837 static void sdhci_arasan_unregister_sdclk(struct device *dev)
 838 {
 839         struct device_node *np = dev->of_node;
 840
 841         if (!of_find_property(np, "#clock-cells", NULL))
 842                 return;
 843
 844         of_clk_del_provider(dev->of_node);
 845 }
 846
 847 static int sdhci_arasan_probe(struct platform_device *pdev)
 848 {
 849         int ret;
 850         const struct of_device_id *match;
 851         struct device_node *node;
 852         struct clk *clk_xin;
 853         struct sdhci_host *host;
 854         struct sdhci_pltfm_host *pltfm_host;
 855         struct sdhci_arasan_data *sdhci_arasan;
 856         struct device_node *np = pdev->dev.of_node;
 857         unsigned int host_quirks2 = 0;
 858
 859         if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a")) {
 860                 char *soc_rev;
 861
 862                 /* read Silicon version using nvmem driver */
 863                 soc_rev = zynqmp_nvmem_get_silicon_version(&pdev->dev,
 864                                                            "soc_revision");
 865                 if (PTR_ERR(soc_rev) == -EPROBE_DEFER)
 866                         /* Do a deferred probe */
 867                         return -EPROBE_DEFER;
 868                 else if (IS_ERR(soc_rev))
 869                         dev_dbg(&pdev->dev, "Error getting silicon version\n");
 870
 871                 /* Set host quirk if the silicon version is v1.0 */
 872                 if (!IS_ERR(soc_rev) && (*soc_rev == ZYNQMP_SILICON_V1))
 873                         host_quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
 874
 875                 /* Clean soc_rev if got a valid pointer from nvmem driver
 876                  * else we may end up in kernel panic
 877                  */
 878                 if (!IS_ERR(soc_rev))
 879                         kfree(soc_rev);
 880         }
 881
 882         host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
 883                                 sizeof(*sdhci_arasan));
 884         if (IS_ERR(host))
 885                 return PTR_ERR(host);
 886
 887         pltfm_host = sdhci_priv(host);
 888         sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 889         sdhci_arasan->host = host;
 890
 891         match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
 892         sdhci_arasan->soc_ctl_map = match->data;
 893
 894         host->quirks2 |= host_quirks2;
 895
 896         node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
 897         if (node) {
 898                 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
 899                 of_node_put(node);
 900
 901                 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
 902                         ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
 903                         if (ret != -EPROBE_DEFER)
 904                                 dev_err(&pdev->dev, "Can't get syscon: %d\n",
 905                                         ret);
 906                         goto err_pltfm_free;
 907                 }
 908         }
 909
 910         sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
 911         if (IS_ERR(sdhci_arasan->clk_ahb)) {
 912                 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
 913                 ret = PTR_ERR(sdhci_arasan->clk_ahb);
 914                 goto err_pltfm_free;
 915         }
 916
 917         clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
 918         if (IS_ERR(clk_xin)) {
 919                 dev_err(&pdev->dev, "clk_xin clock not found.\n");
 920                 ret = PTR_ERR(clk_xin);
 921                 goto err_pltfm_free;
 922         }
 923
 924         ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
 925         if (ret) {
 926                 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
 927                 goto err_pltfm_free;
 928         }
 929
 930         ret = clk_prepare_enable(clk_xin);
 931         if (ret) {
 932                 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
 933                 goto clk_dis_ahb;
 934         }
 935
 936         sdhci_get_of_property(pdev);
 937
 938         if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
 939                 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
 940
 941         pltfm_host->clk = clk_xin;
 942
 943         if (of_device_is_compatible(pdev->dev.of_node,
 944                                     "rockchip,rk3399-sdhci-5.1"))
 945                 sdhci_arasan_update_clockmultiplier(host, 0x0);
 946
 947         sdhci_arasan_update_baseclkfreq(host);
 948
 949         ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
 950         if (ret)
 951                 goto clk_disable_all;
 952
 953         ret = mmc_of_parse(host->mmc);
 954         if (ret) {
 955                 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
 956                 goto unreg_clk;
 957         }
 958
 959         if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a") ||
 960                 of_device_is_compatible(pdev->dev.of_node,
 961                                         "arasan,sdhci-8.9a")) {
 962                 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 963                 host->quirks2 |= SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN;
 964                 if (of_device_is_compatible(pdev->dev.of_node,
 965                                             "xlnx,zynqmp-8.9a")) {
 966                         ret = of_property_read_u32(pdev->dev.of_node,
 967                                                    "xlnx,mio_bank",
 968                                                    &sdhci_arasan->mio_bank);
 969                         if (ret < 0) {
 970                                 dev_err(&pdev->dev,
 971                                         "\"xlnx,mio_bank \" property is missing.\n");
 972                                 goto clk_disable_all;
 973                         }
 974                         ret = of_property_read_u32(pdev->dev.of_node,
 975                                                    "xlnx,device_id",
 976                                                    &sdhci_arasan->device_id);
 977                         if (ret < 0) {
 978                                 dev_err(&pdev->dev,
 979                                         "\"xlnx,device_id \" property is missing.\n");
 980                                 goto clk_disable_all;
 981                         }
 982                         sdhci_arasan_ops.platform_execute_tuning =
 983                                 arasan_zynqmp_execute_tuning;
 984                 }
 985         }
 986
 987         sdhci_arasan->pinctrl = devm_pinctrl_get(&pdev->dev);
 988         if (!IS_ERR(sdhci_arasan->pinctrl)) {
 989                 sdhci_arasan->pins_default = pinctrl_lookup_state(
 990                                                         sdhci_arasan->pinctrl,
 991                                                         PINCTRL_STATE_DEFAULT);
 992                 if (IS_ERR(sdhci_arasan->pins_default)) {
 993                         dev_err(&pdev->dev, "Missing default pinctrl config\n");
 994                         return IS_ERR(sdhci_arasan->pins_default);
 995                 }
 996
 997                 pinctrl_select_state(sdhci_arasan->pinctrl,
 998                                      sdhci_arasan->pins_default);
 999         }
1000
1001         sdhci_arasan->phy = ERR_PTR(-ENODEV);
1002         if (of_device_is_compatible(pdev->dev.of_node,
1003                                     "arasan,sdhci-5.1")) {
1004                 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
1005                                                  "phy_arasan");
1006                 if (IS_ERR(sdhci_arasan->phy)) {
1007                         ret = PTR_ERR(sdhci_arasan->phy);
1008                         dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
1009                         goto unreg_clk;
1010                 }
1011
1012                 ret = phy_init(sdhci_arasan->phy);
1013                 if (ret < 0) {
1014                         dev_err(&pdev->dev, "phy_init err.\n");
1015                         goto unreg_clk;
1016                 }
1017
1018                 host->mmc_host_ops.hs400_enhanced_strobe =
1019                                         sdhci_arasan_hs400_enhanced_strobe;
1020                 host->mmc_host_ops.start_signal_voltage_switch =
1021                                         sdhci_arasan_voltage_switch;
1022         }
1023
1024         ret = sdhci_add_host(host);
1025         if (ret)
1026                 goto err_add_host;
1027
1028         pm_runtime_set_active(&pdev->dev);
1029         pm_runtime_enable(&pdev->dev);
1030         pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1031         pm_runtime_mark_last_busy(&pdev->dev);
1032         pm_runtime_use_autosuspend(&pdev->dev);
1033         pm_runtime_forbid(&pdev->dev);
1034
1035         return 0;
1036
1037 err_add_host:
1038         if (!IS_ERR(sdhci_arasan->phy))
1039                 phy_exit(sdhci_arasan->phy);
1040 unreg_clk:
1041         sdhci_arasan_unregister_sdclk(&pdev->dev);
1042 clk_disable_all:
1043         clk_disable_unprepare(clk_xin);
1044 clk_dis_ahb:
1045         clk_disable_unprepare(sdhci_arasan->clk_ahb);
1046 err_pltfm_free:
1047         sdhci_pltfm_free(pdev);
1048         return ret;
1049 }
1050
1051 static int sdhci_arasan_remove(struct platform_device *pdev)
1052 {
1053         int ret;
1054         struct sdhci_host *host = platform_get_drvdata(pdev);
1055         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1056         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1057         struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1058
1059         if (!IS_ERR(sdhci_arasan->phy)) {
1060                 if (sdhci_arasan->is_phy_on)
1061                         phy_power_off(sdhci_arasan->phy);
1062                 phy_exit(sdhci_arasan->phy);
1063         }
1064
1065         sdhci_arasan_unregister_sdclk(&pdev->dev);
1066
1067         ret = sdhci_pltfm_unregister(pdev);
1068
1069         clk_disable_unprepare(clk_ahb);
1070
1071         return ret;
1072 }
1073
1074 static struct platform_driver sdhci_arasan_driver = {
1075         .driver = {
1076                 .name = "sdhci-arasan",
1077                 .of_match_table = sdhci_arasan_of_match,
1078                 .pm = &sdhci_arasan_dev_pm_ops,
1079         },
1080         .probe = sdhci_arasan_probe,
1081         .remove = sdhci_arasan_remove,
1082 };
1083
1084 module_platform_driver(sdhci_arasan_driver);
1085
1086 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1087 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1088 MODULE_LICENSE("GPL");