include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2018 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15
  16 #include <linux/device.h>
  17
  18 #define ZYNQMP_PM_VERSION_MAJOR 1
  19 #define ZYNQMP_PM_VERSION_MINOR 0
  20
  21 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  22                                         ZYNQMP_PM_VERSION_MINOR)
  23
  24 #define ZYNQMP_TZ_VERSION_MAJOR 1
  25 #define ZYNQMP_TZ_VERSION_MINOR 0
  26
  27 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  28                                         ZYNQMP_TZ_VERSION_MINOR)
  29
  30 /* SMC SIP service Call Function Identifier Prefix */
  31 #define PM_SIP_SVC                      0xC2000000
  32 #define PM_GET_TRUSTZONE_VERSION        0xa03
  33 #define PM_SET_SUSPEND_MODE             0xa02
  34 #define GET_CALLBACK_DATA               0xa01
  35
  36 /* Number of 32bits values in payload */
  37 #define PAYLOAD_ARG_CNT 4U
  38
  39 /* Number of arguments for a callback */
  40 #define CB_ARG_CNT      4
  41
  42 /* Payload size (consists of callback API ID + arguments) */
  43 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  44
  45 #define ZYNQMP_PM_MAX_LATENCY   (~0U)
  46 #define ZYNQMP_PM_MAX_QOS       100U
  47
  48 /* Usage status, returned by PmGetNodeStatus */
  49 #define PM_USAGE_NO_MASTER                      0x0U
  50 #define PM_USAGE_CURRENT_MASTER                 0x1U
  51 #define PM_USAGE_OTHER_MASTER                   0x2U
  52 #define PM_USAGE_BOTH_MASTERS                   (PM_USAGE_CURRENT_MASTER | \
  53                                                  PM_USAGE_OTHER_MASTER)
  54
  55 #define GSS_NUM_REGS    (4)
  56
  57 /* Node capabilities */
  58 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  59 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  60 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  61 #define ZYNQMP_PM_CAPABILITY_POWER      0x8U
  62
  63 /* Feature check status */
  64 #define PM_FEATURE_INVALID              -1
  65 #define PM_FEATURE_UNCHECKED            0
  66
  67 enum pm_api_id {
  68         PM_GET_API_VERSION = 1,
  69         PM_SET_CONFIGURATION,
  70         PM_GET_NODE_STATUS,
  71         PM_GET_OPERATING_CHARACTERISTIC,
  72         PM_REGISTER_NOTIFIER,
  73         /* API for suspending of PUs: */
  74         PM_REQUEST_SUSPEND,
  75         PM_SELF_SUSPEND,
  76         PM_FORCE_POWERDOWN,
  77         PM_ABORT_SUSPEND,
  78         PM_REQUEST_WAKEUP,
  79         PM_SET_WAKEUP_SOURCE,
  80         PM_SYSTEM_SHUTDOWN,
  81         /* API for managing PM slaves: */
  82         PM_REQUEST_NODE,
  83         PM_RELEASE_NODE,
  84         PM_SET_REQUIREMENT,
  85         PM_SET_MAX_LATENCY,
  86         /* Direct control API functions: */
  87         PM_RESET_ASSERT,
  88         PM_RESET_GET_STATUS,
  89         PM_MMIO_WRITE,
  90         PM_MMIO_READ,
  91         PM_PM_INIT_FINALIZE,
  92         PM_FPGA_LOAD,
  93         PM_FPGA_GET_STATUS,
  94         PM_GET_CHIPID,
  95         /* ID 25 is been used by U-boot to process secure boot images */
  96         /* Secure library generic API functions */
  97         PM_SECURE_SHA = 26,
  98         PM_SECURE_RSA,
  99         /* Pin control API functions */
 100         PM_PINCTRL_REQUEST,
 101         PM_PINCTRL_RELEASE,
 102         PM_PINCTRL_GET_FUNCTION,
 103         PM_PINCTRL_SET_FUNCTION,
 104         PM_PINCTRL_CONFIG_PARAM_GET,
 105         PM_PINCTRL_CONFIG_PARAM_SET,
 106         /* PM IOCTL API */
 107         PM_IOCTL,
 108         /* API to query information from firmware */
 109         PM_QUERY_DATA,
 110         /* Clock control API functions */
 111         PM_CLOCK_ENABLE,
 112         PM_CLOCK_DISABLE,
 113         PM_CLOCK_GETSTATE,
 114         PM_CLOCK_SETDIVIDER,
 115         PM_CLOCK_GETDIVIDER,
 116         PM_CLOCK_SETRATE,
 117         PM_CLOCK_GETRATE,
 118         PM_CLOCK_SETPARENT,
 119         PM_CLOCK_GETPARENT,
 120         PM_SECURE_IMAGE,
 121         PM_FPGA_READ = 46,
 122         PM_SECURE_AES,
 123         /* PM_REGISTER_ACCESS API */
 124         PM_REGISTER_ACCESS = 52,
 125         PM_EFUSE_ACCESS,
 126         PM_FEATURE_CHECK = 63,
 127         PM_API_MAX,
 128 };
 129
 130 /* PMU-FW return status codes */
 131 enum pm_ret_status {
 132         XST_PM_SUCCESS = 0,
 133         XST_PM_NO_FEATURE = 19,
 134         XST_PM_INTERNAL = 2000,
 135         XST_PM_CONFLICT,
 136         XST_PM_NO_ACCESS,
 137         XST_PM_INVALID_NODE,
 138         XST_PM_DOUBLE_REQ,
 139         XST_PM_ABORT_SUSPEND,
 140 };
 141
 142 enum pm_ioctl_id {
 143         IOCTL_GET_RPU_OPER_MODE,
 144         IOCTL_SET_RPU_OPER_MODE,
 145         IOCTL_RPU_BOOT_ADDR_CONFIG,
 146         IOCTL_TCM_COMB_CONFIG,
 147         IOCTL_SET_TAPDELAY_BYPASS,
 148         IOCTL_SET_SGMII_MODE,
 149         IOCTL_SD_DLL_RESET,
 150         IOCTL_SET_SD_TAPDELAY,
 151         /* Ioctl for clock driver */
 152         IOCTL_SET_PLL_FRAC_MODE,
 153         IOCTL_GET_PLL_FRAC_MODE,
 154         IOCTL_SET_PLL_FRAC_DATA,
 155         IOCTL_GET_PLL_FRAC_DATA,
 156         IOCTL_WRITE_GGS,
 157         IOCTL_READ_GGS,
 158         IOCTL_WRITE_PGGS,
 159         IOCTL_READ_PGGS,
 160         /* IOCTL for ULPI reset */
 161         IOCTL_ULPI_RESET,
 162         /* Set healthy bit value*/
 163         IOCTL_SET_BOOT_HEALTH_STATUS,
 164         IOCTL_AFI,
 165 };
 166
 167 enum pm_query_id {
 168         PM_QID_INVALID,
 169         PM_QID_CLOCK_GET_NAME,
 170         PM_QID_CLOCK_GET_TOPOLOGY,
 171         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
 172         PM_QID_CLOCK_GET_PARENTS,
 173         PM_QID_CLOCK_GET_ATTRIBUTES,
 174         PM_QID_PINCTRL_GET_NUM_PINS,
 175         PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
 176         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
 177         PM_QID_PINCTRL_GET_FUNCTION_NAME,
 178         PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
 179         PM_QID_PINCTRL_GET_PIN_GROUPS,
 180         PM_QID_CLOCK_GET_NUM_CLOCKS,
 181 };
 182
 183 enum zynqmp_pm_reset_action {
 184         PM_RESET_ACTION_RELEASE,
 185         PM_RESET_ACTION_ASSERT,
 186         PM_RESET_ACTION_PULSE,
 187 };
 188
 189 enum zynqmp_pm_reset {
 190         ZYNQMP_PM_RESET_START = 1000,
 191         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 192         ZYNQMP_PM_RESET_PCIE_BRIDGE,
 193         ZYNQMP_PM_RESET_PCIE_CTRL,
 194         ZYNQMP_PM_RESET_DP,
 195         ZYNQMP_PM_RESET_SWDT_CRF,
 196         ZYNQMP_PM_RESET_AFI_FM5,
 197         ZYNQMP_PM_RESET_AFI_FM4,
 198         ZYNQMP_PM_RESET_AFI_FM3,
 199         ZYNQMP_PM_RESET_AFI_FM2,
 200         ZYNQMP_PM_RESET_AFI_FM1,
 201         ZYNQMP_PM_RESET_AFI_FM0,
 202         ZYNQMP_PM_RESET_GDMA,
 203         ZYNQMP_PM_RESET_GPU_PP1,
 204         ZYNQMP_PM_RESET_GPU_PP0,
 205         ZYNQMP_PM_RESET_GPU,
 206         ZYNQMP_PM_RESET_GT,
 207         ZYNQMP_PM_RESET_SATA,
 208         ZYNQMP_PM_RESET_ACPU3_PWRON,
 209         ZYNQMP_PM_RESET_ACPU2_PWRON,
 210         ZYNQMP_PM_RESET_ACPU1_PWRON,
 211         ZYNQMP_PM_RESET_ACPU0_PWRON,
 212         ZYNQMP_PM_RESET_APU_L2,
 213         ZYNQMP_PM_RESET_ACPU3,
 214         ZYNQMP_PM_RESET_ACPU2,
 215         ZYNQMP_PM_RESET_ACPU1,
 216         ZYNQMP_PM_RESET_ACPU0,
 217         ZYNQMP_PM_RESET_DDR,
 218         ZYNQMP_PM_RESET_APM_FPD,
 219         ZYNQMP_PM_RESET_SOFT,
 220         ZYNQMP_PM_RESET_GEM0,
 221         ZYNQMP_PM_RESET_GEM1,
 222         ZYNQMP_PM_RESET_GEM2,
 223         ZYNQMP_PM_RESET_GEM3,
 224         ZYNQMP_PM_RESET_QSPI,
 225         ZYNQMP_PM_RESET_UART0,
 226         ZYNQMP_PM_RESET_UART1,
 227         ZYNQMP_PM_RESET_SPI0,
 228         ZYNQMP_PM_RESET_SPI1,
 229         ZYNQMP_PM_RESET_SDIO0,
 230         ZYNQMP_PM_RESET_SDIO1,
 231         ZYNQMP_PM_RESET_CAN0,
 232         ZYNQMP_PM_RESET_CAN1,
 233         ZYNQMP_PM_RESET_I2C0,
 234         ZYNQMP_PM_RESET_I2C1,
 235         ZYNQMP_PM_RESET_TTC0,
 236         ZYNQMP_PM_RESET_TTC1,
 237         ZYNQMP_PM_RESET_TTC2,
 238         ZYNQMP_PM_RESET_TTC3,
 239         ZYNQMP_PM_RESET_SWDT_CRL,
 240         ZYNQMP_PM_RESET_NAND,
 241         ZYNQMP_PM_RESET_ADMA,
 242         ZYNQMP_PM_RESET_GPIO,
 243         ZYNQMP_PM_RESET_IOU_CC,
 244         ZYNQMP_PM_RESET_TIMESTAMP,
 245         ZYNQMP_PM_RESET_RPU_R50,
 246         ZYNQMP_PM_RESET_RPU_R51,
 247         ZYNQMP_PM_RESET_RPU_AMBA,
 248         ZYNQMP_PM_RESET_OCM,
 249         ZYNQMP_PM_RESET_RPU_PGE,
 250         ZYNQMP_PM_RESET_USB0_CORERESET,
 251         ZYNQMP_PM_RESET_USB1_CORERESET,
 252         ZYNQMP_PM_RESET_USB0_HIBERRESET,
 253         ZYNQMP_PM_RESET_USB1_HIBERRESET,
 254         ZYNQMP_PM_RESET_USB0_APB,
 255         ZYNQMP_PM_RESET_USB1_APB,
 256         ZYNQMP_PM_RESET_IPI,
 257         ZYNQMP_PM_RESET_APM_LPD,
 258         ZYNQMP_PM_RESET_RTC,
 259         ZYNQMP_PM_RESET_SYSMON,
 260         ZYNQMP_PM_RESET_AFI_FM6,
 261         ZYNQMP_PM_RESET_LPD_SWDT,
 262         ZYNQMP_PM_RESET_FPD,
 263         ZYNQMP_PM_RESET_RPU_DBG1,
 264         ZYNQMP_PM_RESET_RPU_DBG0,
 265         ZYNQMP_PM_RESET_DBG_LPD,
 266         ZYNQMP_PM_RESET_DBG_FPD,
 267         ZYNQMP_PM_RESET_APLL,
 268         ZYNQMP_PM_RESET_DPLL,
 269         ZYNQMP_PM_RESET_VPLL,
 270         ZYNQMP_PM_RESET_IOPLL,
 271         ZYNQMP_PM_RESET_RPLL,
 272         ZYNQMP_PM_RESET_GPO3_PL_0,
 273         ZYNQMP_PM_RESET_GPO3_PL_1,
 274         ZYNQMP_PM_RESET_GPO3_PL_2,
 275         ZYNQMP_PM_RESET_GPO3_PL_3,
 276         ZYNQMP_PM_RESET_GPO3_PL_4,
 277         ZYNQMP_PM_RESET_GPO3_PL_5,
 278         ZYNQMP_PM_RESET_GPO3_PL_6,
 279         ZYNQMP_PM_RESET_GPO3_PL_7,
 280         ZYNQMP_PM_RESET_GPO3_PL_8,
 281         ZYNQMP_PM_RESET_GPO3_PL_9,
 282         ZYNQMP_PM_RESET_GPO3_PL_10,
 283         ZYNQMP_PM_RESET_GPO3_PL_11,
 284         ZYNQMP_PM_RESET_GPO3_PL_12,
 285         ZYNQMP_PM_RESET_GPO3_PL_13,
 286         ZYNQMP_PM_RESET_GPO3_PL_14,
 287         ZYNQMP_PM_RESET_GPO3_PL_15,
 288         ZYNQMP_PM_RESET_GPO3_PL_16,
 289         ZYNQMP_PM_RESET_GPO3_PL_17,
 290         ZYNQMP_PM_RESET_GPO3_PL_18,
 291         ZYNQMP_PM_RESET_GPO3_PL_19,
 292         ZYNQMP_PM_RESET_GPO3_PL_20,
 293         ZYNQMP_PM_RESET_GPO3_PL_21,
 294         ZYNQMP_PM_RESET_GPO3_PL_22,
 295         ZYNQMP_PM_RESET_GPO3_PL_23,
 296         ZYNQMP_PM_RESET_GPO3_PL_24,
 297         ZYNQMP_PM_RESET_GPO3_PL_25,
 298         ZYNQMP_PM_RESET_GPO3_PL_26,
 299         ZYNQMP_PM_RESET_GPO3_PL_27,
 300         ZYNQMP_PM_RESET_GPO3_PL_28,
 301         ZYNQMP_PM_RESET_GPO3_PL_29,
 302         ZYNQMP_PM_RESET_GPO3_PL_30,
 303         ZYNQMP_PM_RESET_GPO3_PL_31,
 304         ZYNQMP_PM_RESET_RPU_LS,
 305         ZYNQMP_PM_RESET_PS_ONLY,
 306         ZYNQMP_PM_RESET_PL,
 307         ZYNQMP_PM_RESET_PS_PL0,
 308         ZYNQMP_PM_RESET_PS_PL1,
 309         ZYNQMP_PM_RESET_PS_PL2,
 310         ZYNQMP_PM_RESET_PS_PL3,
 311         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 312 };
 313
 314 enum zynqmp_pm_abort_reason {
 315         ZYNQMP_PM_ABORT_REASON_WAKEUP_EVENT = 100,
 316         ZYNQMP_PM_ABORT_REASON_POWER_UNIT_BUSY,
 317         ZYNQMP_PM_ABORT_REASON_NO_POWERDOWN,
 318         ZYNQMP_PM_ABORT_REASON_UNKNOWN,
 319 };
 320
 321 enum zynqmp_pm_suspend_reason {
 322         SUSPEND_POWER_REQUEST = 201,
 323         SUSPEND_ALERT,
 324         SUSPEND_SYSTEM_SHUTDOWN,
 325 };
 326
 327 enum zynqmp_pm_request_ack {
 328         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 329         ZYNQMP_PM_REQUEST_ACK_BLOCKING,
 330         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
 331 };
 332
 333 enum zynqmp_pm_opchar_type {
 334         ZYNQMP_PM_OPERATING_CHARACTERISTIC_POWER = 1,
 335         ZYNQMP_PM_OPERATING_CHARACTERISTIC_ENERGY,
 336         ZYNQMP_PM_OPERATING_CHARACTERISTIC_TEMPERATURE,
 337 };
 338
 339 enum zynqmp_pm_shutdown_type {
 340         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
 341         ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
 342         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
 343 };
 344
 345 enum zynqmp_pm_shutdown_subtype {
 346         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
 347         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
 348         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
 349 };
 350
 351 enum pm_node_id {
 352         NODE_UNKNOWN = 0,
 353         NODE_APU,
 354         NODE_APU_0,
 355         NODE_APU_1,
 356         NODE_APU_2,
 357         NODE_APU_3,
 358         NODE_RPU,
 359         NODE_RPU_0,
 360         NODE_RPU_1,
 361         NODE_PLD,
 362         NODE_FPD,
 363         NODE_OCM_BANK_0,
 364         NODE_OCM_BANK_1,
 365         NODE_OCM_BANK_2,
 366         NODE_OCM_BANK_3,
 367         NODE_TCM_0_A,
 368         NODE_TCM_0_B,
 369         NODE_TCM_1_A,
 370         NODE_TCM_1_B,
 371         NODE_L2,
 372         NODE_GPU_PP_0,
 373         NODE_GPU_PP_1,
 374         NODE_USB_0,
 375         NODE_USB_1,
 376         NODE_TTC_0,
 377         NODE_TTC_1,
 378         NODE_TTC_2,
 379         NODE_TTC_3,
 380         NODE_SATA,
 381         NODE_ETH_0,
 382         NODE_ETH_1,
 383         NODE_ETH_2,
 384         NODE_ETH_3,
 385         NODE_UART_0,
 386         NODE_UART_1,
 387         NODE_SPI_0,
 388         NODE_SPI_1,
 389         NODE_I2C_0,
 390         NODE_I2C_1,
 391         NODE_SD_0,
 392         NODE_SD_1,
 393         NODE_DP,
 394         NODE_GDMA,
 395         NODE_ADMA,
 396         NODE_NAND,
 397         NODE_QSPI,
 398         NODE_GPIO,
 399         NODE_CAN_0,
 400         NODE_CAN_1,
 401         NODE_EXTERN,
 402         NODE_APLL,
 403         NODE_VPLL,
 404         NODE_DPLL,
 405         NODE_RPLL,
 406         NODE_IOPLL,
 407         NODE_DDR,
 408         NODE_IPI_APU,
 409         NODE_IPI_RPU_0,
 410         NODE_GPU,
 411         NODE_PCIE,
 412         NODE_PCAP,
 413         NODE_RTC,
 414         NODE_LPD,
 415         NODE_VCU,
 416         NODE_IPI_RPU_1,
 417         NODE_IPI_PL_0,
 418         NODE_IPI_PL_1,
 419         NODE_IPI_PL_2,
 420         NODE_IPI_PL_3,
 421         NODE_PL,
 422         NODE_GEM_TSU,
 423         NODE_SWDT_0,
 424         NODE_SWDT_1,
 425         NODE_CSU,
 426         NODE_PJTAG,
 427         NODE_TRACE,
 428         NODE_TESTSCAN,
 429         NODE_PMU,
 430         NODE_MAX,
 431 };
 432
 433 enum pm_pinctrl_config_param {
 434         PM_PINCTRL_CONFIG_SLEW_RATE,
 435         PM_PINCTRL_CONFIG_BIAS_STATUS,
 436         PM_PINCTRL_CONFIG_PULL_CTRL,
 437         PM_PINCTRL_CONFIG_SCHMITT_CMOS,
 438         PM_PINCTRL_CONFIG_DRIVE_STRENGTH,
 439         PM_PINCTRL_CONFIG_VOLTAGE_STATUS,
 440         PM_PINCTRL_CONFIG_MAX,
 441 };
 442
 443 enum pm_pinctrl_slew_rate {
 444         PM_PINCTRL_SLEW_RATE_FAST,
 445         PM_PINCTRL_SLEW_RATE_SLOW,
 446 };
 447
 448 enum pm_pinctrl_bias_status {
 449         PM_PINCTRL_BIAS_DISABLE,
 450         PM_PINCTRL_BIAS_ENABLE,
 451 };
 452
 453 enum pm_pinctrl_pull_ctrl {
 454         PM_PINCTRL_BIAS_PULL_DOWN,
 455         PM_PINCTRL_BIAS_PULL_UP,
 456 };
 457
 458 enum pm_pinctrl_schmitt_cmos {
 459         PM_PINCTRL_INPUT_TYPE_CMOS,
 460         PM_PINCTRL_INPUT_TYPE_SCHMITT,
 461 };
 462
 463 enum pm_pinctrl_drive_strength {
 464         PM_PINCTRL_DRIVE_STRENGTH_2MA,
 465         PM_PINCTRL_DRIVE_STRENGTH_4MA,
 466         PM_PINCTRL_DRIVE_STRENGTH_8MA,
 467         PM_PINCTRL_DRIVE_STRENGTH_12MA,
 468 };
 469
 470 enum rpu_oper_mode {
 471         PM_RPU_MODE_LOCKSTEP,
 472         PM_RPU_MODE_SPLIT,
 473 };
 474
 475 enum rpu_boot_mem {
 476         PM_RPU_BOOTMEM_LOVEC,
 477         PM_RPU_BOOTMEM_HIVEC,
 478 };
 479
 480 enum rpu_tcm_comb {
 481         PM_RPU_TCM_SPLIT,
 482         PM_RPU_TCM_COMB,
 483 };
 484
 485 enum tap_delay_signal_type {
 486         PM_TAPDELAY_NAND_DQS_IN,
 487         PM_TAPDELAY_NAND_DQS_OUT,
 488         PM_TAPDELAY_QSPI,
 489         PM_TAPDELAY_MAX,
 490 };
 491
 492 enum tap_delay_bypass_ctrl {
 493         PM_TAPDELAY_BYPASS_DISABLE,
 494         PM_TAPDELAY_BYPASS_ENABLE,
 495 };
 496
 497 enum sgmii_mode {
 498         PM_SGMII_DISABLE,
 499         PM_SGMII_ENABLE,
 500 };
 501
 502 enum tap_delay_type {
 503         PM_TAPDELAY_INPUT,
 504         PM_TAPDELAY_OUTPUT,
 505 };
 506
 507 enum dll_reset_type {
 508         PM_DLL_RESET_ASSERT,
 509         PM_DLL_RESET_RELEASE,
 510         PM_DLL_RESET_PULSE,
 511 };
 512
 513 enum pm_register_access_id {
 514         CONFIG_REG_WRITE,
 515         CONFIG_REG_READ,
 516 };
 517
 518 /**
 519  * struct zynqmp_pm_query_data - PM query data
 520  * @qid:        query ID
 521  * @arg1:       Argument 1 of query data
 522  * @arg2:       Argument 2 of query data
 523  * @arg3:       Argument 3 of query data
 524  */
 525 struct zynqmp_pm_query_data {
 526         u32 qid;
 527         u32 arg1;
 528         u32 arg2;
 529         u32 arg3;
 530 };
 531
 532 struct zynqmp_eemi_ops {
 533         int (*get_api_version)(u32 *version);
 534         int (*get_chipid)(u32 *idcode, u32 *version);
 535         int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
 536         int (*clock_enable)(u32 clock_id);
 537         int (*clock_disable)(u32 clock_id);
 538         int (*clock_getstate)(u32 clock_id, u32 *state);
 539         int (*clock_setdivider)(u32 clock_id, u32 divider);
 540         int (*clock_getdivider)(u32 clock_id, u32 *divider);
 541         int (*clock_setrate)(u32 clock_id, u64 rate);
 542         int (*clock_getrate)(u32 clock_id, u64 *rate);
 543         int (*clock_setparent)(u32 clock_id, u32 parent_id);
 544         int (*clock_getparent)(u32 clock_id, u32 *parent_id);
 545         int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
 546         int (*reset_assert)(const enum zynqmp_pm_reset reset,
 547                             const enum zynqmp_pm_reset_action assert_flag);
 548         int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
 549         int (*init_finalize)(void);
 550         int (*set_suspend_mode)(u32 mode);
 551         int (*request_node)(const u32 node,
 552                             const u32 capabilities,
 553                             const u32 qos,
 554                             const enum zynqmp_pm_request_ack ack);
 555         int (*release_node)(const u32 node);
 556         int (*set_requirement)(const u32 node,
 557                                const u32 capabilities,
 558                                const u32 qos,
 559                                const enum zynqmp_pm_request_ack ack);
 560         int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
 561         int (*fpga_get_status)(u32 *value);
 562         int (*fpga_read)(const u32 reg_numframes, const u64 phys_address,
 563                          u32 readback_type, u32 *value);
 564         int (*sha_hash)(const u64 address, const u32 size, const u32 flags);
 565         int (*rsa)(const u64 address, const u32 size, const u32 flags);
 566         int (*request_suspend)(const u32 node,
 567                                const enum zynqmp_pm_request_ack ack,
 568                                const u32 latency,
 569                                const u32 state);
 570         int (*force_powerdown)(const u32 target,
 571                                const enum zynqmp_pm_request_ack ack);
 572         int (*request_wakeup)(const u32 node,
 573                               const bool set_addr,
 574                               const u64 address,
 575                               const enum zynqmp_pm_request_ack ack);
 576         int (*set_wakeup_source)(const u32 target,
 577                                  const u32 wakeup_node,
 578                                  const u32 enable);
 579         int (*system_shutdown)(const u32 type, const u32 subtype);
 580         int (*set_max_latency)(const u32 node, const u32 latency);
 581         int (*set_configuration)(const u32 physical_addr);
 582         int (*get_node_status)(const u32 node, u32 *const status,
 583                                u32 *const requirements, u32 *const usage);
 584         int (*get_operating_characteristic)(const u32 node,
 585                                             const enum zynqmp_pm_opchar_type
 586                                             type, u32 *const result);
 587         int (*pinctrl_request)(const u32 pin);
 588         int (*pinctrl_release)(const u32 pin);
 589         int (*pinctrl_get_function)(const u32 pin, u32 *id);
 590         int (*pinctrl_set_function)(const u32 pin, const u32 id);
 591         int (*pinctrl_get_config)(const u32 pin, const u32 param, u32 *value);
 592         int (*pinctrl_set_config)(const u32 pin, const u32 param, u32 value);
 593         int (*register_access)(u32 register_access_id, u32 address,
 594                                u32 mask, u32 value, u32 *out);
 595         int (*aes)(const u64 address, u32 *out);
 596         int (*efuse_access)(const u64 address, u32 *out);
 597         int (*secure_image)(const u64 src_addr, u64 key_addr, u64 *dst);
 598 };
 599
 600 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 601                         u32 arg2, u32 arg3, u32 *ret_payload);
 602
 603 int zynqmp_pm_ggs_init(struct kobject *parent_kobj);
 604
 605 #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
 606 const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
 607 #else
 608 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
 609 {
 610         return ERR_PTR(-ENODEV);
 611 }
 612 #endif
 613
 614 #endif /* __FIRMWARE_ZYNQMP_H__ */