drivers/misc/xilinx_sdfec.c

   1 /*
   2  * Xilinx SDFEC
   3  *
   4  * Copyright (C) 2016 - 2017 Xilinx, Inc.
   5  *
   6  * Description:
   7  * This driver is developed for SDFEC16 (Soft Decision FEC 16nm)
   8  * IP. It exposes a char device interface in sysfs and supports file
   9  * operations like  open(), close() and ioctl().
  10  *
  11  * This program is free software: you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #include <linux/cdev.h>
  26 #include <linux/device.h>
  27 #include <linux/fs.h>
  28 #include <linux/io.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/poll.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38
  39 #include <uapi/misc/xilinx_sdfec.h>
  40
  41 #define DRIVER_NAME     "xilinx_sdfec"
  42 #define DRIVER_VERSION  "0.3"
  43 #define DRIVER_MAX_DEV  (6)
  44
  45 static  struct class *xsdfec_class;
  46 static atomic_t xsdfec_ndevs = ATOMIC_INIT(0);
  47 static dev_t xsdfec_devt;
  48
  49 /* Xilinx SDFEC Register Map */
  50 #define XSDFEC_AXI_WR_PROTECT_ADDR              (0x00000)
  51 #define XSDFEC_CODE_WR_PROTECT_ADDR             (0x00004)
  52 #define XSDFEC_ACTIVE_ADDR                      (0x00008)
  53 #define XSDFEC_AXIS_WIDTH_ADDR                  (0x0000c)
  54 #define XSDFEC_AXIS_ENABLE_ADDR                 (0x00010)
  55 #define XSDFEC_AXIS_ENABLE_MASK                 (0x0001F)
  56 #define XSDFEC_FEC_CODE_ADDR                    (0x00014)
  57 #define XSDFEC_ORDER_ADDR                       (0x00018)
  58
  59 /* Interrupt Status Register Bit Mask*/
  60 #define XSDFEC_ISR_MASK                         (0x0003F)
  61 /* Interrupt Status Register */
  62 #define XSDFEC_ISR_ADDR                         (0x0001c)
  63 /* Write Only - Interrupt Enable Register */
  64 #define XSDFEC_IER_ADDR                         (0x00020)
  65 /* Write Only - Interrupt Disable Register */
  66 #define XSDFEC_IDR_ADDR                         (0x00024)
  67 /* Read Only - Interrupt Mask Register */
  68 #define XSDFEC_IMR_ADDR                         (0x00028)
  69
  70 /* Single Bit Errors */
  71 #define XSDFEC_ECC_ISR_SBE                      (0x7FF)
  72 /* Multi Bit Errors */
  73 #define XSDFEC_ECC_ISR_MBE                      (0x3FF800)
  74 /* ECC Interrupt Status Bit Mask */
  75 #define XSDFEC_ECC_ISR_MASK     (XSDFEC_ECC_ISR_SBE | XSDFEC_ECC_ISR_MBE)
  76
  77 /* Multi Bit Error Postion */
  78 #define XSDFEC_ECC_MULTI_BIT_POS                (11)
  79 #define XSDFEC_ERROR_MAX_THRESHOLD              (100)
  80
  81 /* ECC Interrupt Status Register */
  82 #define XSDFEC_ECC_ISR_ADDR                     (0x0002c)
  83 /* Write Only - ECC Interrupt Enable Register */
  84 #define XSDFEC_ECC_IER_ADDR                     (0x00030)
  85 /* Write Only - ECC Interrupt Disable Register */
  86 #define XSDFEC_ECC_IDR_ADDR                     (0x00034)
  87 /* Read Only - ECC Interrupt Mask Register */
  88 #define XSDFEC_ECC_IMR_ADDR                     (0x00038)
  89
  90 #define XSDFEC_BYPASS_ADDR                      (0x0003c)
  91 #define XSDFEC_TEST_EMA_ADDR_BASE               (0x00080)
  92 #define XSDFEC_TEST_EMA_ADDR_HIGH               (0x00089)
  93 #define XSDFEC_TURBO_ADDR                       (0x00100)
  94 #define XSDFEC_LDPC_CODE_REG0_ADDR_BASE         (0x02000)
  95 #define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH         (0x021fc)
  96 #define XSDFEC_LDPC_CODE_REG1_ADDR_BASE         (0x02004)
  97 #define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH         (0x02200)
  98 #define XSDFEC_LDPC_CODE_REG2_ADDR_BASE         (0x02008)
  99 #define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH         (0x02204)
 100 #define XSDFEC_LDPC_CODE_REG3_ADDR_BASE         (0x0200c)
 101 #define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH         (0x02208)
 102
 103 /**
 104  * struct xsdfec_dev - Driver data for SDFEC
 105  * @regs: device physical base address
 106  * @dev: pointer to device struct
 107  * @fec_id: Instance number
 108  * @intr_enabled: indicates IRQ enabled
 109  * @wr_protect: indicates Write Protect enabled
 110  * @code: LDPC or Turbo Codes being used
 111  * @order: In-Order or Out-of-Order
 112  * @state: State of the SDFEC device
 113  * @op_mode: Operating in Encode or Decode
 114  * @isr_err_count: Count of ISR errors
 115  * @cecc_count: Count of Correctable ECC errors (SBE)
 116  * @uecc_count: Count of Uncorrectable ECC errors (MBE)
 117  * @reset_count: Count of Resets requested
 118  * @open_count: Count of char device being opened
 119  * @irq: IRQ number
 120  * @xsdfec_cdev: Character device handle
 121  * @sc_off: Shared Scale Table Offset
 122  * @qc_off: Shared Circulant Table Offset
 123  * @la_off: Shared Layer Table Offset
 124  * @waitq: Driver wait queue
 125  *
 126  * This structure contains necessary state for SDFEC driver to operate
 127  */
 128 struct xsdfec_dev {
 129         void __iomem *regs;
 130         struct device *dev;
 131         s32  fec_id;
 132         bool intr_enabled;
 133         bool wr_protect;
 134         enum xsdfec_code code;
 135         enum xsdfec_order order;
 136         enum xsdfec_state state;
 137         enum xsdfec_op_mode op_mode;
 138         atomic_t isr_err_count;
 139         atomic_t cecc_count;
 140         atomic_t uecc_count;
 141         atomic_t reset_count;
 142         atomic_t open_count;
 143         int  irq;
 144         struct cdev xsdfec_cdev;
 145         int sc_off;
 146         int qc_off;
 147         int la_off;
 148         wait_queue_head_t waitq;
 149 };
 150
 151 static inline void
 152 xsdfec_regwrite(struct xsdfec_dev *xsdfec, u32 addr, u32 value)
 153 {
 154         if (xsdfec->wr_protect) {
 155                 dev_err(xsdfec->dev, "SDFEC in write protect");
 156                 return;
 157         }
 158
 159         dev_dbg(xsdfec->dev,
 160                 "Writing 0x%x to offset 0x%x", value, addr);
 161         iowrite32(value, xsdfec->regs + addr);
 162 }
 163
 164 static inline u32
 165 xsdfec_regread(struct xsdfec_dev *xsdfec, u32 addr)
 166 {
 167         u32 rval;
 168
 169         rval = ioread32(xsdfec->regs + addr);
 170         dev_info(xsdfec->dev,
 171                  "Read value = 0x%x from offset 0x%x",
 172                  rval, addr);
 173         return rval;
 174 }
 175
 176 #define XSDFEC_WRITE_PROTECT_ENABLE     (1)
 177 #define XSDFEC_WRITE_PROTECT_DISABLE    (0)
 178 static void
 179 xsdfec_wr_protect(struct xsdfec_dev *xsdfec, bool wr_pr)
 180 {
 181         if (wr_pr) {
 182                 xsdfec_regwrite(xsdfec,
 183                                 XSDFEC_CODE_WR_PROTECT_ADDR,
 184                                 XSDFEC_WRITE_PROTECT_ENABLE);
 185                 xsdfec_regwrite(xsdfec,
 186                                 XSDFEC_AXI_WR_PROTECT_ADDR,
 187                                 XSDFEC_WRITE_PROTECT_ENABLE);
 188         } else {
 189                 xsdfec_regwrite(xsdfec,
 190                                 XSDFEC_AXI_WR_PROTECT_ADDR,
 191                                 XSDFEC_WRITE_PROTECT_DISABLE);
 192                 xsdfec_regwrite(xsdfec,
 193                                 XSDFEC_CODE_WR_PROTECT_ADDR,
 194                                 XSDFEC_WRITE_PROTECT_DISABLE);
 195         }
 196         xsdfec->wr_protect = wr_pr;
 197 }
 198
 199 static int
 200 xsdfec_dev_open(struct inode *iptr, struct file *fptr)
 201 {
 202         struct xsdfec_dev *xsdfec;
 203
 204         xsdfec = container_of(iptr->i_cdev, struct xsdfec_dev, xsdfec_cdev);
 205         if (!xsdfec)
 206                 return  -EAGAIN;
 207
 208         /* Only one open per device at a time */
 209         if (!atomic_dec_and_test(&xsdfec->open_count))
 210                 return -EBUSY;
 211
 212         fptr->private_data = xsdfec;
 213         return 0;
 214 }
 215
 216 static int
 217 xsdfec_dev_release(struct inode *iptr, struct file *fptr)
 218 {
 219         struct xsdfec_dev *xsdfec;
 220
 221         xsdfec = container_of(iptr->i_cdev, struct xsdfec_dev, xsdfec_cdev);
 222         if (!xsdfec)
 223                 return -EAGAIN;
 224
 225         atomic_inc(&xsdfec->open_count);
 226         return 0;
 227 }
 228
 229 #define XSDFEC_IS_ACTIVITY_SET  (0x1)
 230 static int
 231 xsdfec_get_status(struct xsdfec_dev *xsdfec, void __user *arg)
 232 {
 233         struct xsdfec_status status;
 234         int err = 0;
 235
 236         status.fec_id = xsdfec->fec_id;
 237         status.state = xsdfec->state;
 238         status.code = xsdfec->code;
 239         status.order = xsdfec->order;
 240         status.mode = xsdfec->op_mode;
 241         status.activity  =
 242                 (xsdfec_regread(xsdfec,
 243                                 XSDFEC_ACTIVE_ADDR) &
 244                                 XSDFEC_IS_ACTIVITY_SET);
 245         status.cecc_count = atomic_read(&xsdfec->cecc_count);
 246
 247         err = copy_to_user(arg, &status, sizeof(status));
 248         if (err) {
 249                 dev_err(xsdfec->dev, "%s failed for SDFEC%d",
 250                         __func__, xsdfec->fec_id);
 251                 err = -EFAULT;
 252         }
 253         return err;
 254 }
 255
 256 static int
 257 xsdfec_get_config(struct xsdfec_dev *xsdfec, void __user *arg)
 258 {
 259         struct xsdfec_config config;
 260         int err = 0;
 261
 262         config.fec_id = xsdfec->fec_id;
 263         config.state = xsdfec->state;
 264         config.code = xsdfec->code;
 265         config.mode = xsdfec->op_mode;
 266         config.order = xsdfec->order;
 267
 268         err = copy_to_user(arg, &config, sizeof(config));
 269         if (err) {
 270                 dev_err(xsdfec->dev, "%s failed for SDFEC%d",
 271                         __func__, xsdfec->fec_id);
 272                 err = -EFAULT;
 273         }
 274         return err;
 275 }
 276
 277 static int
 278 xsdfec_isr_enable(struct xsdfec_dev *xsdfec, bool enable)
 279 {
 280         u32 mask_read;
 281
 282         if (enable) {
 283                 /* Enable */
 284                 xsdfec_regwrite(xsdfec, XSDFEC_IER_ADDR,
 285                                 XSDFEC_ISR_MASK);
 286                 mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);
 287                 if (mask_read & XSDFEC_ISR_MASK) {
 288                         dev_err(xsdfec->dev,
 289                                 "SDFEC enabling irq with IER failed");
 290                         return -EIO;
 291                 }
 292         } else {
 293                 /* Disable */
 294                 xsdfec_regwrite(xsdfec, XSDFEC_IDR_ADDR,
 295                                 XSDFEC_ISR_MASK);
 296                 mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);
 297                 if ((mask_read & XSDFEC_ISR_MASK) != XSDFEC_ISR_MASK) {
 298                         dev_err(xsdfec->dev,
 299                                 "SDFEC disabling irq with IDR failed");
 300                         return -EIO;
 301                 }
 302         }
 303         return 0;
 304 }
 305
 306 static int
 307 xsdfec_ecc_isr_enable(struct xsdfec_dev *xsdfec, bool enable)
 308 {
 309         u32 mask_read;
 310
 311         if (enable) {
 312                 /* Enable */
 313                 xsdfec_regwrite(xsdfec, XSDFEC_ECC_IER_ADDR,
 314                                 XSDFEC_ECC_ISR_MASK);
 315                 mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);
 316                 if (mask_read & XSDFEC_ECC_ISR_MASK) {
 317                         dev_err(xsdfec->dev,
 318                                 "SDFEC enabling ECC irq with ECC IER failed");
 319                         return -EIO;
 320                 }
 321         } else {
 322                 /* Disable */
 323                 xsdfec_regwrite(xsdfec, XSDFEC_ECC_IDR_ADDR,
 324                                 XSDFEC_ECC_ISR_MASK);
 325                 mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);
 326                 if ((mask_read & XSDFEC_ECC_ISR_MASK) != XSDFEC_ECC_ISR_MASK) {
 327                         dev_err(xsdfec->dev,
 328                                 "SDFEC disable ECC irq with ECC IDR failed");
 329                         return -EIO;
 330                 }
 331         }
 332         return 0;
 333 }
 334
 335 static int
 336 xsdfec_set_irq(struct xsdfec_dev *xsdfec, void __user *arg)
 337 {
 338         struct xsdfec_irq  irq;
 339         int err = 0;
 340
 341         err = copy_from_user(&irq, arg, sizeof(irq));
 342         if (err) {
 343                 dev_err(xsdfec->dev, "%s failed for SDFEC%d",
 344                         __func__, xsdfec->fec_id);
 345                 return -EFAULT;
 346         }
 347
 348         /* Setup tlast related IRQ */
 349         if (irq.enable_isr) {
 350                 err = xsdfec_isr_enable(xsdfec, true);
 351                 if (err < 0)
 352                         return err;
 353         }
 354
 355         /* Setup ECC related IRQ */
 356         if (irq.enable_ecc_isr) {
 357                 err = xsdfec_ecc_isr_enable(xsdfec, true);
 358                 if (err < 0)
 359                         return err;
 360         }
 361
 362         return 0;
 363 }
 364
 365 #define XSDFEC_TURBO_SCALE_MASK         (0xF)
 366 #define XSDFEC_TURBO_SCALE_BIT_POS      (8)
 367 static int
 368 xsdfec_set_turbo(struct xsdfec_dev *xsdfec, void __user *arg)
 369 {
 370         struct xsdfec_turbo turbo;
 371         int err = 0;
 372         u32 turbo_write = 0;
 373
 374         err = copy_from_user(&turbo, arg, sizeof(turbo));
 375         if (err) {
 376                 dev_err(xsdfec->dev, "%s failed for SDFEC%d",
 377                         __func__, xsdfec->fec_id);
 378                 return -EFAULT;
 379         }
 380
 381         /* Check to see what device tree says about the FEC codes */
 382         if (xsdfec->code == XSDFEC_LDPC_CODE) {
 383                 dev_err(xsdfec->dev,
 384                         "%s: Unable to write Turbo to SDFEC%d check DT",
 385                                 __func__, xsdfec->fec_id);
 386                 return -EIO;
 387         } else if (xsdfec->code == XSDFEC_CODE_INVALID) {
 388                 xsdfec->code = XSDFEC_TURBO_CODE;
 389         }
 390
 391         if (xsdfec->wr_protect)
 392                 xsdfec_wr_protect(xsdfec, false);
 393
 394         xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, (xsdfec->code - 1));
 395         turbo_write = ((turbo.scale & XSDFEC_TURBO_SCALE_MASK) <<
 396                         XSDFEC_TURBO_SCALE_BIT_POS) | turbo.alg;
 397         xsdfec_regwrite(xsdfec, XSDFEC_TURBO_ADDR, turbo_write);
 398         return err;
 399 }
 400
 401 #define XSDFEC_LDPC_REG_JUMP    (0x10)
 402 #define XSDFEC_REG0_N_MASK      (0x0000FFFF)
 403 #define XSDFEC_REG0_N_LSB       (0)
 404 #define XSDFEC_REG0_K_MASK      (0x7fff0000)
 405 #define XSDFEC_REG0_K_LSB       (16)
 406 static int
 407 xsdfec_reg0_write(struct xsdfec_dev *xsdfec,
 408                   u32 n, u32 k, u32 offset)
 409 {
 410         u32 wdata;
 411
 412         /* Use only lower 16 bits */
 413         if (n & ~XSDFEC_REG0_N_MASK)
 414                 dev_err(xsdfec->dev, "N value is beyond 16 bits");
 415         n &= XSDFEC_REG0_N_MASK;
 416         n <<= XSDFEC_REG0_N_LSB;
 417
 418         if (k & XSDFEC_REG0_K_MASK)
 419                 dev_err(xsdfec->dev, "K value is beyond 16 bits");
 420
 421         k = ((k << XSDFEC_REG0_K_LSB) & XSDFEC_REG0_K_MASK);
 422         wdata = k | n;
 423
 424         if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP)
 425                                 > XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) {
 426                 dev_err(xsdfec->dev,
 427                         "Writing outside of LDPC reg0 space 0x%x",
 428                         XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
 429                         (offset * XSDFEC_LDPC_REG_JUMP));
 430                 return -EINVAL;
 431         }
 432         xsdfec_regwrite(xsdfec,
 433                         XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
 434                         (offset * XSDFEC_LDPC_REG_JUMP), wdata);
 435         return 0;
 436 }
 437
 438 #define XSDFEC_REG1_PSIZE_MASK          (0x000001ff)
 439 #define XSDFEC_REG1_NO_PACKING_MASK     (0x00000400)
 440 #define XSDFEC_REG1_NO_PACKING_LSB      (10)
 441 #define XSDFEC_REG1_NM_MASK             (0x000ff800)
 442 #define XSDFEC_REG1_NM_LSB              (11)
 443 #define XSDFEC_REG1_BYPASS_MASK (0x00100000)
 444 static int
 445 xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize,
 446                   u32 no_packing, u32 nm, u32 offset)
 447 {
 448         u32 wdata;
 449
 450         if (psize & ~XSDFEC_REG1_PSIZE_MASK)
 451                 dev_err(xsdfec->dev, "Psize is beyond 10 bits");
 452         psize &= XSDFEC_REG1_PSIZE_MASK;
 453
 454         if (no_packing != 0 && no_packing != 1)
 455                 dev_err(xsdfec->dev, "No-packing bit register invalid");
 456         no_packing = ((no_packing << XSDFEC_REG1_NO_PACKING_LSB) &
 457                                         XSDFEC_REG1_NO_PACKING_MASK);
 458
 459         if (nm & ~(XSDFEC_REG1_NM_MASK >> XSDFEC_REG1_NM_LSB))
 460                 dev_err(xsdfec->dev, "NM is beyond 10 bits");
 461         nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK;
 462
 463         wdata = nm | no_packing | psize;
 464         if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP)
 465                 > XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) {
 466                 dev_err(xsdfec->dev,
 467                         "Writing outside of LDPC reg1 space 0x%x",
 468                         XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
 469                         (offset * XSDFEC_LDPC_REG_JUMP));
 470                 return -EINVAL;
 471         }
 472         xsdfec_regwrite(xsdfec, XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
 473                 (offset * XSDFEC_LDPC_REG_JUMP), wdata);
 474         return 0;
 475 }
 476
 477 #define XSDFEC_REG2_NLAYERS_MASK                (0x000001FF)
 478 #define XSDFEC_REG2_NLAYERS_LSB                 (0)
 479 #define XSDFEC_REG2_NNMQC_MASK                  (0x000FFE00)
 480 #define XSDFEC_REG2_NMQC_LSB                    (9)
 481 #define XSDFEC_REG2_NORM_TYPE_MASK              (0x00100000)
 482 #define XSDFEC_REG2_NORM_TYPE_LSB               (20)
 483 #define XSDFEC_REG2_SPECIAL_QC_MASK             (0x00200000)
 484 #define XSDFEC_REG2_SPEICAL_QC_LSB              (21)
 485 #define XSDFEC_REG2_NO_FINAL_PARITY_MASK        (0x00400000)
 486 #define XSDFEC_REG2_NO_FINAL_PARITY_LSB         (22)
 487 #define XSDFEC_REG2_MAX_SCHEDULE_MASK           (0x01800000)
 488 #define XSDFEC_REG2_MAX_SCHEDULE_LSB            (23)
 489
 490 static int
 491 xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc,
 492                   u32 norm_type, u32 special_qc, u32 no_final_parity,
 493                   u32 max_schedule, u32 offset)
 494 {
 495         u32 wdata;
 496
 497         if (nlayers & ~(XSDFEC_REG2_NLAYERS_MASK >>
 498                                 XSDFEC_REG2_NLAYERS_LSB))
 499                 dev_err(xsdfec->dev, "Nlayers exceeds 9 bits");
 500         nlayers &= XSDFEC_REG2_NLAYERS_MASK;
 501
 502         if (nmqc & ~(XSDFEC_REG2_NNMQC_MASK >> XSDFEC_REG2_NMQC_LSB))
 503                 dev_err(xsdfec->dev, "NMQC exceeds 11 bits");
 504         nmqc = (nmqc << XSDFEC_REG2_NMQC_LSB) & XSDFEC_REG2_NNMQC_MASK;
 505
 506         if (norm_type > 1)
 507                 dev_err(xsdfec->dev, "Norm type is invalid");
 508         norm_type = ((norm_type << XSDFEC_REG2_NORM_TYPE_LSB) &
 509                                         XSDFEC_REG2_NORM_TYPE_MASK);
 510         if (special_qc > 1)
 511                 dev_err(xsdfec->dev, "Special QC in invalid");
 512         special_qc = ((special_qc << XSDFEC_REG2_SPEICAL_QC_LSB) &
 513                         XSDFEC_REG2_SPECIAL_QC_MASK);
 514
 515         if (no_final_parity > 1)
 516                 dev_err(xsdfec->dev, "No final parity check invalid");
 517         no_final_parity =
 518                 ((no_final_parity << XSDFEC_REG2_NO_FINAL_PARITY_LSB) &
 519                                         XSDFEC_REG2_NO_FINAL_PARITY_MASK);
 520         if (max_schedule & ~(XSDFEC_REG2_MAX_SCHEDULE_MASK >>
 521                                         XSDFEC_REG2_MAX_SCHEDULE_LSB))
 522                 dev_err(xsdfec->dev, "Max Schdule exceeds 2 bits");
 523         max_schedule = ((max_schedule << XSDFEC_REG2_MAX_SCHEDULE_LSB) &
 524                                 XSDFEC_REG2_MAX_SCHEDULE_MASK);
 525
 526         wdata = (max_schedule | no_final_parity | special_qc | norm_type |
 527                         nmqc | nlayers);
 528
 529         if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP)
 530                 > XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) {
 531                 dev_err(xsdfec->dev,
 532                         "Writing outside of LDPC reg2 space 0x%x",
 533                         XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
 534                         (offset * XSDFEC_LDPC_REG_JUMP));
 535                 return -EINVAL;
 536         }
 537         xsdfec_regwrite(xsdfec, XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
 538                         (offset * XSDFEC_LDPC_REG_JUMP), wdata);
 539         return 0;
 540 }
 541
 542 #define XSDFEC_REG3_LA_OFF_LSB          (8)
 543 #define XSDFEC_REG3_QC_OFF_LSB          (16)
 544 static int
 545 xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off,
 546                   u8 la_off, u16 qc_off, u32 offset)
 547 {
 548         u32 wdata;
 549
 550         wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) |
 551                 (la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off);
 552         if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
 553                 (offset *  XSDFEC_LDPC_REG_JUMP) >
 554                         XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) {
 555                 dev_err(xsdfec->dev,
 556                         "Writing outside of LDPC reg3 space 0x%x",
 557                         XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
 558                         (offset * XSDFEC_LDPC_REG_JUMP));
 559                 return -EINVAL;
 560         }
 561         xsdfec_regwrite(xsdfec, XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
 562                         (offset * XSDFEC_LDPC_REG_JUMP), wdata);
 563         return 0;
 564 }
 565
 566 #define XSDFEC_SC_TABLE_DEPTH           (0x3fc)
 567 #define XSDFEC_REG_WIDTH_JUMP           (4)
 568 static int
 569 xsdfec_sc_table_write(struct xsdfec_dev *xsdfec, u32 offset,
 570                       u32 *sc_ptr, u32 len)
 571 {
 572         int reg;
 573
 574         /*
 575          * Writes that go beyond the length of
 576          * Shared Scale(SC) table should fail
 577          */
 578         if ((XSDFEC_REG_WIDTH_JUMP * (offset + len)) > XSDFEC_SC_TABLE_DEPTH) {
 579                 dev_err(xsdfec->dev, "Write exceeds SC table length");
 580                 return -EINVAL;
 581         }
 582
 583         /*
 584          * sc_off tracks the points to the last written location
 585          * in the Shared Scale(SC) table. Those shared codes might
 586          * be in use. Updating them without quiescing the device
 587          * can put the SDFEC device in an indeterminate state
 588          */
 589         if ((XSDFEC_REG_WIDTH_JUMP * offset) < xsdfec->sc_off) {
 590                 dev_err(xsdfec->dev, "Might write to in use shared SC code");
 591                 return -EINVAL;
 592         }
 593
 594         for (reg = 0; reg < len; reg++) {
 595                 xsdfec_regwrite(xsdfec, XSDFEC_LDPC_SC_TABLE_ADDR_BASE +
 596                 (offset + reg) *  XSDFEC_REG_WIDTH_JUMP, sc_ptr[reg]);
 597         }
 598         xsdfec->sc_off = reg + (XSDFEC_REG_WIDTH_JUMP * offset);
 599         return reg;
 600 }
 601
 602 #define XSDFEC_LA_TABLE_DEPTH           (0xFFC)
 603 static int
 604 xsdfec_la_table_write(struct xsdfec_dev *xsdfec, u32 offset,
 605                       u32 *la_ptr, u32 len)
 606 {
 607         int reg;
 608
 609         if (XSDFEC_REG_WIDTH_JUMP * (offset + len) > XSDFEC_LA_TABLE_DEPTH) {
 610                 dev_err(xsdfec->dev, "Write exceeds LA table length");
 611                 return -EINVAL;
 612         }
 613
 614         if  (XSDFEC_REG_WIDTH_JUMP * offset < xsdfec->la_off) {
 615                 dev_err(xsdfec->dev, "Might write to in use shared LA code");
 616                 return -EINVAL;
 617         }
 618
 619         for (reg = 0; reg < len; reg++) {
 620                 xsdfec_regwrite(xsdfec, XSDFEC_LDPC_LA_TABLE_ADDR_BASE +
 621                                 (offset + reg) * XSDFEC_REG_WIDTH_JUMP,
 622                                 la_ptr[reg]);
 623         }
 624         xsdfec->la_off = reg + (offset * XSDFEC_REG_WIDTH_JUMP);
 625         return reg;
 626 }
 627
 628 #define XSDFEC_QC_TABLE_DEPTH           (0x7FFC)
 629 static int
 630 xsdfec_qc_table_write(struct xsdfec_dev *xsdfec,
 631                       u32 offset, u32 *qc_ptr, u32 len)
 632 {
 633         int reg;
 634
 635         if (XSDFEC_REG_WIDTH_JUMP * (offset + len) > XSDFEC_QC_TABLE_DEPTH) {
 636                 dev_err(xsdfec->dev, "Write exceeds QC table length");
 637                 return -EINVAL;
 638         }
 639
 640         if (XSDFEC_REG_WIDTH_JUMP * offset < xsdfec->qc_off) {
 641                 dev_err(xsdfec->dev, "Might write to in use shared LA code");
 642                 return -EINVAL;
 643         }
 644
 645         for (reg = 0; reg < len; reg++) {
 646                 xsdfec_regwrite(xsdfec, XSDFEC_LDPC_QC_TABLE_ADDR_BASE +
 647                  (offset + reg) * XSDFEC_REG_WIDTH_JUMP, qc_ptr[reg]);
 648         }
 649
 650         xsdfec->qc_off = reg + (offset * XSDFEC_REG_WIDTH_JUMP);
 651         return reg;
 652 }
 653
 654 static int
 655 xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg)
 656 {
 657         struct xsdfec_ldpc_params *ldpc;
 658         int err;
 659
 660         ldpc = kzalloc(sizeof(*ldpc), GFP_KERNEL);
 661         if (!ldpc)
 662                 return -ENOMEM;
 663
 664         err = copy_from_user(ldpc, arg, sizeof(*ldpc));
 665         if (err) {
 666                 dev_err(xsdfec->dev,
 667                         "%s failed to copy from user for SDFEC%d",
 668                         __func__, xsdfec->fec_id);
 669                 return -EFAULT;
 670         }
 671         if (xsdfec->code == XSDFEC_TURBO_CODE) {
 672                 dev_err(xsdfec->dev,
 673                         "%s: Unable to write LDPC to SDFEC%d check DT",
 674                         __func__, xsdfec->fec_id);
 675                 return -EIO;
 676         }
 677         xsdfec->code = XSDFEC_LDPC_CODE;
 678         /* Disable Write Protection before proceeding */
 679         if (xsdfec->wr_protect)
 680                 xsdfec_wr_protect(xsdfec, false);
 681
 682         /* Write LDPC to CODE Register */
 683         xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, (xsdfec->code - 1));
 684         /* Write Reg 0 */
 685         err = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->code_id);
 686         if (err)
 687                 goto err_out;
 688
 689         /* Write Reg 1 */
 690         err = xsdfec_reg1_write(xsdfec, ldpc->psize, ldpc->no_packing,
 691                                 ldpc->nm, ldpc->code_id);
 692         if (err)
 693                 goto err_out;
 694
 695         /* Write Reg 2 */
 696         err = xsdfec_reg2_write(xsdfec, ldpc->nlayers, ldpc->nmqc,
 697                                 ldpc->norm_type, ldpc->special_qc,
 698                                 ldpc->no_final_parity, ldpc->max_schedule,
 699                                 ldpc->code_id);
 700         if (err)
 701                 goto err_out;
 702
 703         /* Write Reg 3 */
 704         err = xsdfec_reg3_write(xsdfec, ldpc->sc_off,
 705                                 ldpc->la_off, ldpc->qc_off, ldpc->code_id);
 706         if (err)
 707                 goto err_out;
 708
 709         /* Write Shared Codes */
 710         err = xsdfec_sc_table_write(xsdfec, ldpc->sc_off,
 711                                     ldpc->sc_table, ldpc->nlayers);
 712         if (err < 0)
 713                 goto err_out;
 714
 715         err = xsdfec_la_table_write(xsdfec, 4 * ldpc->la_off,
 716                                     ldpc->la_table, ldpc->nlayers);
 717         if (err < 0)
 718                 goto err_out;
 719
 720         err = xsdfec_qc_table_write(xsdfec, 4 * ldpc->qc_off,
 721                                     ldpc->qc_table, ldpc->nqc);
 722         if (err < 0)
 723                 goto err_out;
 724
 725         kfree(ldpc);
 726         return 0;
 727         /* Error Path */
 728 err_out:
 729         kfree(ldpc);
 730         return err;
 731 }
 732
 733 static int xsdfec_start(struct xsdfec_dev *xsdfec)
 734 {
 735         u32 regread;
 736
 737         /* Verify Code is loaded */
 738         if (xsdfec->code == XSDFEC_CODE_INVALID) {
 739                 dev_err(xsdfec->dev,
 740                         "%s : set code before start for SDFEC%d",
 741                         __func__, xsdfec->fec_id);
 742                 return -EINVAL;
 743         }
 744         regread = xsdfec_regread(xsdfec, XSDFEC_FEC_CODE_ADDR);
 745         regread &= 0x1;
 746         if (regread + 1 != xsdfec->code) {
 747                 dev_err(xsdfec->dev,
 748                         "%s SDFEC HW code does not match driver code",
 749                         __func__);
 750                 return -EINVAL;
 751         }
 752         /* Set Order to maintain order */
 753         xsdfec->order = XSDFEC_MAINTAIN_ORDER;
 754         xsdfec_regwrite(xsdfec, XSDFEC_ORDER_ADDR, (xsdfec->order - 1));
 755         /* Set AXIS width */
 756         xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, 0);
 757         /* Set AXIS enable */
 758         xsdfec_regwrite(xsdfec,
 759                         XSDFEC_AXIS_ENABLE_ADDR,
 760                         XSDFEC_AXIS_ENABLE_MASK);
 761         /* Write Protect Code and Registers */
 762         xsdfec_wr_protect(xsdfec, true);
 763         /* Done */
 764         xsdfec->state = XSDFEC_STARTED;
 765         return 0;
 766 }
 767
 768 static int
 769 xsdfec_stop(struct xsdfec_dev *xsdfec)
 770 {
 771         u32 regread;
 772
 773         if (xsdfec->state != XSDFEC_STARTED)
 774                 dev_err(xsdfec->dev, "Device not started correctly");
 775         /* Disable Write Protect */
 776         xsdfec_wr_protect(xsdfec, false);
 777         /* Disable AXIS_ENABLE register */
 778         regread = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR);
 779         regread &= (~XSDFEC_AXIS_ENABLE_MASK);
 780         xsdfec_regwrite(xsdfec, XSDFEC_AXIS_ENABLE_ADDR, regread);
 781         /* Stop */
 782         xsdfec->state = XSDFEC_STOPPED;
 783         return 0;
 784 }
 785
 786 /*
 787  * Reset will happen asynchronously
 788  * since there is no in-band reset register
 789  * Prepare driver for reset
 790  */
 791
 792 static int
 793 xsdfec_reset_req(struct xsdfec_dev *xsdfec)
 794 {
 795         xsdfec->state = XSDFEC_INIT;
 796         xsdfec->order = XSDFEC_INVALID_ORDER;
 797         xsdfec->sc_off = 0;
 798         xsdfec->la_off = 0;
 799         xsdfec->qc_off = 0;
 800         xsdfec->wr_protect = false;
 801         atomic_set(&xsdfec->isr_err_count, 0);
 802         atomic_set(&xsdfec->uecc_count, 0);
 803         atomic_set(&xsdfec->cecc_count, 0);
 804         atomic_inc(&xsdfec->reset_count);
 805         return 0;
 806 }
 807
 808 static long
 809 xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
 810 {
 811         struct xsdfec_dev *xsdfec = fptr->private_data;
 812         void __user *arg = (void __user *)data;
 813         int rval = -EINVAL;
 814
 815         if (!xsdfec)
 816                 return rval;
 817         if (!arg)
 818                 return rval;
 819
 820         /* In failed state allow only reset and get status IOCTLs */
 821         if (xsdfec->state == XSDFEC_NEEDS_RESET &&
 822             (cmd != XSDFEC_RESET_REQ && cmd != XSDFEC_GET_STATUS)) {
 823                 dev_err(xsdfec->dev,
 824                         "SDFEC%d in failed state. Reset Required",
 825                         xsdfec->fec_id);
 826                 return -EPERM;
 827         }
 828
 829         switch (cmd) {
 830         case XSDFEC_START_DEV:
 831                 rval = xsdfec_start(xsdfec);
 832                 break;
 833         case XSDFEC_STOP_DEV:
 834                 rval = xsdfec_stop(xsdfec);
 835                 break;
 836         case XSDFEC_RESET_REQ:
 837                 rval = xsdfec_reset_req(xsdfec);
 838                 break;
 839         case XSDFEC_GET_STATUS:
 840                 rval = xsdfec_get_status(xsdfec, arg);
 841                 break;
 842         case XSDFEC_GET_CONFIG:
 843                 rval = xsdfec_get_config(xsdfec, arg);
 844                 break;
 845         case XSDFEC_SET_IRQ:
 846                 rval = xsdfec_set_irq(xsdfec, arg);
 847                 break;
 848         case XSDFEC_SET_TURBO:
 849                 rval = xsdfec_set_turbo(xsdfec, arg);
 850                 break;
 851         case XSDFEC_ADD_LDPC:
 852                 rval  = xsdfec_add_ldpc(xsdfec, arg);
 853                 break;
 854         default:
 855                 /* Should not get here */
 856                 dev_err(xsdfec->dev, "Undefined SDFEC IOCTL");
 857                 break;
 858         }
 859         return rval;
 860 }
 861
 862 static unsigned int
 863 xsdfec_poll(struct file *file, poll_table *wait)
 864 {
 865         unsigned int mask;
 866         struct xsdfec_dev *xsdfec = file->private_data;
 867
 868         if (!xsdfec)
 869                 return POLLNVAL | POLLHUP;
 870
 871         poll_wait(file, &xsdfec->waitq, wait);
 872
 873         /* XSDFEC ISR detected an error */
 874         if (xsdfec->state == XSDFEC_NEEDS_RESET)
 875                 mask = POLLIN | POLLRDNORM;
 876         else
 877                 mask = POLLPRI | POLLERR;
 878
 879         return mask;
 880 }
 881
 882 static const struct file_operations xsdfec_fops = {
 883         .owner = THIS_MODULE,
 884         .open = xsdfec_dev_open,
 885         .release = xsdfec_dev_release,
 886         .unlocked_ioctl = xsdfec_dev_ioctl,
 887         .poll = xsdfec_poll,
 888 };
 889
 890 static int
 891 xsdfec_parse_of(struct xsdfec_dev *xsdfec)
 892 {
 893         struct device *dev = xsdfec->dev;
 894         struct device_node *node = dev->of_node;
 895         int rval;
 896         const char *fec_code;
 897         const char *fec_op_mode;
 898
 899         rval = of_property_read_string(node,
 900                                        "xlnx,sdfec-op-mode",
 901                                        &fec_op_mode);
 902         if (rval < 0) {
 903                 dev_err(dev, "xlnx,sdfec-op-mode not in DT");
 904                 return rval;
 905         }
 906
 907         if (!strcasecmp(fec_op_mode, "encode")) {
 908                 xsdfec->op_mode = XSDFEC_ENCODE;
 909         } else if (!strcasecmp(fec_op_mode, "decode")) {
 910                 xsdfec->op_mode = XSDFEC_DECODE;
 911         } else {
 912                 dev_err(dev, "Encode or Decode not specified in DT");
 913                 return -EINVAL;
 914         }
 915
 916         rval = of_property_read_string(node, "xlnx,sdfec-code", &fec_code);
 917         if (rval < 0) {
 918                 dev_err(dev, "xlnx,sdfec-code not in DT");
 919                 return rval;
 920         }
 921
 922         if (!strcasecmp(fec_code, "ldpc")) {
 923                 xsdfec->code = XSDFEC_LDPC_CODE;
 924         } else if (!strcasecmp(fec_code, "turbo")) {
 925                 xsdfec->code = XSDFEC_TURBO_CODE;
 926         } else {
 927                 dev_err(xsdfec->dev, "Invalid Op Mode in DT");
 928                 return -EINVAL;
 929         }
 930
 931         return 0;
 932 }
 933
 934 static void
 935 xsdfec_log_ecc_errors(struct xsdfec_dev *xsdfec, u32 ecc_err)
 936 {
 937         u32 cecc, uecc;
 938         int uecc_cnt;
 939
 940         cecc = ecc_err & XSDFEC_ECC_ISR_SBE;
 941         uecc = ecc_err & XSDFEC_ECC_ISR_MBE;
 942
 943         uecc_cnt = atomic_add_return(hweight32(uecc), &xsdfec->uecc_count);
 944         atomic_add(hweight32(cecc), &xsdfec->cecc_count);
 945
 946         if (uecc_cnt > 0 && uecc_cnt < XSDFEC_ERROR_MAX_THRESHOLD) {
 947                 dev_err(xsdfec->dev,
 948                         "Multi-bit error on xsdfec%d. Needs reset",
 949                         xsdfec->fec_id);
 950         }
 951
 952         /* Clear ECC errors */
 953         xsdfec_regwrite(xsdfec, XSDFEC_ECC_ISR_ADDR, 0);
 954 }
 955
 956 static void
 957 xsdfec_log_isr_errors(struct xsdfec_dev *xsdfec, u32 isr_err)
 958 {
 959         int isr_err_cnt;
 960
 961         /* Update ISR error counts */
 962         isr_err_cnt = atomic_add_return(hweight32(isr_err),
 963                                         &xsdfec->isr_err_count);
 964         if (isr_err_cnt > 0 && isr_err_cnt < XSDFEC_ERROR_MAX_THRESHOLD) {
 965                 dev_err(xsdfec->dev,
 966                         "Tlast,or DIN_WORDS or DOUT_WORDS not correct");
 967         }
 968
 969         /* Clear ISR error status */
 970         xsdfec_regwrite(xsdfec, XSDFEC_ECC_ISR_ADDR, 0);
 971 }
 972
 973 static void
 974 xsdfec_reset_required(struct xsdfec_dev *xsdfec)
 975 {
 976         xsdfec->state = XSDFEC_NEEDS_RESET;
 977 }
 978
 979 static irqreturn_t
 980 xsdfec_irq_thread(int irq, void *dev_id)
 981 {
 982         struct xsdfec_dev *xsdfec = dev_id;
 983         irqreturn_t ret = IRQ_HANDLED;
 984         u32 ecc_err;
 985         u32 isr_err;
 986         bool fatal_err = false;
 987
 988         WARN_ON(xsdfec->irq != irq);
 989
 990         /* Mask Interrupts */
 991         xsdfec_isr_enable(xsdfec, false);
 992         xsdfec_ecc_isr_enable(xsdfec, false);
 993
 994         /* Read Interrupt Status Registers */
 995         ecc_err = xsdfec_regread(xsdfec, XSDFEC_ECC_ISR_ADDR);
 996         isr_err = xsdfec_regread(xsdfec, XSDFEC_ISR_ADDR);
 997
 998         if (ecc_err & XSDFEC_ECC_ISR_MBE) {
 999                 /* Multi-Bit Errors need Reset */
1000                 xsdfec_log_ecc_errors(xsdfec, ecc_err);
1001                 xsdfec_reset_required(xsdfec);
1002                 fatal_err = true;
1003         } else if (isr_err & XSDFEC_ISR_MASK) {
1004                 /*
1005                  * Tlast, DIN_WORDS and DOUT_WORDS related
1006                  * errors need Reset
1007                  */
1008                 xsdfec_log_isr_errors(xsdfec, isr_err);
1009                 xsdfec_reset_required(xsdfec);
1010                 fatal_err = true;
1011         } else if (ecc_err & XSDFEC_ECC_ISR_SBE) {
1012                 /* Correctable ECC Errors */
1013                 xsdfec_log_ecc_errors(xsdfec, ecc_err);
1014         } else {
1015                 ret = IRQ_NONE;
1016         }
1017
1018         if (fatal_err)
1019                 wake_up_interruptible(&xsdfec->waitq);
1020
1021         /* Unmaks Interrupts */
1022         xsdfec_isr_enable(xsdfec, true);
1023         xsdfec_ecc_isr_enable(xsdfec, true);
1024
1025         return ret;
1026 }
1027
1028 static int
1029 xsdfec_probe(struct platform_device *pdev)
1030 {
1031         struct xsdfec_dev *xsdfec;
1032         struct device *dev;
1033         struct device *dev_create;
1034         struct resource *res;
1035         int err;
1036         bool irq_enabled = true;
1037
1038         xsdfec = devm_kzalloc(&pdev->dev, sizeof(*xsdfec), GFP_KERNEL);
1039         if (!xsdfec)
1040                 return -ENOMEM;
1041
1042         xsdfec->dev = &pdev->dev;
1043         if (atomic_read(&xsdfec_ndevs) > DRIVER_MAX_DEV) {
1044                 dev_err(&pdev->dev,
1045                         "Cannot instantiate more than %d SDFEC instances",
1046                         (DRIVER_MAX_DEV + 1));
1047                 return -EINVAL;
1048         }
1049
1050         xsdfec->fec_id = atomic_read(&xsdfec_ndevs);
1051
1052         dev = xsdfec->dev;
1053         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1054         xsdfec->regs = devm_ioremap_resource(dev, res);
1055         if (IS_ERR(xsdfec->regs)) {
1056                 dev_err(dev, "Unable to map resource");
1057                 err = PTR_ERR(xsdfec->regs);
1058                 goto err_xsdfec_dev;
1059         }
1060
1061         xsdfec->irq = platform_get_irq(pdev, 0);
1062         if (xsdfec->irq < 0) {
1063                 dev_dbg(dev, "platform_get_irq failed");
1064                 irq_enabled = false;
1065         }
1066
1067         err = xsdfec_parse_of(xsdfec);
1068         if (err < 0)
1069                 goto err_xsdfec_dev;
1070
1071         /* Save driver private data */
1072         platform_set_drvdata(pdev, xsdfec);
1073
1074         if (irq_enabled) {
1075                 init_waitqueue_head(&xsdfec->waitq);
1076                 /* Register IRQ thread */
1077                 err = devm_request_threaded_irq(dev, xsdfec->irq, NULL,
1078                                                 xsdfec_irq_thread,
1079                                                 IRQF_ONESHOT,
1080                                                 "xilinx-sdfec16",
1081                                                 xsdfec);
1082                 if (err < 0) {
1083                         dev_err(dev, "unable to request IRQ%d", xsdfec->irq);
1084                         goto err_xsdfec_dev;
1085                 }
1086         }
1087
1088         cdev_init(&xsdfec->xsdfec_cdev, &xsdfec_fops);
1089         xsdfec->xsdfec_cdev.owner = THIS_MODULE;
1090         err = cdev_add(&xsdfec->xsdfec_cdev,
1091                        MKDEV(MAJOR(xsdfec_devt), xsdfec->fec_id), 1);
1092         if (err < 0) {
1093                 dev_err(dev, "cdev_add failed");
1094                 err = -EIO;
1095                 goto err_xsdfec_dev;
1096         }
1097
1098         if (!xsdfec_class) {
1099                 err = -EIO;
1100                 dev_err(dev, "xsdfec class not created correctly");
1101                 goto err_xsdfec_cdev;
1102         }
1103
1104         dev_create = device_create(xsdfec_class, dev,
1105                                    MKDEV(MAJOR(xsdfec_devt), xsdfec->fec_id),
1106                                    xsdfec, "xsdfec%d", xsdfec->fec_id);
1107         if (IS_ERR(dev_create)) {
1108                 dev_err(dev, "unable to create device");
1109                 err = PTR_ERR(dev_create);
1110                 goto err_xsdfec_cdev;
1111         }
1112
1113         atomic_set(&xsdfec->open_count, 1);
1114         dev_info(dev, "XSDFEC%d Probe Successful", xsdfec->fec_id);
1115         atomic_inc(&xsdfec_ndevs);
1116         return 0;
1117
1118         /* Failure cleanup */
1119 err_xsdfec_cdev:
1120         cdev_del(&xsdfec->xsdfec_cdev);
1121 err_xsdfec_dev:
1122         return err;
1123 }
1124
1125 static int
1126 xsdfec_remove(struct platform_device *pdev)
1127 {
1128         struct xsdfec_dev *xsdfec;
1129         struct device *dev = &pdev->dev;
1130
1131         xsdfec = platform_get_drvdata(pdev);
1132         if (!xsdfec)
1133                 return -ENODEV;
1134         dev = xsdfec->dev;
1135         if (!xsdfec_class) {
1136                 dev_err(dev, "xsdfec_class is NULL");
1137                 return -EIO;
1138         }
1139
1140         device_destroy(xsdfec_class,
1141                        MKDEV(MAJOR(xsdfec_devt), xsdfec->fec_id));
1142         cdev_del(&xsdfec->xsdfec_cdev);
1143         atomic_dec(&xsdfec_ndevs);
1144         return 0;
1145 }
1146
1147 static const struct of_device_id xsdfec_of_match[] = {
1148         { .compatible = "xlnx,fec-engine", },
1149         { /* end of table */ }
1150 };
1151 MODULE_DEVICE_TABLE(of, xsdfec_of_match);
1152
1153 static struct platform_driver xsdfec_driver = {
1154         .driver = {
1155                 .name = "xilinx-sdfec",
1156                 .of_match_table = xsdfec_of_match,
1157         },
1158         .probe = xsdfec_probe,
1159         .remove =  xsdfec_remove,
1160 };
1161
1162 static int __init xsdfec_init_mod(void)
1163 {
1164         int err;
1165
1166         xsdfec_class = class_create(THIS_MODULE, DRIVER_NAME);
1167         if (IS_ERR(xsdfec_class)) {
1168                 err = PTR_ERR(xsdfec_class);
1169                 pr_err("%s : Unable to register xsdfec class", __func__);
1170                 return err;
1171         }
1172
1173         err = alloc_chrdev_region(&xsdfec_devt,
1174                                   0, DRIVER_MAX_DEV, DRIVER_NAME);
1175         if (err < 0) {
1176                 pr_err("%s : Unable to get major number", __func__);
1177                 goto err_xsdfec_class;
1178         }
1179
1180         err = platform_driver_register(&xsdfec_driver);
1181         if (err < 0) {
1182                 pr_err("%s Unabled to register %s driver",
1183                        __func__, DRIVER_NAME);
1184                 goto err_xsdfec_drv;
1185         }
1186         return 0;
1187
1188         /* Error Path */
1189 err_xsdfec_drv:
1190         unregister_chrdev_region(xsdfec_devt, DRIVER_MAX_DEV);
1191 err_xsdfec_class:
1192         class_destroy(xsdfec_class);
1193         return err;
1194 }
1195
1196 static void __exit xsdfec_cleanup_mod(void)
1197 {
1198         platform_driver_unregister(&xsdfec_driver);
1199         unregister_chrdev_region(xsdfec_devt, DRIVER_MAX_DEV);
1200         class_destroy(xsdfec_class);
1201         xsdfec_class = NULL;
1202 }
1203
1204 module_init(xsdfec_init_mod);
1205 module_exit(xsdfec_cleanup_mod);
1206
1207 MODULE_AUTHOR("Xilinx, Inc");
1208 MODULE_DESCRIPTION("Xilinx SD-FEC16 Driver");
1209 MODULE_LICENSE("GPL");
1210 MODULE_VERSION(DRIVER_VERSION);