arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU106
   4  *
   5  * (C) Copyright 2016, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU106 RevA";
  20         compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <108>; /* down */
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &can1 {
  71         status = "okay";
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_can1_default>;
  74 };
  75
  76 &dcc {
  77         status = "okay";
  78 };
  79
  80 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  81 &fpd_dma_chan1 {
  82         status = "okay";
  83 };
  84
  85 &fpd_dma_chan2 {
  86         status = "okay";
  87 };
  88
  89 &fpd_dma_chan3 {
  90         status = "okay";
  91 };
  92
  93 &fpd_dma_chan4 {
  94         status = "okay";
  95 };
  96
  97 &fpd_dma_chan5 {
  98         status = "okay";
  99 };
 100
 101 &fpd_dma_chan6 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan7 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan8 {
 110         status = "okay";
 111 };
 112
 113 &gem3 {
 114         status = "okay";
 115         phy-handle = <&phy0>;
 116         phy-mode = "rgmii-id";
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gem3_default>;
 119         phy0: phy@c {
 120                 reg = <0xc>;
 121                 ti,rx-internal-delay = <0x8>;
 122                 ti,tx-internal-delay = <0xa>;
 123                 ti,fifo-depth = <0x1>;
 124                 ti,rxctrl-strap-worka;
 125         };
 126 };
 127
 128 &gpio {
 129         status = "okay";
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_gpio_default>;
 132 };
 133
 134 &gpu {
 135         status = "okay";
 136 };
 137
 138 &i2c0 {
 139         status = "okay";
 140         clock-frequency = <400000>;
 141         pinctrl-names = "default", "gpio";
 142         pinctrl-0 = <&pinctrl_i2c0_default>;
 143         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 144         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 145         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 146
 147         tca6416_u97: gpio@20 {
 148                 /*
 149                  * Enable all GTs to out from U-Boot
 150                  * i2c mw 20 6 0  - setup IO to output
 151                  * i2c mw 20 2 ef - setup output values on pins 0-7
 152                  * i2c mw 20 3 ff - setup output values on pins 10-17
 153                  */
 154                 compatible = "ti,tca6416";
 155                 reg = <0x20>;
 156                 gpio-controller; /* interrupt not connected */
 157                 #gpio-cells = <2>;
 158                 /*
 159                  * IRQ not connected
 160                  * Lines:
 161                  * 0 - SFP_SI5328_INT_ALM
 162                  * 1 - HDMI_SI5328_INT_ALM
 163                  * 5 - IIC_MUX_RESET_B
 164                  * 6 - GEM3_EXP_RESET_B
 165                  * 10 - FMC_HPC0_PRSNT_M2C_B
 166                  * 11 - FMC_HPC1_PRSNT_M2C_B
 167                  * 2-4, 7, 12-17 - not connected
 168                  */
 169         };
 170
 171         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 172                 compatible = "ti,tca6416";
 173                 reg = <0x21>;
 174                 gpio-controller;
 175                 #gpio-cells = <2>;
 176                 /*
 177                  * IRQ not connected
 178                  * Lines:
 179                  * 0 - VCCPSPLL_EN
 180                  * 1 - MGTRAVCC_EN
 181                  * 2 - MGTRAVTT_EN
 182                  * 3 - VCCPSDDRPLL_EN
 183                  * 4 - MIO26_PMU_INPUT_LS
 184                  * 5 - PL_PMBUS_ALERT
 185                  * 6 - PS_PMBUS_ALERT
 186                  * 7 - MAXIM_PMBUS_ALERT
 187                  * 10 - PL_DDR4_VTERM_EN
 188                  * 11 - PL_DDR4_VPP_2V5_EN
 189                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 190                  * 13 - PS_DIMM_SUSPEND_EN
 191                  * 14 - PS_DDR4_VTERM_EN
 192                  * 15 - PS_DDR4_VPP_2V5_EN
 193                  * 16 - 17 - not connected
 194                  */
 195         };
 196
 197         i2cswitch@75 { /* u60 */
 198                 compatible = "nxp,pca9544";
 199                 #address-cells = <1>;
 200                 #size-cells = <0>;
 201                 reg = <0x75>;
 202                 i2c@0 { /* i2c mw 75 0 1 */
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         reg = <0>;
 206                         /* PS_PMBUS */
 207                         ina226@40 { /* u76 */
 208                                 compatible = "ti,ina226";
 209                                 reg = <0x40>;
 210                                 shunt-resistor = <5000>;
 211                         };
 212                         ina226@41 { /* u77 */
 213                                 compatible = "ti,ina226";
 214                                 reg = <0x41>;
 215                                 shunt-resistor = <5000>;
 216                         };
 217                         ina226@42 { /* u78 */
 218                                 compatible = "ti,ina226";
 219                                 reg = <0x42>;
 220                                 shunt-resistor = <5000>;
 221                         };
 222                         ina226@43 { /* u87 */
 223                                 compatible = "ti,ina226";
 224                                 reg = <0x43>;
 225                                 shunt-resistor = <5000>;
 226                         };
 227                         ina226@44 { /* u85 */
 228                                 compatible = "ti,ina226";
 229                                 reg = <0x44>;
 230                                 shunt-resistor = <5000>;
 231                         };
 232                         ina226@45 { /* u86 */
 233                                 compatible = "ti,ina226";
 234                                 reg = <0x45>;
 235                                 shunt-resistor = <5000>;
 236                         };
 237                         ina226@46 { /* u93 */
 238                                 compatible = "ti,ina226";
 239                                 reg = <0x46>;
 240                                 shunt-resistor = <5000>;
 241                         };
 242                         ina226@47 { /* u88 */
 243                                 compatible = "ti,ina226";
 244                                 reg = <0x47>;
 245                                 shunt-resistor = <5000>;
 246                         };
 247                         ina226@4a { /* u15 */
 248                                 compatible = "ti,ina226";
 249                                 reg = <0x4a>;
 250                                 shunt-resistor = <5000>;
 251                         };
 252                         ina226@4b { /* u92 */
 253                                 compatible = "ti,ina226";
 254                                 reg = <0x4b>;
 255                                 shunt-resistor = <5000>;
 256                         };
 257                 };
 258                 i2c@1 { /* i2c mw 75 0 1 */
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         reg = <1>;
 262                         /* PL_PMBUS */
 263                         ina226@40 { /* u79 */
 264                                 compatible = "ti,ina226";
 265                                 reg = <0x40>;
 266                                 shunt-resistor = <2000>;
 267                         };
 268                         ina226@41 { /* u81 */
 269                                 compatible = "ti,ina226";
 270                                 reg = <0x41>;
 271                                 shunt-resistor = <5000>;
 272                         };
 273                         ina226@42 { /* u80 */
 274                                 compatible = "ti,ina226";
 275                                 reg = <0x42>;
 276                                 shunt-resistor = <5000>;
 277                         };
 278                         ina226@43 { /* u84 */
 279                                 compatible = "ti,ina226";
 280                                 reg = <0x43>;
 281                                 shunt-resistor = <5000>;
 282                         };
 283                         ina226@44 { /* u16 */
 284                                 compatible = "ti,ina226";
 285                                 reg = <0x44>;
 286                                 shunt-resistor = <5000>;
 287                         };
 288                         ina226@45 { /* u65 */
 289                                 compatible = "ti,ina226";
 290                                 reg = <0x45>;
 291                                 shunt-resistor = <5000>;
 292                         };
 293                         ina226@46 { /* u74 */
 294                                 compatible = "ti,ina226";
 295                                 reg = <0x46>;
 296                                 shunt-resistor = <5000>;
 297                         };
 298                         ina226@47 { /* u75 */
 299                                 compatible = "ti,ina226";
 300                                 reg = <0x47>;
 301                                 shunt-resistor = <5000>;
 302                         };
 303                 };
 304                 i2c@2 { /* i2c mw 75 0 1 */
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                         reg = <2>;
 308                         /* MAXIM_PMBUS - 00 */
 309                         max15301@a { /* u46 */
 310                                 compatible = "max15301";
 311                                 reg = <0xa>;
 312                         };
 313                         max15303@b { /* u4 */
 314                                 compatible = "max15303";
 315                                 reg = <0xb>;
 316                         };
 317                         max15303@10 { /* u13 */
 318                                 compatible = "max15303";
 319                                 reg = <0x10>;
 320                         };
 321                         max15301@13 { /* u47 */
 322                                 compatible = "max15301";
 323                                 reg = <0x13>;
 324                         };
 325                         max15303@14 { /* u7 */
 326                                 compatible = "max15303";
 327                                 reg = <0x14>;
 328                         };
 329                         max15303@15 { /* u6 */
 330                                 compatible = "max15303";
 331                                 reg = <0x15>;
 332                         };
 333                         max15303@16 { /* u10 */
 334                                 compatible = "max15303";
 335                                 reg = <0x16>;
 336                         };
 337                         max15303@17 { /* u9 */
 338                                 compatible = "max15303";
 339                                 reg = <0x17>;
 340                         };
 341                         max15301@18 { /* u63 */
 342                                 compatible = "max15301";
 343                                 reg = <0x18>;
 344                         };
 345                         max15303@1a { /* u49 */
 346                                 compatible = "max15303";
 347                                 reg = <0x1a>;
 348                         };
 349                         max15303@1b { /* u8 */
 350                                 compatible = "max15303";
 351                                 reg = <0x1b>;
 352                         };
 353                         max15303@1d { /* u18 */
 354                                 compatible = "max15303";
 355                                 reg = <0x1d>;
 356                         };
 357
 358                         max20751@72 { /* u95 */
 359                                 compatible = "max20751";
 360                                 reg = <0x72>;
 361                         };
 362                         max20751@73 { /* u96 */
 363                                 compatible = "max20751";
 364                                 reg = <0x73>;
 365                         };
 366                 };
 367                 /* Bus 3 is not connected */
 368         };
 369
 370         /* FIXME PMOD - j160 */
 371         /* FIXME MSP430F - u41 - not detected */
 372 };
 373
 374 &i2c1 {
 375         status = "okay";
 376         clock-frequency = <400000>;
 377         pinctrl-names = "default", "gpio";
 378         pinctrl-0 = <&pinctrl_i2c1_default>;
 379         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 380         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 381         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 382
 383         /* FIXME PL i2c via PCA9306 - u45 */
 384         /* FIXME MSP430 - u41 - not detected */
 385         i2cswitch@74 { /* u34 */
 386                 compatible = "nxp,pca9548";
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 reg = <0x74>;
 390                 i2c@0 { /* i2c mw 74 0 1 */
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         reg = <0>;
 394                         /*
 395                          * IIC_EEPROM 1kB memory which uses 256B blocks
 396                          * where every block has different address.
 397                          *    0 - 256B address 0x54
 398                          * 256B - 512B address 0x55
 399                          * 512B - 768B address 0x56
 400                          * 768B - 1024B address 0x57
 401                          */
 402                         eeprom@54 { /* u23 */
 403                                 compatible = "at,24c08";
 404                                 reg = <0x54>;
 405                         };
 406                 };
 407                 i2c@1 { /* i2c mw 74 0 2 */
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         reg = <1>;
 411                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 412                                 compatible = "si5341";
 413                                 reg = <0x36>;
 414                         };
 415
 416                 };
 417                 i2c@2 { /* i2c mw 74 0 4 */
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         reg = <2>;
 421                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 422                                 #clock-cells = <0>;
 423                                 compatible = "silabs,si570";
 424                                 reg = <0x5d>;
 425                                 temperature-stability = <50>;
 426                                 factory-fout = <300000000>;
 427                                 clock-frequency = <300000000>;
 428                         };
 429                 };
 430                 i2c@3 { /* i2c mw 74 0 8 */
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         reg = <3>;
 434                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 435                                 #clock-cells = <0>;
 436                                 compatible = "silabs,si570";
 437                                 reg = <0x5d>;
 438                                 temperature-stability = <50>; /* copy from zc702 */
 439                                 factory-fout = <156250000>;
 440                                 clock-frequency = <148500000>;
 441                         };
 442                 };
 443                 i2c@4 { /* i2c mw 74 0 10 */
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         reg = <4>;
 447                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 448                                 compatible = "silabs,si5328";
 449                                 reg = <0x69>;
 450                         };
 451                 };
 452                 i2c@5 { /* i2c mw 74 0 11 */
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         reg = <5>; /* FAN controller */
 456                         temp@4c {/* lm96163 - u128 */
 457                                 compatible = "national,lm96163";
 458                                 reg = <0x4c>; /* FIXME */
 459                         };
 460                 };
 461                 /* 6 - 7 unconnected */
 462         };
 463
 464         i2cswitch@75 {
 465                 compatible = "nxp,pca9548"; /* u135 */
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 reg = <0x75>;
 469
 470                 i2c@0 {
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         reg = <0>;
 474                         /* HPC0_IIC */
 475                 };
 476                 i2c@1 {
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         reg = <1>;
 480                         /* HPC1_IIC */
 481                 };
 482                 i2c@2 {
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <2>;
 486                         /* SYSMON */
 487                 };
 488                 i2c@3 { /* i2c mw 75 0 8 */
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         reg = <3>;
 492                         /* DDR4 SODIMM */
 493                         dev@19 { /* u-boot detection */
 494                                 compatible = "xxx";
 495                                 reg = <0x19>;
 496                         };
 497                         dev@30 { /* u-boot detection */
 498                                 compatible = "xxx";
 499                                 reg = <0x30>;
 500                         };
 501                         dev@35 { /* u-boot detection */
 502                                 compatible = "xxx";
 503                                 reg = <0x35>;
 504                         };
 505                         dev@36 { /* u-boot detection */
 506                                 compatible = "xxx";
 507                                 reg = <0x36>;
 508                         };
 509                         dev@51 { /* u-boot detection - maybe SPD */
 510                                 compatible = "xxx";
 511                                 reg = <0x51>;
 512                         };
 513                 };
 514                 i2c@4 {
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         reg = <4>;
 518                         /* SEP 3 */
 519                 };
 520                 i2c@5 {
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         reg = <5>;
 524                         /* SEP 2 */
 525                 };
 526                 i2c@6 {
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         reg = <6>;
 530                         /* SEP 1 */
 531                 };
 532                 i2c@7 {
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         reg = <7>;
 536                         /* SEP 0 */
 537                 };
 538         };
 539 };
 540
 541 &pinctrl0 {
 542         status = "okay";
 543         pinctrl_i2c0_default: i2c0-default {
 544                 mux {
 545                         groups = "i2c0_3_grp";
 546                         function = "i2c0";
 547                 };
 548
 549                 conf {
 550                         groups = "i2c0_3_grp";
 551                         bias-pull-up;
 552                         slew-rate = <SLEW_RATE_SLOW>;
 553                         io-standard = <IO_STANDARD_LVCMOS18>;
 554                 };
 555         };
 556
 557         pinctrl_i2c0_gpio: i2c0-gpio {
 558                 mux {
 559                         groups = "gpio0_14_grp", "gpio0_15_grp";
 560                         function = "gpio0";
 561                 };
 562
 563                 conf {
 564                         groups = "gpio0_14_grp", "gpio0_15_grp";
 565                         slew-rate = <SLEW_RATE_SLOW>;
 566                         io-standard = <IO_STANDARD_LVCMOS18>;
 567                 };
 568         };
 569
 570         pinctrl_i2c1_default: i2c1-default {
 571                 mux {
 572                         groups = "i2c1_4_grp";
 573                         function = "i2c1";
 574                 };
 575
 576                 conf {
 577                         groups = "i2c1_4_grp";
 578                         bias-pull-up;
 579                         slew-rate = <SLEW_RATE_SLOW>;
 580                         io-standard = <IO_STANDARD_LVCMOS18>;
 581                 };
 582         };
 583
 584         pinctrl_i2c1_gpio: i2c1-gpio {
 585                 mux {
 586                         groups = "gpio0_16_grp", "gpio0_17_grp";
 587                         function = "gpio0";
 588                 };
 589
 590                 conf {
 591                         groups = "gpio0_16_grp", "gpio0_17_grp";
 592                         slew-rate = <SLEW_RATE_SLOW>;
 593                         io-standard = <IO_STANDARD_LVCMOS18>;
 594                 };
 595         };
 596
 597         pinctrl_uart0_default: uart0-default {
 598                 mux {
 599                         groups = "uart0_4_grp";
 600                         function = "uart0";
 601                 };
 602
 603                 conf {
 604                         groups = "uart0_4_grp";
 605                         slew-rate = <SLEW_RATE_SLOW>;
 606                         io-standard = <IO_STANDARD_LVCMOS18>;
 607                 };
 608
 609                 conf-rx {
 610                         pins = "MIO18";
 611                         bias-high-impedance;
 612                 };
 613
 614                 conf-tx {
 615                         pins = "MIO19";
 616                         bias-disable;
 617                 };
 618         };
 619
 620         pinctrl_uart1_default: uart1-default {
 621                 mux {
 622                         groups = "uart1_5_grp";
 623                         function = "uart1";
 624                 };
 625
 626                 conf {
 627                         groups = "uart1_5_grp";
 628                         slew-rate = <SLEW_RATE_SLOW>;
 629                         io-standard = <IO_STANDARD_LVCMOS18>;
 630                 };
 631
 632                 conf-rx {
 633                         pins = "MIO21";
 634                         bias-high-impedance;
 635                 };
 636
 637                 conf-tx {
 638                         pins = "MIO20";
 639                         bias-disable;
 640                 };
 641         };
 642
 643         pinctrl_usb0_default: usb0-default {
 644                 mux {
 645                         groups = "usb0_0_grp";
 646                         function = "usb0";
 647                 };
 648
 649                 conf {
 650                         groups = "usb0_0_grp";
 651                         slew-rate = <SLEW_RATE_SLOW>;
 652                         io-standard = <IO_STANDARD_LVCMOS18>;
 653                 };
 654
 655                 conf-rx {
 656                         pins = "MIO52", "MIO53", "MIO55";
 657                         bias-high-impedance;
 658                 };
 659
 660                 conf-tx {
 661                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 662                                "MIO60", "MIO61", "MIO62", "MIO63";
 663                         bias-disable;
 664                 };
 665         };
 666
 667         pinctrl_gem3_default: gem3-default {
 668                 mux {
 669                         function = "ethernet3";
 670                         groups = "ethernet3_0_grp";
 671                 };
 672
 673                 conf {
 674                         groups = "ethernet3_0_grp";
 675                         slew-rate = <SLEW_RATE_SLOW>;
 676                         io-standard = <IO_STANDARD_LVCMOS18>;
 677                 };
 678
 679                 conf-rx {
 680                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 681                                                                         "MIO75";
 682                         bias-high-impedance;
 683                         low-power-disable;
 684                 };
 685
 686                 conf-tx {
 687                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 688                                                                         "MIO69";
 689                         bias-disable;
 690                         low-power-enable;
 691                 };
 692
 693                 mux-mdio {
 694                         function = "mdio3";
 695                         groups = "mdio3_0_grp";
 696                 };
 697
 698                 conf-mdio {
 699                         groups = "mdio3_0_grp";
 700                         slew-rate = <SLEW_RATE_SLOW>;
 701                         io-standard = <IO_STANDARD_LVCMOS18>;
 702                         bias-disable;
 703                 };
 704         };
 705
 706         pinctrl_can1_default: can1-default {
 707                 mux {
 708                         function = "can1";
 709                         groups = "can1_6_grp";
 710                 };
 711
 712                 conf {
 713                         groups = "can1_6_grp";
 714                         slew-rate = <SLEW_RATE_SLOW>;
 715                         io-standard = <IO_STANDARD_LVCMOS18>;
 716                 };
 717
 718                 conf-rx {
 719                         pins = "MIO25";
 720                         bias-high-impedance;
 721                 };
 722
 723                 conf-tx {
 724                         pins = "MIO24";
 725                         bias-disable;
 726                 };
 727         };
 728
 729         pinctrl_sdhci1_default: sdhci1-default {
 730                 mux {
 731                         groups = "sdio1_0_grp";
 732                         function = "sdio1";
 733                 };
 734
 735                 conf {
 736                         groups = "sdio1_0_grp";
 737                         slew-rate = <SLEW_RATE_SLOW>;
 738                         io-standard = <IO_STANDARD_LVCMOS18>;
 739                         bias-disable;
 740                 };
 741
 742                 mux-cd {
 743                         groups = "sdio1_cd_0_grp";
 744                         function = "sdio1_cd";
 745                 };
 746
 747                 conf-cd {
 748                         groups = "sdio1_cd_0_grp";
 749                         bias-high-impedance;
 750                         bias-pull-up;
 751                         slew-rate = <SLEW_RATE_SLOW>;
 752                         io-standard = <IO_STANDARD_LVCMOS18>;
 753                 };
 754
 755                 mux-wp {
 756                         groups = "sdio1_wp_0_grp";
 757                         function = "sdio1_wp";
 758                 };
 759
 760                 conf-wp {
 761                         groups = "sdio1_wp_0_grp";
 762                         bias-high-impedance;
 763                         bias-pull-up;
 764                         slew-rate = <SLEW_RATE_SLOW>;
 765                         io-standard = <IO_STANDARD_LVCMOS18>;
 766                 };
 767         };
 768
 769         pinctrl_gpio_default: gpio-default {
 770                 mux {
 771                         function = "gpio0";
 772                         groups = "gpio0_22_grp", "gpio0_23_grp";
 773                 };
 774
 775                 conf {
 776                         groups = "gpio0_22_grp", "gpio0_23_grp";
 777                         slew-rate = <SLEW_RATE_SLOW>;
 778                         io-standard = <IO_STANDARD_LVCMOS18>;
 779                 };
 780
 781                 mux-msp {
 782                         function = "gpio0";
 783                         groups = "gpio0_13_grp", "gpio0_38_grp";
 784                 };
 785
 786                 conf-msp {
 787                         groups = "gpio0_13_grp", "gpio0_38_grp";
 788                         slew-rate = <SLEW_RATE_SLOW>;
 789                         io-standard = <IO_STANDARD_LVCMOS18>;
 790                 };
 791
 792                 conf-pull-up {
 793                         pins = "MIO22";
 794                         bias-pull-up;
 795                 };
 796
 797                 conf-pull-none {
 798                         pins = "MIO13", "MIO23", "MIO38";
 799                         bias-disable;
 800                 };
 801         };
 802 };
 803
 804 &qspi {
 805         status = "okay";
 806         is-dual = <1>;
 807         flash@0 {
 808                 compatible = "m25p80"; /* 32MB */
 809                 #address-cells = <1>;
 810                 #size-cells = <1>;
 811                 reg = <0x0>;
 812                 spi-tx-bus-width = <1>;
 813                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 814                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 815                 partition@qspi-fsbl-uboot { /* for testing purpose */
 816                         label = "qspi-fsbl-uboot";
 817                         reg = <0x0 0x100000>;
 818                 };
 819                 partition@qspi-linux { /* for testing purpose */
 820                         label = "qspi-linux";
 821                         reg = <0x100000 0x500000>;
 822                 };
 823                 partition@qspi-device-tree { /* for testing purpose */
 824                         label = "qspi-device-tree";
 825                         reg = <0x600000 0x20000>;
 826                 };
 827                 partition@qspi-rootfs { /* for testing purpose */
 828                         label = "qspi-rootfs";
 829                         reg = <0x620000 0x5E0000>;
 830                 };
 831         };
 832 };
 833
 834 &rtc {
 835         status = "okay";
 836 };
 837
 838 &sata {
 839         status = "okay";
 840         /* SATA OOB timing settings */
 841         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 842         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 843         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 844         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 845         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 846         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 847         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 848         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 849         phy-names = "sata-phy";
 850         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 851 };
 852
 853 /* SD1 with level shifter */
 854 &sdhci1 {
 855         status = "okay";
 856         pinctrl-names = "default";
 857         pinctrl-0 = <&pinctrl_sdhci1_default>;
 858         no-1-8-v;
 859         xlnx,mio_bank = <1>;
 860 };
 861
 862 &serdes {
 863         status = "okay";
 864 };
 865
 866 &uart0 {
 867         status = "okay";
 868         pinctrl-names = "default";
 869         pinctrl-0 = <&pinctrl_uart0_default>;
 870 };
 871
 872 &uart1 {
 873         status = "okay";
 874         pinctrl-names = "default";
 875         pinctrl-0 = <&pinctrl_uart1_default>;
 876 };
 877
 878 /* ULPI SMSC USB3320 */
 879 &usb0 {
 880         status = "okay";
 881         pinctrl-names = "default";
 882         pinctrl-0 = <&pinctrl_usb0_default>;
 883 };
 884
 885 &dwc3_0 {
 886         status = "okay";
 887         dr_mode = "host";
 888         snps,usb3_lpm_capable;
 889         phy-names = "usb3-phy";
 890         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 891 };
 892
 893 &zynqmp_dpsub {
 894         status = "okay";
 895         phy-names = "dp-phy0", "dp-phy1";
 896         phys = <&lane1 PHY_TYPE_DP 0 3 27000000>, <&lane0 PHY_TYPE_DP 1 3 27000000>;
 897 };
 898
 899 &zynqmp_dp_snd_pcm0 {
 900         status = "okay";
 901 };
 902
 903 &zynqmp_dp_snd_pcm1 {
 904         status = "okay";
 905 };
 906
 907 &zynqmp_dp_snd_card0 {
 908         status = "okay";
 909 };
 910
 911 &zynqmp_dp_snd_codec0 {
 912         status = "okay";
 913 };
 914
 915 &xlnx_dpdma {
 916         status = "okay";
 917 };