2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/pm_runtime.h>
35 #define CDNS_UART_TTY_NAME "ttyPS"
36 #define CDNS_UART_NAME "xuartps"
37 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
38 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
39 #define CDNS_UART_NR_PORTS CONFIG_SERIAL_XILINX_NR_UARTS
40 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
41 #define CDNS_UART_REGISTER_SPACE 0x1000
43 /* Rx Trigger level */
44 static int rx_trigger_level = 56;
45 module_param(rx_trigger_level, uint, 0444);
46 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
49 static int rx_timeout = 10;
50 module_param(rx_timeout, uint, 0444);
51 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
53 /* Register offsets for the UART. */
54 #define CDNS_UART_CR 0x00 /* Control Register */
55 #define CDNS_UART_MR 0x04 /* Mode Register */
56 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
57 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
58 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
59 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
60 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
61 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
62 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
63 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
64 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
65 #define CDNS_UART_SR 0x2C /* Channel Status */
66 #define CDNS_UART_FIFO 0x30 /* FIFO */
67 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
68 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
69 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
70 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
71 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
72 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
74 /* Control Register Bit Definitions */
75 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
76 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
77 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
78 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
79 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
80 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
81 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
82 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
83 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
84 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
85 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
86 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
90 * The mode register (MR) defines the mode of transfer as well as the data
91 * format. If this register is modified during transmission or reception,
92 * data validity cannot be guaranteed.
94 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
95 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
96 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
97 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
99 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
100 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
102 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
103 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
104 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
105 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
106 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
108 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
109 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
110 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
113 * Interrupt Registers:
114 * Interrupt control logic uses the interrupt enable register (IER) and the
115 * interrupt disable register (IDR) to set the value of the bits in the
116 * interrupt mask register (IMR). The IMR determines whether to pass an
117 * interrupt to the interrupt status register (ISR).
118 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
119 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
120 * Reading either IER or IDR returns 0x00.
121 * All four registers have the same bit definitions.
123 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
124 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
125 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
126 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
127 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
128 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
129 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
130 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
131 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
132 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
133 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
136 * Do not enable parity error interrupt for the following
137 * reason: When parity error interrupt is enabled, each Rx
138 * parity error always results in 2 events. The first one
139 * being parity error interrupt and the second one with a
140 * proper Rx interrupt with the incoming data. Disabling
141 * parity error interrupt ensures better handling of parity
142 * error events. With this change, for a parity error case, we
143 * get a Rx interrupt with parity error set in ISR register
144 * and we still handle parity errors in the desired way.
147 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
148 CDNS_UART_IXR_OVERRUN | \
149 CDNS_UART_IXR_RXTRIG | \
152 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
153 #define CDNS_UART_IXR_BRK 0x00002000
155 #define CDNS_UART_RXBS_SUPPORT BIT(1)
157 * Modem Control register:
158 * The read/write Modem Control register controls the interface with the modem
159 * or data set, or a peripheral device emulating a modem.
161 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
162 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
163 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
166 * Channel Status Register:
167 * The channel status register (CSR) is provided to enable the control logic
168 * to monitor the status of bits in the channel interrupt status register,
169 * even if these are masked out by the interrupt mask register.
171 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
172 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
173 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
174 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
176 /* baud dividers min/max values */
177 #define CDNS_UART_BDIV_MIN 4
178 #define CDNS_UART_BDIV_MAX 255
179 #define CDNS_UART_CD_MAX 65535
180 #define UART_AUTOSUSPEND_TIMEOUT 3000
183 * struct cdns_uart - device data
184 * @port: Pointer to the UART port
185 * @uartclk: Reference clock
187 * @baud: Current baud rate
188 * @clk_rate_change_nb: Notifier block for clock changes
189 * @quirks: Flags for RXBS support.
192 struct uart_port *port;
196 struct notifier_block clk_rate_change_nb;
199 struct cdns_platform_data {
202 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
206 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
207 * @dev_id: Id of the UART port
208 * @isrstatus: The interrupt status register value as read
211 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
213 struct uart_port *port = (struct uart_port *)dev_id;
214 struct cdns_uart *cdns_uart = port->private_data;
216 unsigned int rxbs_status = 0;
217 unsigned int status_mask;
218 unsigned int framerrprocessed = 0;
219 char status = TTY_NORMAL;
220 bool is_rxbs_support;
222 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
224 while ((readl(port->membase + CDNS_UART_SR) &
225 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
227 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
228 data = readl(port->membase + CDNS_UART_FIFO);
231 * There is no hardware break detection in Zynq, so we interpret
232 * framing error with all-zeros data as a break sequence.
233 * Most of the time, there's another non-zero byte at the
234 * end of the sequence.
236 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
238 port->read_status_mask |= CDNS_UART_IXR_BRK;
239 framerrprocessed = 1;
243 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
246 if (uart_handle_break(port))
250 isrstatus &= port->read_status_mask;
251 isrstatus &= ~port->ignore_status_mask;
252 status_mask = port->read_status_mask;
253 status_mask &= ~port->ignore_status_mask;
256 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
257 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
259 if (uart_handle_break(port))
263 if (uart_handle_sysrq_char(port, data))
266 if (is_rxbs_support) {
267 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
268 && (status_mask & CDNS_UART_IXR_PARITY)) {
269 port->icount.parity++;
272 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
273 && (status_mask & CDNS_UART_IXR_PARITY)) {
274 port->icount.frame++;
278 if (isrstatus & CDNS_UART_IXR_PARITY) {
279 port->icount.parity++;
282 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
284 port->icount.frame++;
288 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
289 port->icount.overrun++;
290 tty_insert_flip_char(&port->state->port, 0,
293 tty_insert_flip_char(&port->state->port, data, status);
296 spin_unlock(&port->lock);
297 tty_flip_buffer_push(&port->state->port);
298 spin_lock(&port->lock);
302 * cdns_uart_handle_tx - Handle the bytes to be Txed.
303 * @dev_id: Id of the UART port
306 static void cdns_uart_handle_tx(void *dev_id)
308 struct uart_port *port = (struct uart_port *)dev_id;
309 unsigned int numbytes;
311 if (uart_circ_empty(&port->state->xmit)) {
312 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
314 numbytes = port->fifosize;
315 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
316 !(readl(port->membase + CDNS_UART_SR) &
317 CDNS_UART_SR_TXFULL)) {
319 * Get the data from the UART circular buffer
320 * and write it to the cdns_uart's TX_FIFO
324 port->state->xmit.buf[port->state->xmit.
325 tail], port->membase + CDNS_UART_FIFO);
330 * Adjust the tail of the UART buffer and wrap
331 * the buffer if it reaches limit.
333 port->state->xmit.tail =
334 (port->state->xmit.tail + 1) &
335 (UART_XMIT_SIZE - 1);
340 if (uart_circ_chars_pending(
341 &port->state->xmit) < WAKEUP_CHARS)
342 uart_write_wakeup(port);
347 * cdns_uart_isr - Interrupt handler
349 * @dev_id: Id of the port
353 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
355 struct uart_port *port = (struct uart_port *)dev_id;
356 unsigned int isrstatus;
358 spin_lock(&port->lock);
360 /* Read the interrupt status register to determine which
361 * interrupt(s) is/are active and clear them.
363 isrstatus = readl(port->membase + CDNS_UART_ISR);
364 writel(isrstatus, port->membase + CDNS_UART_ISR);
366 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
367 cdns_uart_handle_tx(dev_id);
368 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
370 if (isrstatus & CDNS_UART_IXR_RXMASK)
371 cdns_uart_handle_rx(dev_id, isrstatus);
373 spin_unlock(&port->lock);
378 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
379 * @clk: UART module input clock
380 * @baud: Desired baud rate
381 * @rbdiv: BDIV value (return value)
382 * @rcd: CD value (return value)
383 * @div8: Value for clk_sel bit in mod (return value)
384 * Return: baud rate, requested baud when possible, or actual baud when there
385 * was too much error, zero if no valid divisors are found.
387 * Formula to obtain baud rate is
388 * baud_tx/rx rate = clk/CD * (BDIV + 1)
389 * input_clk = (Uart User Defined Clock or Apb Clock)
390 * depends on UCLKEN in MR Reg
391 * clk = input_clk or input_clk/8;
392 * depends on CLKS in MR reg
393 * CD and BDIV depends on values in
394 * baud rate generate register
395 * baud rate clock divisor register
397 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
398 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
401 unsigned int calc_baud;
402 unsigned int bestbaud = 0;
403 unsigned int bauderror;
404 unsigned int besterror = ~0;
406 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
413 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
414 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
415 if (cd < 1 || cd > CDNS_UART_CD_MAX)
418 calc_baud = clk / (cd * (bdiv + 1));
420 if (baud > calc_baud)
421 bauderror = baud - calc_baud;
423 bauderror = calc_baud - baud;
425 if (besterror > bauderror) {
428 bestbaud = calc_baud;
429 besterror = bauderror;
432 /* use the values when percent error is acceptable */
433 if (((besterror * 100) / baud) < 3)
440 * cdns_uart_set_baud_rate - Calculate and set the baud rate
441 * @port: Handle to the uart port structure
442 * @baud: Baud rate to set
443 * Return: baud rate, requested baud when possible, or actual baud when there
444 * was too much error, zero if no valid divisors are found.
446 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
449 unsigned int calc_baud;
450 u32 cd = 0, bdiv = 0;
453 struct cdns_uart *cdns_uart = port->private_data;
455 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
458 /* Write new divisors to hardware */
459 mreg = readl(port->membase + CDNS_UART_MR);
461 mreg |= CDNS_UART_MR_CLKSEL;
463 mreg &= ~CDNS_UART_MR_CLKSEL;
464 writel(mreg, port->membase + CDNS_UART_MR);
465 writel(cd, port->membase + CDNS_UART_BAUDGEN);
466 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
467 cdns_uart->baud = baud;
472 #ifdef CONFIG_COMMON_CLK
474 * cdns_uart_clk_notitifer_cb - Clock notifier callback
475 * @nb: Notifier block
476 * @event: Notify event
477 * @data: Notifier data
478 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
480 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
481 unsigned long event, void *data)
484 struct uart_port *port;
486 struct clk_notifier_data *ndata = data;
487 unsigned long flags = 0;
488 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
490 port = cdns_uart->port;
495 case PRE_RATE_CHANGE:
501 * Find out if current baud-rate can be achieved with new clock
504 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
505 &bdiv, &cd, &div8)) {
506 dev_warn(port->dev, "clock rate change rejected\n");
510 spin_lock_irqsave(&cdns_uart->port->lock, flags);
512 /* Disable the TX and RX to set baud rate */
513 ctrl_reg = readl(port->membase + CDNS_UART_CR);
514 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
515 writel(ctrl_reg, port->membase + CDNS_UART_CR);
517 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
521 case POST_RATE_CHANGE:
523 * Set clk dividers to generate correct baud with new clock
527 spin_lock_irqsave(&cdns_uart->port->lock, flags);
530 port->uartclk = ndata->new_rate;
532 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
535 case ABORT_RATE_CHANGE:
537 spin_lock_irqsave(&cdns_uart->port->lock, flags);
539 /* Set TX/RX Reset */
540 ctrl_reg = readl(port->membase + CDNS_UART_CR);
541 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
542 writel(ctrl_reg, port->membase + CDNS_UART_CR);
544 while (readl(port->membase + CDNS_UART_CR) &
545 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
549 * Clear the RX disable and TX disable bits and then set the TX
550 * enable bit and RX enable bit to enable the transmitter and
553 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
554 ctrl_reg = readl(port->membase + CDNS_UART_CR);
555 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
556 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
557 writel(ctrl_reg, port->membase + CDNS_UART_CR);
559 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
569 * cdns_uart_start_tx - Start transmitting bytes
570 * @port: Handle to the uart port structure
572 static void cdns_uart_start_tx(struct uart_port *port)
576 if (uart_tx_stopped(port))
580 * Set the TX enable bit and clear the TX disable bit to enable the
583 status = readl(port->membase + CDNS_UART_CR);
584 status &= ~CDNS_UART_CR_TX_DIS;
585 status |= CDNS_UART_CR_TX_EN;
586 writel(status, port->membase + CDNS_UART_CR);
588 if (uart_circ_empty(&port->state->xmit))
591 cdns_uart_handle_tx(port);
593 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
594 /* Enable the TX Empty interrupt */
595 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
599 * cdns_uart_stop_tx - Stop TX
600 * @port: Handle to the uart port structure
602 static void cdns_uart_stop_tx(struct uart_port *port)
606 regval = readl(port->membase + CDNS_UART_CR);
607 regval |= CDNS_UART_CR_TX_DIS;
608 /* Disable the transmitter */
609 writel(regval, port->membase + CDNS_UART_CR);
613 * cdns_uart_stop_rx - Stop RX
614 * @port: Handle to the uart port structure
616 static void cdns_uart_stop_rx(struct uart_port *port)
620 /* Disable RX IRQs */
621 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
623 /* Disable the receiver */
624 regval = readl(port->membase + CDNS_UART_CR);
625 regval |= CDNS_UART_CR_RX_DIS;
626 writel(regval, port->membase + CDNS_UART_CR);
630 * cdns_uart_tx_empty - Check whether TX is empty
631 * @port: Handle to the uart port structure
633 * Return: TIOCSER_TEMT on success, 0 otherwise
635 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
639 status = readl(port->membase + CDNS_UART_SR) &
640 CDNS_UART_SR_TXEMPTY;
641 return status ? TIOCSER_TEMT : 0;
645 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
646 * transmitting char breaks
647 * @port: Handle to the uart port structure
648 * @ctl: Value based on which start or stop decision is taken
650 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
655 spin_lock_irqsave(&port->lock, flags);
657 status = readl(port->membase + CDNS_UART_CR);
660 writel(CDNS_UART_CR_STARTBRK | status,
661 port->membase + CDNS_UART_CR);
663 if ((status & CDNS_UART_CR_STOPBRK) == 0)
664 writel(CDNS_UART_CR_STOPBRK | status,
665 port->membase + CDNS_UART_CR);
667 spin_unlock_irqrestore(&port->lock, flags);
671 * cdns_uart_set_termios - termios operations, handling data length, parity,
672 * stop bits, flow control, baud rate
673 * @port: Handle to the uart port structure
674 * @termios: Handle to the input termios structure
675 * @old: Values of the previously saved termios structure
677 static void cdns_uart_set_termios(struct uart_port *port,
678 struct ktermios *termios, struct ktermios *old)
680 unsigned int cval = 0;
681 unsigned int baud, minbaud, maxbaud;
683 unsigned int ctrl_reg, mode_reg;
685 spin_lock_irqsave(&port->lock, flags);
687 /* Wait for the transmit FIFO to empty before making changes */
688 if (!(readl(port->membase + CDNS_UART_CR) &
689 CDNS_UART_CR_TX_DIS)) {
690 while (!(readl(port->membase + CDNS_UART_SR) &
691 CDNS_UART_SR_TXEMPTY)) {
696 /* Disable the TX and RX to set baud rate */
697 ctrl_reg = readl(port->membase + CDNS_UART_CR);
698 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
699 writel(ctrl_reg, port->membase + CDNS_UART_CR);
702 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
703 * min and max baud should be calculated here based on port->uartclk.
704 * this way we get a valid baud and can safely call set_baud()
706 minbaud = port->uartclk /
707 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
708 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
709 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
710 baud = cdns_uart_set_baud_rate(port, baud);
711 if (tty_termios_baud_rate(termios))
712 tty_termios_encode_baud_rate(termios, baud, baud);
714 /* Update the per-port timeout. */
715 uart_update_timeout(port, termios->c_cflag, baud);
717 /* Set TX/RX Reset */
718 ctrl_reg = readl(port->membase + CDNS_UART_CR);
719 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
720 writel(ctrl_reg, port->membase + CDNS_UART_CR);
722 while (readl(port->membase + CDNS_UART_CR) &
723 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
727 * Clear the RX disable and TX disable bits and then set the TX enable
728 * bit and RX enable bit to enable the transmitter and receiver.
730 ctrl_reg = readl(port->membase + CDNS_UART_CR);
731 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
732 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
733 writel(ctrl_reg, port->membase + CDNS_UART_CR);
735 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
737 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
738 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
739 port->ignore_status_mask = 0;
741 if (termios->c_iflag & INPCK)
742 port->read_status_mask |= CDNS_UART_IXR_PARITY |
743 CDNS_UART_IXR_FRAMING;
745 if (termios->c_iflag & IGNPAR)
746 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
747 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
749 /* ignore all characters if CREAD is not set */
750 if ((termios->c_cflag & CREAD) == 0)
751 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
752 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
753 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
755 mode_reg = readl(port->membase + CDNS_UART_MR);
757 /* Handling Data Size */
758 switch (termios->c_cflag & CSIZE) {
760 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
763 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
767 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
768 termios->c_cflag &= ~CSIZE;
769 termios->c_cflag |= CS8;
773 /* Handling Parity and Stop Bits length */
774 if (termios->c_cflag & CSTOPB)
775 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
777 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
779 if (termios->c_cflag & PARENB) {
780 /* Mark or Space parity */
781 if (termios->c_cflag & CMSPAR) {
782 if (termios->c_cflag & PARODD)
783 cval |= CDNS_UART_MR_PARITY_MARK;
785 cval |= CDNS_UART_MR_PARITY_SPACE;
787 if (termios->c_cflag & PARODD)
788 cval |= CDNS_UART_MR_PARITY_ODD;
790 cval |= CDNS_UART_MR_PARITY_EVEN;
793 cval |= CDNS_UART_MR_PARITY_NONE;
795 cval |= mode_reg & 1;
796 writel(cval, port->membase + CDNS_UART_MR);
798 spin_unlock_irqrestore(&port->lock, flags);
802 * cdns_uart_startup - Called when an application opens a cdns_uart port
803 * @port: Handle to the uart port structure
805 * Return: 0 on success, negative errno otherwise
807 static int cdns_uart_startup(struct uart_port *port)
809 struct cdns_uart *cdns_uart = port->private_data;
813 unsigned int status = 0;
815 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
817 spin_lock_irqsave(&port->lock, flags);
819 /* Disable the TX and RX */
820 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
821 port->membase + CDNS_UART_CR);
823 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
826 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
827 port->membase + CDNS_UART_CR);
829 while (readl(port->membase + CDNS_UART_CR) &
830 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
834 * Clear the RX disable bit and then set the RX enable bit to enable
837 status = readl(port->membase + CDNS_UART_CR);
838 status &= CDNS_UART_CR_RX_DIS;
839 status |= CDNS_UART_CR_RX_EN;
840 writel(status, port->membase + CDNS_UART_CR);
842 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
845 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
846 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
847 port->membase + CDNS_UART_MR);
850 * Set the RX FIFO Trigger level to use most of the FIFO, but it
851 * can be tuned with a module parameter
853 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
856 * Receive Timeout register is enabled but it
857 * can be tuned with a module parameter
859 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
861 /* Clear out any pending interrupts before enabling them */
862 writel(readl(port->membase + CDNS_UART_ISR),
863 port->membase + CDNS_UART_ISR);
865 spin_unlock_irqrestore(&port->lock, flags);
867 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
869 dev_err(port->dev, "request_irq '%d' failed with %d\n",
874 /* Set the Interrupt Registers with desired interrupts */
876 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
877 port->membase + CDNS_UART_IER);
879 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
885 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
886 * @port: Handle to the uart port structure
888 static void cdns_uart_shutdown(struct uart_port *port)
893 spin_lock_irqsave(&port->lock, flags);
895 /* Disable interrupts */
896 status = readl(port->membase + CDNS_UART_IMR);
897 writel(status, port->membase + CDNS_UART_IDR);
898 writel(0xffffffff, port->membase + CDNS_UART_ISR);
900 /* Disable the TX and RX */
901 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
902 port->membase + CDNS_UART_CR);
904 spin_unlock_irqrestore(&port->lock, flags);
906 free_irq(port->irq, port);
910 * cdns_uart_type - Set UART type to cdns_uart port
911 * @port: Handle to the uart port structure
913 * Return: string on success, NULL otherwise
915 static const char *cdns_uart_type(struct uart_port *port)
917 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
921 * cdns_uart_verify_port - Verify the port params
922 * @port: Handle to the uart port structure
923 * @ser: Handle to the structure whose members are compared
925 * Return: 0 on success, negative errno otherwise.
927 static int cdns_uart_verify_port(struct uart_port *port,
928 struct serial_struct *ser)
930 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
932 if (port->irq != ser->irq)
934 if (ser->io_type != UPIO_MEM)
936 if (port->iobase != ser->port)
944 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
945 * called when the driver adds a cdns_uart port via
946 * uart_add_one_port()
947 * @port: Handle to the uart port structure
949 * Return: 0 on success, negative errno otherwise.
951 static int cdns_uart_request_port(struct uart_port *port)
953 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
958 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
959 if (!port->membase) {
960 dev_err(port->dev, "Unable to map registers\n");
961 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
968 * cdns_uart_release_port - Release UART port
969 * @port: Handle to the uart port structure
971 * Release the memory region attached to a cdns_uart port. Called when the
972 * driver removes a cdns_uart port via uart_remove_one_port().
974 static void cdns_uart_release_port(struct uart_port *port)
976 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
977 iounmap(port->membase);
978 port->membase = NULL;
982 * cdns_uart_config_port - Configure UART port
983 * @port: Handle to the uart port structure
986 static void cdns_uart_config_port(struct uart_port *port, int flags)
988 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
989 port->type = PORT_XUARTPS;
993 * cdns_uart_get_mctrl - Get the modem control state
994 * @port: Handle to the uart port structure
996 * Return: the modem control state
998 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1000 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1003 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1008 val = readl(port->membase + CDNS_UART_MODEMCR);
1009 mode_reg = readl(port->membase + CDNS_UART_MR);
1011 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1012 CDNS_UART_MODEMCR_FCM);
1013 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1015 if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1016 val |= CDNS_UART_MODEMCR_FCM;
1017 if (mctrl & TIOCM_LOOP)
1018 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1020 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1022 writel(val, port->membase + CDNS_UART_MODEMCR);
1023 writel(mode_reg, port->membase + CDNS_UART_MR);
1026 #ifdef CONFIG_CONSOLE_POLL
1027 static int cdns_uart_poll_get_char(struct uart_port *port)
1030 unsigned long flags;
1032 spin_lock_irqsave(&port->lock, flags);
1034 /* Check if FIFO is empty */
1035 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1037 else /* Read a character */
1038 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1040 spin_unlock_irqrestore(&port->lock, flags);
1045 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1047 unsigned long flags;
1049 spin_lock_irqsave(&port->lock, flags);
1051 /* Wait until FIFO is empty */
1052 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1055 /* Write a character */
1056 writel(c, port->membase + CDNS_UART_FIFO);
1058 /* Wait until FIFO is empty */
1059 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1062 spin_unlock_irqrestore(&port->lock, flags);
1066 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1067 unsigned int oldstate)
1070 case UART_PM_STATE_OFF:
1071 pm_runtime_mark_last_busy(port->dev);
1072 pm_runtime_put_autosuspend(port->dev);
1075 pm_runtime_get_sync(port->dev);
1080 static const struct uart_ops cdns_uart_ops = {
1081 .set_mctrl = cdns_uart_set_mctrl,
1082 .get_mctrl = cdns_uart_get_mctrl,
1083 .start_tx = cdns_uart_start_tx,
1084 .stop_tx = cdns_uart_stop_tx,
1085 .stop_rx = cdns_uart_stop_rx,
1086 .tx_empty = cdns_uart_tx_empty,
1087 .break_ctl = cdns_uart_break_ctl,
1088 .set_termios = cdns_uart_set_termios,
1089 .startup = cdns_uart_startup,
1090 .shutdown = cdns_uart_shutdown,
1092 .type = cdns_uart_type,
1093 .verify_port = cdns_uart_verify_port,
1094 .request_port = cdns_uart_request_port,
1095 .release_port = cdns_uart_release_port,
1096 .config_port = cdns_uart_config_port,
1097 #ifdef CONFIG_CONSOLE_POLL
1098 .poll_get_char = cdns_uart_poll_get_char,
1099 .poll_put_char = cdns_uart_poll_put_char,
1103 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1106 * cdns_uart_get_port - Configure the port from platform device resource info
1109 * Return: a pointer to a uart_port or NULL for failure
1111 static struct uart_port *cdns_uart_get_port(int id)
1113 struct uart_port *port;
1115 /* Try the given port id if failed use default method */
1116 if (cdns_uart_port[id].mapbase != 0) {
1117 /* Find the next unused port */
1118 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1119 if (cdns_uart_port[id].mapbase == 0)
1123 if (id >= CDNS_UART_NR_PORTS)
1126 port = &cdns_uart_port[id];
1128 /* At this point, we've got an empty uart_port struct, initialize it */
1129 spin_lock_init(&port->lock);
1130 port->membase = NULL;
1132 port->type = PORT_UNKNOWN;
1133 port->iotype = UPIO_MEM32;
1134 port->flags = UPF_BOOT_AUTOCONF;
1135 port->ops = &cdns_uart_ops;
1136 port->fifosize = CDNS_UART_FIFO_SIZE;
1142 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1144 * cdns_uart_console_wait_tx - Wait for the TX to be full
1145 * @port: Handle to the uart port structure
1147 static void cdns_uart_console_wait_tx(struct uart_port *port)
1149 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1154 * cdns_uart_console_putchar - write the character to the FIFO buffer
1155 * @port: Handle to the uart port structure
1156 * @ch: Character to be written
1158 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1160 cdns_uart_console_wait_tx(port);
1161 writel(ch, port->membase + CDNS_UART_FIFO);
1164 static void cdns_early_write(struct console *con, const char *s,
1167 struct earlycon_device *dev = con->data;
1169 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1172 static int __init cdns_early_console_setup(struct earlycon_device *device,
1175 if (!device->port.membase)
1178 device->con->write = cdns_early_write;
1182 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1183 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1184 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1185 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1188 * cdns_uart_console_write - perform write operation
1189 * @co: Console handle
1190 * @s: Pointer to character array
1191 * @count: No of characters
1193 static void cdns_uart_console_write(struct console *co, const char *s,
1196 struct uart_port *port = &cdns_uart_port[co->index];
1197 unsigned long flags;
1198 unsigned int imr, ctrl;
1203 else if (oops_in_progress)
1204 locked = spin_trylock_irqsave(&port->lock, flags);
1206 spin_lock_irqsave(&port->lock, flags);
1208 /* save and disable interrupt */
1209 imr = readl(port->membase + CDNS_UART_IMR);
1210 writel(imr, port->membase + CDNS_UART_IDR);
1213 * Make sure that the tx part is enabled. Set the TX enable bit and
1214 * clear the TX disable bit to enable the transmitter.
1216 ctrl = readl(port->membase + CDNS_UART_CR);
1217 ctrl &= ~CDNS_UART_CR_TX_DIS;
1218 ctrl |= CDNS_UART_CR_TX_EN;
1219 writel(ctrl, port->membase + CDNS_UART_CR);
1221 uart_console_write(port, s, count, cdns_uart_console_putchar);
1222 cdns_uart_console_wait_tx(port);
1224 writel(ctrl, port->membase + CDNS_UART_CR);
1226 /* restore interrupt state */
1227 writel(imr, port->membase + CDNS_UART_IER);
1230 spin_unlock_irqrestore(&port->lock, flags);
1234 * cdns_uart_console_setup - Initialize the uart to default config
1235 * @co: Console handle
1236 * @options: Initial settings of uart
1238 * Return: 0 on success, negative errno otherwise.
1240 static int __init cdns_uart_console_setup(struct console *co, char *options)
1242 struct uart_port *port = &cdns_uart_port[co->index];
1248 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1251 if (!port->membase) {
1252 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1258 uart_parse_options(options, &baud, &parity, &bits, &flow);
1260 return uart_set_options(port, co, baud, parity, bits, flow);
1263 static struct uart_driver cdns_uart_uart_driver;
1265 static struct console cdns_uart_console = {
1266 .name = CDNS_UART_TTY_NAME,
1267 .write = cdns_uart_console_write,
1268 .device = uart_console_device,
1269 .setup = cdns_uart_console_setup,
1270 .flags = CON_PRINTBUFFER,
1271 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1272 .data = &cdns_uart_uart_driver,
1276 * cdns_uart_console_init - Initialization call
1278 * Return: 0 on success, negative errno otherwise
1280 static int __init cdns_uart_console_init(void)
1282 register_console(&cdns_uart_console);
1286 console_initcall(cdns_uart_console_init);
1288 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1290 static struct uart_driver cdns_uart_uart_driver = {
1291 .owner = THIS_MODULE,
1292 .driver_name = CDNS_UART_NAME,
1293 .dev_name = CDNS_UART_TTY_NAME,
1294 .major = CDNS_UART_MAJOR,
1295 .minor = CDNS_UART_MINOR,
1296 .nr = CDNS_UART_NR_PORTS,
1297 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1298 .cons = &cdns_uart_console,
1302 #ifdef CONFIG_PM_SLEEP
1304 * cdns_uart_suspend - suspend event
1305 * @device: Pointer to the device structure
1309 static int cdns_uart_suspend(struct device *device)
1311 struct uart_port *port = dev_get_drvdata(device);
1312 struct tty_struct *tty;
1313 struct device *tty_dev;
1316 /* Get the tty which could be NULL so don't assume it's valid */
1317 tty = tty_port_tty_get(&port->state->port);
1320 may_wake = device_may_wakeup(tty_dev);
1325 * Call the API provided in serial_core.c file which handles
1328 uart_suspend_port(&cdns_uart_uart_driver, port);
1329 if (!(console_suspend_enabled && !may_wake)) {
1330 unsigned long flags = 0;
1332 spin_lock_irqsave(&port->lock, flags);
1333 /* Empty the receive FIFO 1st before making changes */
1334 while (!(readl(port->membase + CDNS_UART_SR) &
1335 CDNS_UART_SR_RXEMPTY))
1336 readl(port->membase + CDNS_UART_FIFO);
1337 /* set RX trigger level to 1 */
1338 writel(1, port->membase + CDNS_UART_RXWM);
1339 /* disable RX timeout interrups */
1340 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1341 spin_unlock_irqrestore(&port->lock, flags);
1348 * cdns_uart_resume - Resume after a previous suspend
1349 * @device: Pointer to the device structure
1353 static int cdns_uart_resume(struct device *device)
1355 struct uart_port *port = dev_get_drvdata(device);
1356 unsigned long flags = 0;
1358 struct tty_struct *tty;
1359 struct device *tty_dev;
1362 /* Get the tty which could be NULL so don't assume it's valid */
1363 tty = tty_port_tty_get(&port->state->port);
1366 may_wake = device_may_wakeup(tty_dev);
1370 if (console_suspend_enabled && !may_wake) {
1371 struct cdns_uart *cdns_uart = port->private_data;
1373 clk_enable(cdns_uart->pclk);
1374 clk_enable(cdns_uart->uartclk);
1376 spin_lock_irqsave(&port->lock, flags);
1378 /* Set TX/RX Reset */
1379 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1380 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1381 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1382 while (readl(port->membase + CDNS_UART_CR) &
1383 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1386 /* restore rx timeout value */
1387 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1389 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1390 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1391 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1392 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1394 clk_disable(cdns_uart->uartclk);
1395 clk_disable(cdns_uart->pclk);
1396 spin_unlock_irqrestore(&port->lock, flags);
1398 spin_lock_irqsave(&port->lock, flags);
1399 /* restore original rx trigger level */
1400 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1401 /* enable RX timeout interrupt */
1402 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1403 spin_unlock_irqrestore(&port->lock, flags);
1406 return uart_resume_port(&cdns_uart_uart_driver, port);
1408 #endif /* ! CONFIG_PM_SLEEP */
1409 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1411 struct platform_device *pdev = to_platform_device(dev);
1412 struct uart_port *port = platform_get_drvdata(pdev);
1413 struct cdns_uart *cdns_uart = port->private_data;
1415 clk_disable(cdns_uart->uartclk);
1416 clk_disable(cdns_uart->pclk);
1420 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1422 struct platform_device *pdev = to_platform_device(dev);
1423 struct uart_port *port = platform_get_drvdata(pdev);
1424 struct cdns_uart *cdns_uart = port->private_data;
1426 clk_enable(cdns_uart->pclk);
1427 clk_enable(cdns_uart->uartclk);
1431 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1432 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1433 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1434 cdns_runtime_resume, NULL)
1437 static const struct cdns_platform_data zynqmp_uart_def = {
1438 .quirks = CDNS_UART_RXBS_SUPPORT, };
1440 /* Match table for of_platform binding */
1441 static const struct of_device_id cdns_uart_of_match[] = {
1442 { .compatible = "xlnx,xuartps", },
1443 { .compatible = "cdns,uart-r1p8", },
1444 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1445 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1448 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1451 * cdns_uart_probe - Platform driver probe
1452 * @pdev: Pointer to the platform device structure
1454 * Return: 0 on success, negative errno otherwise
1456 static int cdns_uart_probe(struct platform_device *pdev)
1459 struct uart_port *port;
1460 struct resource *res;
1461 struct cdns_uart *cdns_uart_data;
1462 const struct of_device_id *match;
1464 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1466 if (!cdns_uart_data)
1469 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1470 if (match && match->data) {
1471 const struct cdns_platform_data *data = match->data;
1473 cdns_uart_data->quirks = data->quirks;
1476 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1477 if (IS_ERR(cdns_uart_data->pclk)) {
1478 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1479 if (!IS_ERR(cdns_uart_data->pclk))
1480 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1482 if (IS_ERR(cdns_uart_data->pclk)) {
1483 dev_err(&pdev->dev, "pclk clock not found.\n");
1484 return PTR_ERR(cdns_uart_data->pclk);
1487 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1488 if (IS_ERR(cdns_uart_data->uartclk)) {
1489 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1490 if (!IS_ERR(cdns_uart_data->uartclk))
1491 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1493 if (IS_ERR(cdns_uart_data->uartclk)) {
1494 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1495 return PTR_ERR(cdns_uart_data->uartclk);
1498 rc = clk_prepare_enable(cdns_uart_data->pclk);
1500 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1503 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1505 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1506 goto err_out_clk_dis_pclk;
1509 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1512 goto err_out_clk_disable;
1515 irq = platform_get_irq(pdev, 0);
1518 goto err_out_clk_disable;
1521 #ifdef CONFIG_COMMON_CLK
1522 cdns_uart_data->clk_rate_change_nb.notifier_call =
1523 cdns_uart_clk_notifier_cb;
1524 if (clk_notifier_register(cdns_uart_data->uartclk,
1525 &cdns_uart_data->clk_rate_change_nb))
1526 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1528 /* Look for a serialN alias */
1529 id = of_alias_get_id(pdev->dev.of_node, "serial");
1533 /* Initialize the port structure */
1534 port = cdns_uart_get_port(id);
1537 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1539 goto err_out_notif_unreg;
1543 * Register the port.
1544 * This function also registers this device with the tty layer
1545 * and triggers invocation of the config_port() entry point.
1547 port->mapbase = res->start;
1549 port->dev = &pdev->dev;
1550 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1551 port->private_data = cdns_uart_data;
1552 cdns_uart_data->port = port;
1553 platform_set_drvdata(pdev, port);
1555 pm_runtime_use_autosuspend(&pdev->dev);
1556 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1557 pm_runtime_set_active(&pdev->dev);
1558 pm_runtime_enable(&pdev->dev);
1560 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1563 "uart_add_one_port() failed; err=%i\n", rc);
1564 goto err_out_pm_disable;
1570 pm_runtime_disable(&pdev->dev);
1571 pm_runtime_set_suspended(&pdev->dev);
1572 pm_runtime_dont_use_autosuspend(&pdev->dev);
1573 err_out_notif_unreg:
1574 #ifdef CONFIG_COMMON_CLK
1575 clk_notifier_unregister(cdns_uart_data->uartclk,
1576 &cdns_uart_data->clk_rate_change_nb);
1578 err_out_clk_disable:
1579 clk_disable_unprepare(cdns_uart_data->uartclk);
1580 err_out_clk_dis_pclk:
1581 clk_disable_unprepare(cdns_uart_data->pclk);
1587 * cdns_uart_remove - called when the platform driver is unregistered
1588 * @pdev: Pointer to the platform device structure
1590 * Return: 0 on success, negative errno otherwise
1592 static int cdns_uart_remove(struct platform_device *pdev)
1594 struct uart_port *port = platform_get_drvdata(pdev);
1595 struct cdns_uart *cdns_uart_data = port->private_data;
1598 /* Remove the cdns_uart port from the serial core */
1599 #ifdef CONFIG_COMMON_CLK
1600 clk_notifier_unregister(cdns_uart_data->uartclk,
1601 &cdns_uart_data->clk_rate_change_nb);
1603 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1605 clk_disable_unprepare(cdns_uart_data->uartclk);
1606 clk_disable_unprepare(cdns_uart_data->pclk);
1607 pm_runtime_disable(&pdev->dev);
1608 pm_runtime_set_suspended(&pdev->dev);
1609 pm_runtime_dont_use_autosuspend(&pdev->dev);
1613 static struct platform_driver cdns_uart_platform_driver = {
1614 .probe = cdns_uart_probe,
1615 .remove = cdns_uart_remove,
1617 .name = CDNS_UART_NAME,
1618 .of_match_table = cdns_uart_of_match,
1619 .pm = &cdns_uart_dev_pm_ops,
1623 static int __init cdns_uart_init(void)
1627 /* Register the cdns_uart driver with the serial core */
1628 retval = uart_register_driver(&cdns_uart_uart_driver);
1632 /* Register the platform driver */
1633 retval = platform_driver_register(&cdns_uart_platform_driver);
1635 uart_unregister_driver(&cdns_uart_uart_driver);
1640 static void __exit cdns_uart_exit(void)
1642 /* Unregister the platform driver */
1643 platform_driver_unregister(&cdns_uart_platform_driver);
1645 /* Unregister the cdns_uart driver */
1646 uart_unregister_driver(&cdns_uart_uart_driver);
1649 arch_initcall(cdns_uart_init);
1650 module_exit(cdns_uart_exit);
1652 MODULE_DESCRIPTION("Driver for Cadence UART");
1653 MODULE_AUTHOR("Xilinx Inc.");
1654 MODULE_LICENSE("GPL");