arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU104 RevA";
  20         compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c1;
  26                 mmc0 = &sdhci1;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44 };
  45
  46 &can1 {
  47         status = "okay";
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&pinctrl_can1_default>;
  50 };
  51
  52 &dcc {
  53         status = "okay";
  54 };
  55
  56 &gem3 {
  57         status = "okay";
  58         phy-handle = <&phy0>;
  59         phy-mode = "rgmii-id";
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&pinctrl_gem3_default>;
  62         phy0: phy@c {
  63                 reg = <0xc>;
  64                 ti,rx-internal-delay = <0x8>;
  65                 ti,tx-internal-delay = <0xa>;
  66                 ti,fifo-depth = <0x1>;
  67                 ti,rxctrl-strap-worka;
  68         };
  69 };
  70
  71 &gpio {
  72         status = "okay";
  73 };
  74
  75 &gpu {
  76         status = "okay";
  77 };
  78
  79 &i2c1 {
  80         status = "okay";
  81         clock-frequency = <400000>;
  82         pinctrl-names = "default", "gpio";
  83         pinctrl-0 = <&pinctrl_i2c1_default>;
  84         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  85         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
  86         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
  87
  88         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
  89         i2c-mux@74 { /* u34 */
  90                 compatible = "nxp,pca9548";
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93                 reg = <0x74>;
  94                 i2c@0 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         reg = <0>;
  98                         /*
  99                          * IIC_EEPROM 1kB memory which uses 256B blocks
 100                          * where every block has different address.
 101                          *    0 - 256B address 0x54
 102                          * 256B - 512B address 0x55
 103                          * 512B - 768B address 0x56
 104                          * 768B - 1024B address 0x57
 105                          */
 106                         eeprom: eeprom@54 { /* u23 */
 107                                 compatible = "atmel,24c08";
 108                                 reg = <0x54>;
 109                                 #address-cells = <1>;
 110                                 #size-cells = <1>;
 111                         };
 112                 };
 113
 114                 i2c@1 {
 115                         #address-cells = <1>;
 116                         #size-cells = <0>;
 117                         reg = <1>;
 118                         clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
 119                                 compatible = "idt,8t49n287";
 120                                 reg = <0x6c>;
 121                         };
 122                 };
 123
 124                 i2c@2 {
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                         reg = <2>;
 128                         irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
 129                                 #clock-cells = <0>;
 130                                 compatible = "infineon,irps5401";
 131                                 reg = <0x43>;
 132                         };
 133                         irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
 134                                 #clock-cells = <0>;
 135                                 compatible = "infineon,irps5401";
 136                                 reg = <0x4d>;
 137                         };
 138                 };
 139
 140                 i2c@4 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         reg = <4>;
 144                         tca6416_u97: gpio@21 {
 145                                 compatible = "ti,tca6416";
 146                                 reg = <0x21>;
 147                                 gpio-controller;
 148                                 #gpio-cells = <2>;
 149                                 /*
 150                                  * IRQ not connected
 151                                  * Lines:
 152                                  * 0 - IRPS5401_ALERT_B
 153                                  * 1 - HDMI_8T49N241_INT_ALM
 154                                  * 2 - MAX6643_OT_B
 155                                  * 3 - MAX6643_FANFAIL_B
 156                                  * 5 - IIC_MUX_RESET_B
 157                                  * 6 - GEM3_EXP_RESET_B
 158                                  * 7 - FMC_LPC_PRSNT_M2C_B
 159                                  * 4, 10 - 17 - not connected
 160                                  */
 161                         };
 162                 };
 163
 164                 i2c@5 {
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         reg = <5>;
 168                 };
 169
 170                 i2c@7 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         reg = <7>;
 174                 };
 175
 176                 /* 3, 6 not connected */
 177         };
 178 };
 179
 180 &pinctrl0 {
 181         status = "okay";
 182
 183         pinctrl_can1_default: can1-default {
 184                 mux {
 185                         function = "can1";
 186                         groups = "can1_6_grp";
 187                 };
 188
 189                 conf {
 190                         groups = "can1_6_grp";
 191                         slew-rate = <SLEW_RATE_SLOW>;
 192                         io-standard = <IO_STANDARD_LVCMOS18>;
 193                         drive-strength = <12>;
 194                 };
 195
 196                 conf-rx {
 197                         pins = "MIO25";
 198                         bias-high-impedance;
 199                 };
 200
 201                 conf-tx {
 202                         pins = "MIO24";
 203                         bias-disable;
 204                 };
 205         };
 206
 207         pinctrl_i2c1_default: i2c1-default {
 208                 mux {
 209                         groups = "i2c1_4_grp";
 210                         function = "i2c1";
 211                 };
 212
 213                 conf {
 214                         groups = "i2c1_4_grp";
 215                         bias-pull-up;
 216                         slew-rate = <SLEW_RATE_SLOW>;
 217                         io-standard = <IO_STANDARD_LVCMOS18>;
 218                         drive-strength = <12>;
 219                 };
 220         };
 221
 222         pinctrl_i2c1_gpio: i2c1-gpio {
 223                 mux {
 224                         groups = "gpio0_16_grp", "gpio0_17_grp";
 225                         function = "gpio0";
 226                 };
 227
 228                 conf {
 229                         groups = "gpio0_16_grp", "gpio0_17_grp";
 230                         slew-rate = <SLEW_RATE_SLOW>;
 231                         io-standard = <IO_STANDARD_LVCMOS18>;
 232                         drive-strength = <12>;
 233                 };
 234         };
 235
 236         pinctrl_gem3_default: gem3-default {
 237                 mux {
 238                         function = "ethernet3";
 239                         groups = "ethernet3_0_grp";
 240                 };
 241
 242                 conf {
 243                         groups = "ethernet3_0_grp";
 244                         slew-rate = <SLEW_RATE_SLOW>;
 245                         io-standard = <IO_STANDARD_LVCMOS18>;
 246                         drive-strength = <12>;
 247                 };
 248
 249                 conf-rx {
 250                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 251                                                                         "MIO75";
 252                         bias-high-impedance;
 253                         low-power-disable;
 254                 };
 255
 256                 conf-tx {
 257                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 258                                                                         "MIO69";
 259                         bias-disable;
 260                         low-power-enable;
 261                 };
 262
 263                 mux-mdio {
 264                         function = "mdio3";
 265                         groups = "mdio3_0_grp";
 266                 };
 267
 268                 conf-mdio {
 269                         groups = "mdio3_0_grp";
 270                         slew-rate = <SLEW_RATE_SLOW>;
 271                         io-standard = <IO_STANDARD_LVCMOS18>;
 272                         bias-disable;
 273                 };
 274         };
 275
 276         pinctrl_sdhci1_default: sdhci1-default {
 277                 mux {
 278                         groups = "sdio1_0_grp";
 279                         function = "sdio1";
 280                 };
 281
 282                 conf {
 283                         groups = "sdio1_0_grp";
 284                         slew-rate = <SLEW_RATE_SLOW>;
 285                         io-standard = <IO_STANDARD_LVCMOS18>;
 286                         bias-disable;
 287                         drive-strength = <12>;
 288                 };
 289
 290                 mux-cd {
 291                         groups = "sdio1_cd_0_grp";
 292                         function = "sdio1_cd";
 293                 };
 294
 295                 conf-cd {
 296                         groups = "sdio1_cd_0_grp";
 297                         bias-high-impedance;
 298                         bias-pull-up;
 299                         slew-rate = <SLEW_RATE_SLOW>;
 300                         io-standard = <IO_STANDARD_LVCMOS18>;
 301                 };
 302         };
 303
 304         pinctrl_uart0_default: uart0-default {
 305                 mux {
 306                         groups = "uart0_4_grp";
 307                         function = "uart0";
 308                 };
 309
 310                 conf {
 311                         groups = "uart0_4_grp";
 312                         slew-rate = <SLEW_RATE_SLOW>;
 313                         io-standard = <IO_STANDARD_LVCMOS18>;
 314                         drive-strength = <12>;
 315                 };
 316
 317                 conf-rx {
 318                         pins = "MIO18";
 319                         bias-high-impedance;
 320                 };
 321
 322                 conf-tx {
 323                         pins = "MIO19";
 324                         bias-disable;
 325                 };
 326         };
 327
 328         pinctrl_uart1_default: uart1-default {
 329                 mux {
 330                         groups = "uart1_5_grp";
 331                         function = "uart1";
 332                 };
 333
 334                 conf {
 335                         groups = "uart1_5_grp";
 336                         slew-rate = <SLEW_RATE_SLOW>;
 337                         io-standard = <IO_STANDARD_LVCMOS18>;
 338                         drive-strength = <12>;
 339                 };
 340
 341                 conf-rx {
 342                         pins = "MIO21";
 343                         bias-high-impedance;
 344                 };
 345
 346                 conf-tx {
 347                         pins = "MIO20";
 348                         bias-disable;
 349                 };
 350         };
 351
 352         pinctrl_usb0_default: usb0-default {
 353                 mux {
 354                         groups = "usb0_0_grp";
 355                         function = "usb0";
 356                 };
 357
 358                 conf {
 359                         groups = "usb0_0_grp";
 360                         slew-rate = <SLEW_RATE_SLOW>;
 361                         io-standard = <IO_STANDARD_LVCMOS18>;
 362                         drive-strength = <12>;
 363                 };
 364
 365                 conf-rx {
 366                         pins = "MIO52", "MIO53", "MIO55";
 367                         bias-high-impedance;
 368                 };
 369
 370                 conf-tx {
 371                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 372                                "MIO60", "MIO61", "MIO62", "MIO63";
 373                         bias-disable;
 374                 };
 375         };
 376 };
 377
 378 &qspi {
 379         status = "okay";
 380         flash@0 {
 381                 compatible = "m25p80"; /* n25q512a 128MiB */
 382                 #address-cells = <1>;
 383                 #size-cells = <1>;
 384                 reg = <0x0>;
 385                 spi-tx-bus-width = <1>;
 386                 spi-rx-bus-width = <4>;
 387                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 388                 partition@qspi-fsbl-uboot { /* for testing purpose */
 389                         label = "qspi-fsbl-uboot";
 390                         reg = <0x0 0x100000>;
 391                 };
 392                 partition@qspi-linux { /* for testing purpose */
 393                         label = "qspi-linux";
 394                         reg = <0x100000 0x500000>;
 395                 };
 396                 partition@qspi-device-tree { /* for testing purpose */
 397                         label = "qspi-device-tree";
 398                         reg = <0x600000 0x20000>;
 399                 };
 400                 partition@qspi-rootfs { /* for testing purpose */
 401                         label = "qspi-rootfs";
 402                         reg = <0x620000 0x5E0000>;
 403                 };
 404         };
 405 };
 406
 407 &rtc {
 408         status = "okay";
 409 };
 410
 411 &sata {
 412         status = "okay";
 413         /* SATA OOB timing settings */
 414         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 415         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 416         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 417         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 418         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 419         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 420         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 421         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 422         phy-names = "sata-phy";
 423         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 424 };
 425
 426 /* SD1 with level shifter */
 427 &sdhci1 {
 428         status = "okay";
 429         no-1-8-v;
 430         pinctrl-names = "default";
 431         pinctrl-0 = <&pinctrl_sdhci1_default>;
 432         xlnx,mio_bank = <1>;
 433         disable-wp;
 434 };
 435
 436 &serdes {
 437         status = "okay";
 438 };
 439
 440 &uart0 {
 441         status = "okay";
 442         pinctrl-names = "default";
 443         pinctrl-0 = <&pinctrl_uart0_default>;
 444 };
 445
 446 &uart1 {
 447         status = "okay";
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&pinctrl_uart1_default>;
 450 };
 451
 452 /* ULPI SMSC USB3320 */
 453 &usb0 {
 454         status = "okay";
 455         pinctrl-names = "default";
 456         pinctrl-0 = <&pinctrl_usb0_default>;
 457 };
 458
 459 &dwc3_0 {
 460         status = "okay";
 461         dr_mode = "host";
 462         snps,usb3_lpm_capable;
 463         phy-names = "usb3-phy";
 464         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 465         maximum-speed = "super-speed";
 466 };
 467
 468 &watchdog0 {
 469         status = "okay";
 470 };
 471
 472 &xilinx_ams {
 473         status = "okay";
 474 };
 475
 476 &ams_ps {
 477         status = "okay";
 478 };
 479
 480 &ams_pl {
 481         status = "okay";
 482 };
 483
 484 &zynqmp_dpsub {
 485         status = "okay";
 486         phy-names = "dp-phy0", "dp-phy1";
 487         phys = <&lane1 PHY_TYPE_DP 0 3 27000000>, <&lane0 PHY_TYPE_DP 1 3 27000000>;
 488 };
 489
 490 &zynqmp_dp_snd_pcm0 {
 491         status = "okay";
 492 };
 493
 494 &zynqmp_dp_snd_pcm1 {
 495         status = "okay";
 496 };
 497
 498 &zynqmp_dp_snd_card0 {
 499         status = "okay";
 500 };
 501
 502 &zynqmp_dp_snd_codec0 {
 503         status = "okay";
 504 };
 505
 506 &xlnx_dpdma {
 507         status = "okay";
 508 };