drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

   1 /*
   2  * Copyright (c) 2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include "hisi_sas.h"
  12 #define DRV_NAME "hisi_sas_v3_hw"
  13
  14 /* global registers need init */
  15 #define DLVRY_QUEUE_ENABLE              0x0
  16 #define IOST_BASE_ADDR_LO               0x8
  17 #define IOST_BASE_ADDR_HI               0xc
  18 #define ITCT_BASE_ADDR_LO               0x10
  19 #define ITCT_BASE_ADDR_HI               0x14
  20 #define IO_BROKEN_MSG_ADDR_LO           0x18
  21 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  22 #define PHY_CONTEXT                     0x20
  23 #define PHY_STATE                       0x24
  24 #define PHY_PORT_NUM_MA                 0x28
  25 #define PHY_CONN_RATE                   0x30
  26 #define ITCT_CLR                        0x44
  27 #define ITCT_CLR_EN_OFF                 16
  28 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  29 #define ITCT_DEV_OFF                    0
  30 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  31 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  32 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  33 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  34 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  35 #define CFG_MAX_TAG                     0x68
  36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  37 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  38 #define HGC_GET_ITV_TIME                0x90
  39 #define DEVICE_MSG_WORK_MODE            0x94
  40 #define OPENA_WT_CONTI_TIME             0x9c
  41 #define I_T_NEXUS_LOSS_TIME             0xa0
  42 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  43 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  44 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  45 #define CQ_INT_CONVERGE_EN              0xb0
  46 #define CFG_AGING_TIME                  0xbc
  47 #define HGC_DFX_CFG2                    0xc0
  48 #define CFG_ABT_SET_QUERY_IPTT  0xd4
  49 #define CFG_SET_ABORTED_IPTT_OFF        0
  50 #define CFG_SET_ABORTED_IPTT_MSK        (0xfff << CFG_SET_ABORTED_IPTT_OFF)
  51 #define CFG_SET_ABORTED_EN_OFF  12
  52 #define CFG_ABT_SET_IPTT_DONE   0xd8
  53 #define CFG_ABT_SET_IPTT_DONE_OFF       0
  54 #define HGC_IOMB_PROC1_STATUS   0x104
  55 #define CHNL_INT_STATUS                 0x148
  56 #define HGC_AXI_FIFO_ERR_INFO  0x154
  57 #define AXI_ERR_INFO_OFF               0
  58 #define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
  59 #define FIFO_ERR_INFO_OFF              8
  60 #define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
  61 #define INT_COAL_EN                     0x19c
  62 #define OQ_INT_COAL_TIME                0x1a0
  63 #define OQ_INT_COAL_CNT                 0x1a4
  64 #define ENT_INT_COAL_TIME               0x1a8
  65 #define ENT_INT_COAL_CNT                0x1ac
  66 #define OQ_INT_SRC                      0x1b0
  67 #define OQ_INT_SRC_MSK                  0x1b4
  68 #define ENT_INT_SRC1                    0x1b8
  69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  73 #define ENT_INT_SRC2                    0x1bc
  74 #define ENT_INT_SRC3                    0x1c0
  75 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
  76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
  77 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
  78 #define ENT_INT_SRC3_AXI_OFF                    11
  79 #define ENT_INT_SRC3_FIFO_OFF                   12
  80 #define ENT_INT_SRC3_LM_OFF                             14
  81 #define ENT_INT_SRC3_ITC_INT_OFF        15
  82 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  83 #define ENT_INT_SRC3_ABT_OFF            16
  84 #define ENT_INT_SRC_MSK1                0x1c4
  85 #define ENT_INT_SRC_MSK2                0x1c8
  86 #define ENT_INT_SRC_MSK3                0x1cc
  87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  88 #define CHNL_PHYUPDOWN_INT_MSK          0x1d0
  89 #define CHNL_ENT_INT_MSK                        0x1d4
  90 #define HGC_COM_INT_MSK                         0x1d8
  91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  92 #define SAS_ECC_INTR                    0x1e8
  93 #define SAS_ECC_INTR_MSK                0x1ec
  94 #define HGC_ERR_STAT_EN                 0x238
  95 #define CQE_SEND_CNT                    0x248
  96 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  97 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  98 #define DLVRY_Q_0_DEPTH                 0x268
  99 #define DLVRY_Q_0_WR_PTR                0x26c
 100 #define DLVRY_Q_0_RD_PTR                0x270
 101 #define HYPER_STREAM_ID_EN_CFG          0xc80
 102 #define OQ0_INT_SRC_MSK                 0xc90
 103 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 104 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 105 #define COMPL_Q_0_DEPTH                 0x4e8
 106 #define COMPL_Q_0_WR_PTR                0x4ec
 107 #define COMPL_Q_0_RD_PTR                0x4f0
 108 #define AWQOS_AWCACHE_CFG       0xc84
 109 #define ARQOS_ARCACHE_CFG       0xc88
 110 #define HILINK_ERR_DFX          0xe04
 111 #define SAS_GPIO_CFG_0          0x1000
 112 #define SAS_GPIO_CFG_1          0x1004
 113 #define SAS_GPIO_TX_0_1 0x1040
 114 #define SAS_CFG_DRIVE_VLD       0x1070
 115
 116 /* phy registers requiring init */
 117 #define PORT_BASE                       (0x2000)
 118 #define PHY_CFG                         (PORT_BASE + 0x0)
 119 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 120 #define PHY_CFG_ENA_OFF                 0
 121 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 122 #define PHY_CFG_DC_OPT_OFF              2
 123 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 124 #define PHY_CFG_PHY_RST_OFF             3
 125 #define PHY_CFG_PHY_RST_MSK             (0x1 << PHY_CFG_PHY_RST_OFF)
 126 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 127 #define PHY_CTRL                        (PORT_BASE + 0x14)
 128 #define PHY_CTRL_RESET_OFF              0
 129 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 130 #define CMD_HDR_PIR_OFF                 8
 131 #define CMD_HDR_PIR_MSK                 (0x1 << CMD_HDR_PIR_OFF)
 132 #define SERDES_CFG                      (PORT_BASE + 0x1c)
 133 #define SL_CFG                          (PORT_BASE + 0x84)
 134 #define AIP_LIMIT                       (PORT_BASE + 0x90)
 135 #define SL_CONTROL                      (PORT_BASE + 0x94)
 136 #define SL_CONTROL_NOTIFY_EN_OFF        0
 137 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 138 #define SL_CTA_OFF              17
 139 #define SL_CTA_MSK              (0x1 << SL_CTA_OFF)
 140 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 141 #define RX_BCAST_CHG_OFF                1
 142 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 143 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 144 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 145 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 146 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 147 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 148 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 149 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 150 #define TXID_AUTO                               (PORT_BASE + 0xb8)
 151 #define CT3_OFF         1
 152 #define CT3_MSK         (0x1 << CT3_OFF)
 153 #define TX_HARDRST_OFF          2
 154 #define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
 155 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 156 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 157 #define STP_LINK_TIMER                  (PORT_BASE + 0x120)
 158 #define STP_LINK_TIMEOUT_STATE          (PORT_BASE + 0x124)
 159 #define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
 160 #define SAS_SSP_CON_TIMER_CFG           (PORT_BASE + 0x134)
 161 #define SAS_SMP_CON_TIMER_CFG           (PORT_BASE + 0x138)
 162 #define SAS_STP_CON_TIMER_CFG           (PORT_BASE + 0x13c)
 163 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 164 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 165 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 166 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 167 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 168 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 169 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 170 #define CHL_INT0_NOT_RDY_OFF            4
 171 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 172 #define CHL_INT0_PHY_RDY_OFF            5
 173 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 174 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 175 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 176 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 177 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 178 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 179 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
 180 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
 181 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
 182 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
 183 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 184 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
 185 #define CHL_INT2_RX_DISP_ERR_OFF        28
 186 #define CHL_INT2_RX_CODE_ERR_OFF        29
 187 #define CHL_INT2_RX_INVLD_DW_OFF        30
 188 #define CHL_INT2_STP_LINK_TIMEOUT_OFF   31
 189 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 190 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 191 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 192 #define SAS_EC_INT_COAL_TIME            (PORT_BASE + 0x1cc)
 193 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 194 #define SAS_RX_TRAIN_TIMER              (PORT_BASE + 0x2a4)
 195 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 196 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 197 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 198 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 199 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 200 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 201 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 202 #define DMA_TX_STATUS_BUSY_OFF          0
 203 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 204 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 205 #define DMA_RX_STATUS_BUSY_OFF          0
 206 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 207
 208 #define COARSETUNE_TIME                 (PORT_BASE + 0x304)
 209 #define ERR_CNT_DWS_LOST                (PORT_BASE + 0x380)
 210 #define ERR_CNT_RESET_PROB              (PORT_BASE + 0x384)
 211 #define ERR_CNT_INVLD_DW                (PORT_BASE + 0x390)
 212 #define ERR_CNT_CODE_ERR                (PORT_BASE + 0x394)
 213 #define ERR_CNT_DISP_ERR                (PORT_BASE + 0x398)
 214
 215 #define DEFAULT_ITCT_HW         2048 /* reset value, not reprogrammed */
 216 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
 217 #error Max ITCT exceeded
 218 #endif
 219
 220 #define AXI_MASTER_CFG_BASE             (0x5000)
 221 #define AM_CTRL_GLOBAL                  (0x0)
 222 #define AM_CTRL_SHUTDOWN_REQ_OFF        0
 223 #define AM_CTRL_SHUTDOWN_REQ_MSK        (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
 224 #define AM_CURR_TRANS_RETURN    (0x150)
 225
 226 #define AM_CFG_MAX_TRANS                (0x5010)
 227 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 228 #define AXI_CFG                                 (0x5100)
 229 #define AM_ROB_ECC_ERR_ADDR             (0x510c)
 230 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF  0
 231 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
 232 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF  8
 233 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
 234
 235 /* RAS registers need init */
 236 #define RAS_BASE                (0x6000)
 237 #define SAS_RAS_INTR0                   (RAS_BASE)
 238 #define SAS_RAS_INTR1                   (RAS_BASE + 0x04)
 239 #define SAS_RAS_INTR0_MASK              (RAS_BASE + 0x08)
 240 #define SAS_RAS_INTR1_MASK              (RAS_BASE + 0x0c)
 241 #define CFG_SAS_RAS_INTR_MASK           (RAS_BASE + 0x1c)
 242 #define SAS_RAS_INTR2                   (RAS_BASE + 0x20)
 243 #define SAS_RAS_INTR2_MASK              (RAS_BASE + 0x24)
 244
 245 /* HW dma structures */
 246 /* Delivery queue header */
 247 /* dw0 */
 248 #define CMD_HDR_ABORT_FLAG_OFF          0
 249 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 250 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 251 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 252 #define CMD_HDR_RESP_REPORT_OFF         5
 253 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 254 #define CMD_HDR_TLR_CTRL_OFF            6
 255 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 256 #define CMD_HDR_PORT_OFF                18
 257 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 258 #define CMD_HDR_PRIORITY_OFF            27
 259 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 260 #define CMD_HDR_CMD_OFF                 29
 261 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 262 /* dw1 */
 263 #define CMD_HDR_UNCON_CMD_OFF   3
 264 #define CMD_HDR_DIR_OFF                 5
 265 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 266 #define CMD_HDR_RESET_OFF               7
 267 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 268 #define CMD_HDR_VDTL_OFF                10
 269 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 270 #define CMD_HDR_FRAME_TYPE_OFF          11
 271 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 272 #define CMD_HDR_DEV_ID_OFF              16
 273 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 274 /* dw2 */
 275 #define CMD_HDR_CFL_OFF                 0
 276 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 277 #define CMD_HDR_NCQ_TAG_OFF             10
 278 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 279 #define CMD_HDR_MRFL_OFF                15
 280 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 281 #define CMD_HDR_SG_MOD_OFF              24
 282 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 283 /* dw3 */
 284 #define CMD_HDR_IPTT_OFF                0
 285 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 286 /* dw6 */
 287 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 288 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 289 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 290 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 291 /* dw7 */
 292 #define CMD_HDR_ADDR_MODE_SEL_OFF               15
 293 #define CMD_HDR_ADDR_MODE_SEL_MSK               (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
 294 #define CMD_HDR_ABORT_IPTT_OFF          16
 295 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 296
 297 /* Completion header */
 298 /* dw0 */
 299 #define CMPLT_HDR_CMPLT_OFF             0
 300 #define CMPLT_HDR_CMPLT_MSK             (0x3 << CMPLT_HDR_CMPLT_OFF)
 301 #define CMPLT_HDR_ERROR_PHASE_OFF   2
 302 #define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
 303 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 304 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 305 #define CMPLT_HDR_ERX_OFF               12
 306 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 307 #define CMPLT_HDR_ABORT_STAT_OFF        13
 308 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 309 /* abort_stat */
 310 #define STAT_IO_NOT_VALID               0x1
 311 #define STAT_IO_NO_DEVICE               0x2
 312 #define STAT_IO_COMPLETE                0x3
 313 #define STAT_IO_ABORTED                 0x4
 314 /* dw1 */
 315 #define CMPLT_HDR_IPTT_OFF              0
 316 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 317 #define CMPLT_HDR_DEV_ID_OFF            16
 318 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 319 /* dw3 */
 320 #define CMPLT_HDR_IO_IN_TARGET_OFF      17
 321 #define CMPLT_HDR_IO_IN_TARGET_MSK      (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
 322
 323 /* ITCT header */
 324 /* qw0 */
 325 #define ITCT_HDR_DEV_TYPE_OFF           0
 326 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 327 #define ITCT_HDR_VALID_OFF              2
 328 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 329 #define ITCT_HDR_MCR_OFF                5
 330 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 331 #define ITCT_HDR_VLN_OFF                9
 332 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 333 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 334 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 335 #define ITCT_HDR_PORT_ID_OFF            28
 336 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 337 /* qw2 */
 338 #define ITCT_HDR_INLT_OFF               0
 339 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 340 #define ITCT_HDR_RTOLT_OFF              48
 341 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 342
 343 struct hisi_sas_protect_iu_v3_hw {
 344         u32 dw0;
 345         u32 lbrtcv;
 346         u32 lbrtgv;
 347         u32 dw3;
 348         u32 dw4;
 349         u32 dw5;
 350         u32 rsv;
 351 };
 352
 353 struct hisi_sas_complete_v3_hdr {
 354         __le32 dw0;
 355         __le32 dw1;
 356         __le32 act;
 357         __le32 dw3;
 358 };
 359
 360 struct hisi_sas_err_record_v3 {
 361         /* dw0 */
 362         __le32 trans_tx_fail_type;
 363
 364         /* dw1 */
 365         __le32 trans_rx_fail_type;
 366
 367         /* dw2 */
 368         __le16 dma_tx_err_type;
 369         __le16 sipc_rx_err_type;
 370
 371         /* dw3 */
 372         __le32 dma_rx_err_type;
 373 };
 374
 375 #define RX_DATA_LEN_UNDERFLOW_OFF       6
 376 #define RX_DATA_LEN_UNDERFLOW_MSK       (1 << RX_DATA_LEN_UNDERFLOW_OFF)
 377
 378 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
 379 #define HISI_SAS_MSI_COUNT_V3_HW 32
 380
 381 #define DIR_NO_DATA 0
 382 #define DIR_TO_INI 1
 383 #define DIR_TO_DEVICE 2
 384 #define DIR_RESERVED 3
 385
 386 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
 387         ((fis.command == ATA_CMD_READ_LOG_EXT) || \
 388         (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
 389         ((fis.command == ATA_CMD_DEV_RESET) && \
 390         ((fis.control & ATA_SRST) != 0)))
 391
 392 #define T10_INSRT_EN_OFF    0
 393 #define T10_INSRT_EN_MSK    (1 << T10_INSRT_EN_OFF)
 394 #define T10_RMV_EN_OFF      1
 395 #define T10_RMV_EN_MSK      (1 << T10_RMV_EN_OFF)
 396 #define T10_RPLC_EN_OFF     2
 397 #define T10_RPLC_EN_MSK     (1 << T10_RPLC_EN_OFF)
 398 #define T10_CHK_EN_OFF      3
 399 #define T10_CHK_EN_MSK      (1 << T10_CHK_EN_OFF)
 400 #define INCR_LBRT_OFF       5
 401 #define INCR_LBRT_MSK       (1 << INCR_LBRT_OFF)
 402 #define USR_DATA_BLOCK_SZ_OFF   20
 403 #define USR_DATA_BLOCK_SZ_MSK   (0x3 << USR_DATA_BLOCK_SZ_OFF)
 404 #define T10_CHK_MSK_OFF     16
 405 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
 406 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
 407
 408 #define BASE_VECTORS_V3_HW  16
 409 #define MIN_AFFINE_VECTORS_V3_HW  (BASE_VECTORS_V3_HW + 1)
 410
 411 static bool hisi_sas_intr_conv;
 412 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
 413
 414 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
 415 static int prot_mask;
 416 module_param(prot_mask, int, 0);
 417 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
 418
 419 static bool auto_affine_msi_experimental;
 420 module_param(auto_affine_msi_experimental, bool, 0444);
 421 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n"
 422                  "default is off");
 423
 424 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 425 {
 426         void __iomem *regs = hisi_hba->regs + off;
 427
 428         return readl(regs);
 429 }
 430
 431 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 432 {
 433         void __iomem *regs = hisi_hba->regs + off;
 434
 435         return readl_relaxed(regs);
 436 }
 437
 438 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 439 {
 440         void __iomem *regs = hisi_hba->regs + off;
 441
 442         writel(val, regs);
 443 }
 444
 445 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 446                                  u32 off, u32 val)
 447 {
 448         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 449
 450         writel(val, regs);
 451 }
 452
 453 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 454                                       int phy_no, u32 off)
 455 {
 456         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 457
 458         return readl(regs);
 459 }
 460
 461 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,          \
 462                                      timeout_us)                        \
 463 ({                                                                      \
 464         void __iomem *regs = hisi_hba->regs + off;                      \
 465         readl_poll_timeout(regs, val, cond, delay_us, timeout_us);      \
 466 })
 467
 468 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,   \
 469                                             timeout_us)                 \
 470 ({                                                                      \
 471         void __iomem *regs = hisi_hba->regs + off;                      \
 472         readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
 473 })
 474
 475 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 476 {
 477         struct pci_dev *pdev = hisi_hba->pci_dev;
 478         int i;
 479
 480         /* Global registers init */
 481         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 482                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 483         hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
 484         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 485         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 486         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 487         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 488         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 489         hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
 490                          hisi_sas_intr_conv);
 491         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
 492         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 493         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 494         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 495         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
 496         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
 497         if (pdev->revision >= 0x21)
 498                 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff);
 499         else
 500                 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
 501         hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
 502         hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
 503         hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
 504         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
 505         hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
 506         hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
 507         for (i = 0; i < hisi_hba->queue_count; i++)
 508                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 509
 510         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 511
 512         for (i = 0; i < hisi_hba->n_phy; i++) {
 513                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 514                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
 515                 u32 prog_phy_link_rate = 0x800;
 516
 517                 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
 518                                 SAS_LINK_RATE_1_5_GBPS)) {
 519                         prog_phy_link_rate = 0x855;
 520                 } else {
 521                         enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
 522
 523                         prog_phy_link_rate =
 524                                 hisi_sas_get_prog_phy_linkrate_mask(max) |
 525                                 0x800;
 526                 }
 527                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
 528                         prog_phy_link_rate);
 529                 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
 530                 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
 531                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 532                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 533                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 534                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 535                 if (pdev->revision >= 0x21)
 536                         hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
 537                                         0xffffffff);
 538                 else
 539                         hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
 540                                         0xff87ffff);
 541                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
 542                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 543                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 544                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 545                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 546                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 547                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
 548                 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
 549                 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
 550                 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
 551                 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
 552                                      0x30f4240);
 553                 /* used for 12G negotiate */
 554                 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
 555                 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
 556         }
 557
 558         for (i = 0; i < hisi_hba->queue_count; i++) {
 559                 /* Delivery queue */
 560                 hisi_sas_write32(hisi_hba,
 561                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 562                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 563
 564                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 565                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 566
 567                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 568                                  HISI_SAS_QUEUE_SLOTS);
 569
 570                 /* Completion queue */
 571                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 572                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 573
 574                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 575                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 576
 577                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 578                                  HISI_SAS_QUEUE_SLOTS);
 579         }
 580
 581         /* itct */
 582         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 583                          lower_32_bits(hisi_hba->itct_dma));
 584
 585         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 586                          upper_32_bits(hisi_hba->itct_dma));
 587
 588         /* iost */
 589         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 590                          lower_32_bits(hisi_hba->iost_dma));
 591
 592         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 593                          upper_32_bits(hisi_hba->iost_dma));
 594
 595         /* breakpoint */
 596         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 597                          lower_32_bits(hisi_hba->breakpoint_dma));
 598
 599         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 600                          upper_32_bits(hisi_hba->breakpoint_dma));
 601
 602         /* SATA broken msg */
 603         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 604                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 605
 606         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 607                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 608
 609         /* SATA initial fis */
 610         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 611                          lower_32_bits(hisi_hba->initial_fis_dma));
 612
 613         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 614                          upper_32_bits(hisi_hba->initial_fis_dma));
 615
 616         /* RAS registers init */
 617         hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
 618         hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
 619         hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
 620         hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
 621
 622         /* LED registers init */
 623         hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
 624         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
 625         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
 626         /* Configure blink generator rate A to 1Hz and B to 4Hz */
 627         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
 628         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
 629 }
 630
 631 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 632 {
 633         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 634
 635         cfg &= ~PHY_CFG_DC_OPT_MSK;
 636         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 637         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 638 }
 639
 640 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 641 {
 642         struct sas_identify_frame identify_frame;
 643         u32 *identify_buffer;
 644
 645         memset(&identify_frame, 0, sizeof(identify_frame));
 646         identify_frame.dev_type = SAS_END_DEVICE;
 647         identify_frame.frame_type = 0;
 648         identify_frame._un1 = 1;
 649         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 650         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 651         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 652         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 653         identify_frame.phy_id = phy_no;
 654         identify_buffer = (u32 *)(&identify_frame);
 655
 656         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 657                         __swab32(identify_buffer[0]));
 658         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 659                         __swab32(identify_buffer[1]));
 660         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 661                         __swab32(identify_buffer[2]));
 662         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 663                         __swab32(identify_buffer[3]));
 664         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 665                         __swab32(identify_buffer[4]));
 666         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 667                         __swab32(identify_buffer[5]));
 668 }
 669
 670 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
 671                              struct hisi_sas_device *sas_dev)
 672 {
 673         struct domain_device *device = sas_dev->sas_device;
 674         struct device *dev = hisi_hba->dev;
 675         u64 qw0, device_id = sas_dev->device_id;
 676         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 677         struct domain_device *parent_dev = device->parent;
 678         struct asd_sas_port *sas_port = device->port;
 679         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 680         u64 sas_addr;
 681
 682         memset(itct, 0, sizeof(*itct));
 683
 684         /* qw0 */
 685         qw0 = 0;
 686         switch (sas_dev->dev_type) {
 687         case SAS_END_DEVICE:
 688         case SAS_EDGE_EXPANDER_DEVICE:
 689         case SAS_FANOUT_EXPANDER_DEVICE:
 690                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 691                 break;
 692         case SAS_SATA_DEV:
 693         case SAS_SATA_PENDING:
 694                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 695                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 696                 else
 697                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 698                 break;
 699         default:
 700                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 701                          sas_dev->dev_type);
 702         }
 703
 704         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 705                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 706                 (1 << ITCT_HDR_VLN_OFF) |
 707                 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
 708                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 709                 (port->id << ITCT_HDR_PORT_ID_OFF));
 710         itct->qw0 = cpu_to_le64(qw0);
 711
 712         /* qw1 */
 713         memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 714         itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 715
 716         /* qw2 */
 717         if (!dev_is_sata(device))
 718                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 719                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 720 }
 721
 722 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
 723                               struct hisi_sas_device *sas_dev)
 724 {
 725         DECLARE_COMPLETION_ONSTACK(completion);
 726         u64 dev_id = sas_dev->device_id;
 727         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 728         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 729
 730         sas_dev->completion = &completion;
 731
 732         /* clear the itct interrupt state */
 733         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 734                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 735                                  ENT_INT_SRC3_ITC_INT_MSK);
 736
 737         /* clear the itct table */
 738         reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 739         hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 740
 741         wait_for_completion(sas_dev->completion);
 742         memset(itct, 0, sizeof(struct hisi_sas_itct));
 743 }
 744
 745 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
 746                                 struct domain_device *device)
 747 {
 748         struct hisi_sas_slot *slot, *slot2;
 749         struct hisi_sas_device *sas_dev = device->lldd_dev;
 750         u32 cfg_abt_set_query_iptt;
 751
 752         cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
 753                 CFG_ABT_SET_QUERY_IPTT);
 754         list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
 755                 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
 756                 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
 757                         (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
 758                 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 759                         cfg_abt_set_query_iptt);
 760         }
 761         cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
 762         hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 763                 cfg_abt_set_query_iptt);
 764         hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
 765                                         1 << CFG_ABT_SET_IPTT_DONE_OFF);
 766 }
 767
 768 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
 769 {
 770         struct device *dev = hisi_hba->dev;
 771         int ret;
 772         u32 val;
 773
 774         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 775
 776         /* Disable all of the PHYs */
 777         hisi_sas_stop_phys(hisi_hba);
 778         udelay(50);
 779
 780         /* Ensure axi bus idle */
 781         ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
 782                                            20000, 1000000);
 783         if (ret) {
 784                 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
 785                 return -EIO;
 786         }
 787
 788         if (ACPI_HANDLE(dev)) {
 789                 acpi_status s;
 790
 791                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 792                 if (ACPI_FAILURE(s)) {
 793                         dev_err(dev, "Reset failed\n");
 794                         return -EIO;
 795                 }
 796         } else {
 797                 dev_err(dev, "no reset method!\n");
 798                 return -EINVAL;
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
 805 {
 806         struct device *dev = hisi_hba->dev;
 807         int rc;
 808
 809         rc = reset_hw_v3_hw(hisi_hba);
 810         if (rc) {
 811                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 812                 return rc;
 813         }
 814
 815         msleep(100);
 816         init_reg_v3_hw(hisi_hba);
 817
 818         return 0;
 819 }
 820
 821 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 822 {
 823         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 824
 825         cfg |= PHY_CFG_ENA_MSK;
 826         cfg &= ~PHY_CFG_PHY_RST_MSK;
 827         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 828 }
 829
 830 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 831 {
 832         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 833         u32 state;
 834
 835         cfg &= ~PHY_CFG_ENA_MSK;
 836         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 837
 838         mdelay(50);
 839
 840         state = hisi_sas_read32(hisi_hba, PHY_STATE);
 841         if (state & BIT(phy_no)) {
 842                 cfg |= PHY_CFG_PHY_RST_MSK;
 843                 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 844         }
 845 }
 846
 847 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 848 {
 849         config_id_frame_v3_hw(hisi_hba, phy_no);
 850         config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
 851         enable_phy_v3_hw(hisi_hba, phy_no);
 852 }
 853
 854 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 855 {
 856         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
 857         u32 txid_auto;
 858
 859         disable_phy_v3_hw(hisi_hba, phy_no);
 860         if (phy->identify.device_type == SAS_END_DEVICE) {
 861                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
 862                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
 863                                         txid_auto | TX_HARDRST_MSK);
 864         }
 865         msleep(100);
 866         start_phy_v3_hw(hisi_hba, phy_no);
 867 }
 868
 869 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
 870 {
 871         return SAS_LINK_RATE_12_0_GBPS;
 872 }
 873
 874 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
 875 {
 876         int i;
 877
 878         for (i = 0; i < hisi_hba->n_phy; i++) {
 879                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 880                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
 881
 882                 if (!sas_phy->phy->enabled)
 883                         continue;
 884
 885                 start_phy_v3_hw(hisi_hba, i);
 886         }
 887 }
 888
 889 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 890 {
 891         u32 sl_control;
 892
 893         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 894         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 895         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 896         msleep(1);
 897         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 898         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 899         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 900 }
 901
 902 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
 903 {
 904         int i, bitmap = 0;
 905         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 906         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
 907
 908         for (i = 0; i < hisi_hba->n_phy; i++)
 909                 if (phy_state & BIT(i))
 910                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 911                                 bitmap |= BIT(i);
 912
 913         return bitmap;
 914 }
 915
 916 /**
 917  * The callpath to this function and upto writing the write
 918  * queue pointer should be safe from interruption.
 919  */
 920 static int
 921 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
 922 {
 923         struct device *dev = hisi_hba->dev;
 924         int queue = dq->id;
 925         u32 r, w;
 926
 927         w = dq->wr_point;
 928         r = hisi_sas_read32_relaxed(hisi_hba,
 929                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
 930         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
 931                 dev_warn(dev, "full queue=%d r=%d w=%d\n",
 932                                 queue, r, w);
 933                 return -EAGAIN;
 934         }
 935
 936         dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
 937
 938         return w;
 939 }
 940
 941 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
 942 {
 943         struct hisi_hba *hisi_hba = dq->hisi_hba;
 944         struct hisi_sas_slot *s, *s1, *s2 = NULL;
 945         int dlvry_queue = dq->id;
 946         int wp;
 947
 948         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
 949                 if (!s->ready)
 950                         break;
 951                 s2 = s;
 952                 list_del(&s->delivery);
 953         }
 954
 955         if (!s2)
 956                 return;
 957
 958         /*
 959          * Ensure that memories for slots built on other CPUs is observed.
 960          */
 961         smp_rmb();
 962         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
 963
 964         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
 965 }
 966
 967 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
 968                               struct hisi_sas_slot *slot,
 969                               struct hisi_sas_cmd_hdr *hdr,
 970                               struct scatterlist *scatter,
 971                               int n_elem)
 972 {
 973         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
 974         struct scatterlist *sg;
 975         int i;
 976
 977         for_each_sg(scatter, sg, n_elem, i) {
 978                 struct hisi_sas_sge *entry = &sge_page->sge[i];
 979
 980                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 981                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 982                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 983                 entry->data_off = 0;
 984         }
 985
 986         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
 987
 988         hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 989 }
 990
 991 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
 992                                    struct hisi_sas_slot *slot,
 993                                    struct hisi_sas_cmd_hdr *hdr,
 994                                    struct scatterlist *scatter,
 995                                    int n_elem)
 996 {
 997         struct hisi_sas_sge_dif_page *sge_dif_page;
 998         struct scatterlist *sg;
 999         int i;
1000
1001         sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1002
1003         for_each_sg(scatter, sg, n_elem, i) {
1004                 struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1005
1006                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1007                 entry->page_ctrl_0 = 0;
1008                 entry->page_ctrl_1 = 0;
1009                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1010                 entry->data_off = 0;
1011         }
1012
1013         hdr->dif_prd_table_addr =
1014                 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1015
1016         hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1017 }
1018
1019 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1020 {
1021         unsigned char prot_flags = scsi_cmnd->prot_flags;
1022
1023         if (prot_flags & SCSI_PROT_REF_CHECK)
1024                 return T10_CHK_APP_TAG_MSK;
1025         return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1026 }
1027
1028 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1029                             struct hisi_sas_protect_iu_v3_hw *prot)
1030 {
1031         unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1032         unsigned int interval = scsi_prot_interval(scsi_cmnd);
1033         u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request);
1034
1035         switch (prot_op) {
1036         case SCSI_PROT_READ_INSERT:
1037                 prot->dw0 |= T10_INSRT_EN_MSK;
1038                 prot->lbrtgv = lbrt_chk_val;
1039                 break;
1040         case SCSI_PROT_READ_STRIP:
1041                 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1042                 prot->lbrtcv = lbrt_chk_val;
1043                 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1044                 break;
1045         case SCSI_PROT_READ_PASS:
1046                 prot->dw0 |= T10_CHK_EN_MSK;
1047                 prot->lbrtcv = lbrt_chk_val;
1048                 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1049                 break;
1050         case SCSI_PROT_WRITE_INSERT:
1051                 prot->dw0 |= T10_INSRT_EN_MSK;
1052                 prot->lbrtgv = lbrt_chk_val;
1053                 break;
1054         case SCSI_PROT_WRITE_STRIP:
1055                 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1056                 prot->lbrtcv = lbrt_chk_val;
1057                 break;
1058         case SCSI_PROT_WRITE_PASS:
1059                 prot->dw0 |= T10_CHK_EN_MSK;
1060                 prot->lbrtcv = lbrt_chk_val;
1061                 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1062                 break;
1063         default:
1064                 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1065                 break;
1066         }
1067
1068         switch (interval) {
1069         case 512:
1070                 break;
1071         case 4096:
1072                 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1073                 break;
1074         case 520:
1075                 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1076                 break;
1077         default:
1078                 WARN(1, "protection interval (0x%x) invalid\n",
1079                      interval);
1080                 break;
1081         }
1082
1083         prot->dw0 |= INCR_LBRT_MSK;
1084 }
1085
1086 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1087                           struct hisi_sas_slot *slot)
1088 {
1089         struct sas_task *task = slot->task;
1090         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1091         struct domain_device *device = task->dev;
1092         struct hisi_sas_device *sas_dev = device->lldd_dev;
1093         struct hisi_sas_port *port = slot->port;
1094         struct sas_ssp_task *ssp_task = &task->ssp_task;
1095         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1096         struct hisi_sas_tmf_task *tmf = slot->tmf;
1097         int has_data = 0, priority = !!tmf;
1098         unsigned char prot_op;
1099         u8 *buf_cmd;
1100         u32 dw1 = 0, dw2 = 0, len = 0;
1101
1102         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1103                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1104                                (port->id << CMD_HDR_PORT_OFF) |
1105                                (priority << CMD_HDR_PRIORITY_OFF) |
1106                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1107
1108         dw1 = 1 << CMD_HDR_VDTL_OFF;
1109         if (tmf) {
1110                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1111                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1112         } else {
1113                 prot_op = scsi_get_prot_op(scsi_cmnd);
1114                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1115                 switch (scsi_cmnd->sc_data_direction) {
1116                 case DMA_TO_DEVICE:
1117                         has_data = 1;
1118                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1119                         break;
1120                 case DMA_FROM_DEVICE:
1121                         has_data = 1;
1122                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1123                         break;
1124                 default:
1125                         dw1 &= ~CMD_HDR_DIR_MSK;
1126                 }
1127         }
1128
1129         /* map itct entry */
1130         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1131
1132         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1133               + 3) / 4) << CMD_HDR_CFL_OFF) |
1134               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1135               (2 << CMD_HDR_SG_MOD_OFF);
1136         hdr->dw2 = cpu_to_le32(dw2);
1137         hdr->transfer_tags = cpu_to_le32(slot->idx);
1138
1139         if (has_data) {
1140                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1141                                    slot->n_elem);
1142
1143                 if (scsi_prot_sg_count(scsi_cmnd))
1144                         prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1145                                                scsi_prot_sglist(scsi_cmnd),
1146                                                slot->n_elem_dif);
1147         }
1148
1149         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1150         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1151
1152         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1153                 sizeof(struct ssp_frame_hdr);
1154
1155         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1156         if (!tmf) {
1157                 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1158                 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1159         } else {
1160                 buf_cmd[10] = tmf->tmf;
1161                 switch (tmf->tmf) {
1162                 case TMF_ABORT_TASK:
1163                 case TMF_QUERY_TASK:
1164                         buf_cmd[12] =
1165                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1166                         buf_cmd[13] =
1167                                 tmf->tag_of_task_to_be_managed & 0xff;
1168                         break;
1169                 default:
1170                         break;
1171                 }
1172         }
1173
1174         if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1175                 struct hisi_sas_protect_iu_v3_hw prot;
1176                 u8 *buf_cmd_prot;
1177
1178                 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1179                 dw1 |= CMD_HDR_PIR_MSK;
1180                 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1181                                sizeof(struct ssp_frame_hdr) +
1182                                sizeof(struct ssp_command_iu);
1183
1184                 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1185                 fill_prot_v3_hw(scsi_cmnd, &prot);
1186                 memcpy(buf_cmd_prot, &prot,
1187                        sizeof(struct hisi_sas_protect_iu_v3_hw));
1188                 /*
1189                  * For READ, we need length of info read to memory, while for
1190                  * WRITE we need length of data written to the disk.
1191                  */
1192                 if (prot_op == SCSI_PROT_WRITE_INSERT ||
1193                     prot_op == SCSI_PROT_READ_INSERT ||
1194                     prot_op == SCSI_PROT_WRITE_PASS ||
1195                     prot_op == SCSI_PROT_READ_PASS) {
1196                         unsigned int interval = scsi_prot_interval(scsi_cmnd);
1197                         unsigned int ilog2_interval = ilog2(interval);
1198
1199                         len = (task->total_xfer_len >> ilog2_interval) * 8;
1200                 }
1201         }
1202
1203         hdr->dw1 = cpu_to_le32(dw1);
1204
1205         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1206 }
1207
1208 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1209                           struct hisi_sas_slot *slot)
1210 {
1211         struct sas_task *task = slot->task;
1212         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1213         struct domain_device *device = task->dev;
1214         struct hisi_sas_port *port = slot->port;
1215         struct scatterlist *sg_req;
1216         struct hisi_sas_device *sas_dev = device->lldd_dev;
1217         dma_addr_t req_dma_addr;
1218         unsigned int req_len;
1219
1220         /* req */
1221         sg_req = &task->smp_task.smp_req;
1222         req_len = sg_dma_len(sg_req);
1223         req_dma_addr = sg_dma_address(sg_req);
1224
1225         /* create header */
1226         /* dw0 */
1227         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1228                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1229                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1230
1231         /* map itct entry */
1232         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1233                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1234                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1235
1236         /* dw2 */
1237         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1238                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1239                                CMD_HDR_MRFL_OFF));
1240
1241         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1242
1243         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1244         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1245
1246 }
1247
1248 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1249                           struct hisi_sas_slot *slot)
1250 {
1251         struct sas_task *task = slot->task;
1252         struct domain_device *device = task->dev;
1253         struct domain_device *parent_dev = device->parent;
1254         struct hisi_sas_device *sas_dev = device->lldd_dev;
1255         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1256         struct asd_sas_port *sas_port = device->port;
1257         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1258         u8 *buf_cmd;
1259         int has_data = 0, hdr_tag = 0;
1260         u32 dw1 = 0, dw2 = 0;
1261
1262         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1263         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1264                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1265         else
1266                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1267
1268         switch (task->data_dir) {
1269         case DMA_TO_DEVICE:
1270                 has_data = 1;
1271                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1272                 break;
1273         case DMA_FROM_DEVICE:
1274                 has_data = 1;
1275                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1276                 break;
1277         default:
1278                 dw1 &= ~CMD_HDR_DIR_MSK;
1279         }
1280
1281         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1282                         (task->ata_task.fis.control & ATA_SRST))
1283                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1284
1285         dw1 |= (hisi_sas_get_ata_protocol(
1286                 &task->ata_task.fis, task->data_dir))
1287                 << CMD_HDR_FRAME_TYPE_OFF;
1288         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1289
1290         if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1291                 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1292
1293         hdr->dw1 = cpu_to_le32(dw1);
1294
1295         /* dw2 */
1296         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1297                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1298                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1299         }
1300
1301         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1302                         2 << CMD_HDR_SG_MOD_OFF;
1303         hdr->dw2 = cpu_to_le32(dw2);
1304
1305         /* dw3 */
1306         hdr->transfer_tags = cpu_to_le32(slot->idx);
1307
1308         if (has_data)
1309                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1310                                         slot->n_elem);
1311
1312         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1313         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1314         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1315
1316         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1317
1318         if (likely(!task->ata_task.device_control_reg_update))
1319                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1320         /* fill in command FIS */
1321         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1322 }
1323
1324 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1325                 struct hisi_sas_slot *slot,
1326                 int device_id, int abort_flag, int tag_to_abort)
1327 {
1328         struct sas_task *task = slot->task;
1329         struct domain_device *dev = task->dev;
1330         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1331         struct hisi_sas_port *port = slot->port;
1332
1333         /* dw0 */
1334         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1335                                (port->id << CMD_HDR_PORT_OFF) |
1336                                    (dev_is_sata(dev)
1337                                         << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1338                                         (abort_flag
1339                                          << CMD_HDR_ABORT_FLAG_OFF));
1340
1341         /* dw1 */
1342         hdr->dw1 = cpu_to_le32(device_id
1343                         << CMD_HDR_DEV_ID_OFF);
1344
1345         /* dw7 */
1346         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1347         hdr->transfer_tags = cpu_to_le32(slot->idx);
1348
1349 }
1350
1351 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1352 {
1353         int i;
1354         irqreturn_t res;
1355         u32 context, port_id, link_rate;
1356         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1357         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1358         struct device *dev = hisi_hba->dev;
1359         unsigned long flags;
1360
1361         del_timer(&phy->timer);
1362         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1363
1364         port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1365         port_id = (port_id >> (4 * phy_no)) & 0xf;
1366         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1367         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1368
1369         if (port_id == 0xf) {
1370                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1371                 res = IRQ_NONE;
1372                 goto end;
1373         }
1374         sas_phy->linkrate = link_rate;
1375         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1376
1377         /* Check for SATA dev */
1378         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1379         if (context & (1 << phy_no)) {
1380                 struct hisi_sas_initial_fis *initial_fis;
1381                 struct dev_to_host_fis *fis;
1382                 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1383
1384                 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1385                 initial_fis = &hisi_hba->initial_fis[phy_no];
1386                 fis = &initial_fis->fis;
1387
1388                 /* check ERR bit of Status Register */
1389                 if (fis->status & ATA_ERR) {
1390                         dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1391                                  phy_no, fis->status);
1392                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1393                         res = IRQ_NONE;
1394                         goto end;
1395                 }
1396
1397                 sas_phy->oob_mode = SATA_OOB_MODE;
1398                 attached_sas_addr[0] = 0x50;
1399                 attached_sas_addr[7] = phy_no;
1400                 memcpy(sas_phy->attached_sas_addr,
1401                        attached_sas_addr,
1402                        SAS_ADDR_SIZE);
1403                 memcpy(sas_phy->frame_rcvd, fis,
1404                        sizeof(struct dev_to_host_fis));
1405                 phy->phy_type |= PORT_TYPE_SATA;
1406                 phy->identify.device_type = SAS_SATA_DEV;
1407                 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1408                 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1409         } else {
1410                 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1411                 struct sas_identify_frame *id =
1412                         (struct sas_identify_frame *)frame_rcvd;
1413
1414                 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1415                 for (i = 0; i < 6; i++) {
1416                         u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1417                                                RX_IDAF_DWORD0 + (i * 4));
1418                         frame_rcvd[i] = __swab32(idaf);
1419                 }
1420                 sas_phy->oob_mode = SAS_OOB_MODE;
1421                 memcpy(sas_phy->attached_sas_addr,
1422                        &id->sas_addr,
1423                        SAS_ADDR_SIZE);
1424                 phy->phy_type |= PORT_TYPE_SAS;
1425                 phy->identify.device_type = id->dev_type;
1426                 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1427                 if (phy->identify.device_type == SAS_END_DEVICE)
1428                         phy->identify.target_port_protocols =
1429                                 SAS_PROTOCOL_SSP;
1430                 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1431                         phy->identify.target_port_protocols =
1432                                 SAS_PROTOCOL_SMP;
1433         }
1434
1435         phy->port_id = port_id;
1436         phy->phy_attached = 1;
1437         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1438         res = IRQ_HANDLED;
1439         spin_lock_irqsave(&phy->lock, flags);
1440         if (phy->reset_completion) {
1441                 phy->in_reset = 0;
1442                 complete(phy->reset_completion);
1443         }
1444         spin_unlock_irqrestore(&phy->lock, flags);
1445 end:
1446         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1447                              CHL_INT0_SL_PHY_ENABLE_MSK);
1448         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1449
1450         return res;
1451 }
1452
1453 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1454 {
1455         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1456         u32 phy_state, sl_ctrl, txid_auto;
1457         struct device *dev = hisi_hba->dev;
1458
1459         del_timer(&phy->timer);
1460         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1461
1462         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1463         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1464         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1465
1466         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1467         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1468                                                 sl_ctrl&(~SL_CTA_MSK));
1469
1470         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1471         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1472                                                 txid_auto | CT3_MSK);
1473
1474         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1475         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1476
1477         return IRQ_HANDLED;
1478 }
1479
1480 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1481 {
1482         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1483         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1484         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1485         u32 bcast_status;
1486
1487         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1488         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1489         if ((bcast_status & RX_BCAST_CHG_MSK) &&
1490             !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1491                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1492         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1493                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1494         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1495
1496         return IRQ_HANDLED;
1497 }
1498
1499 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1500 {
1501         struct hisi_hba *hisi_hba = p;
1502         u32 irq_msk;
1503         int phy_no = 0;
1504         irqreturn_t res = IRQ_NONE;
1505
1506         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1507                                 & 0x11111111;
1508         while (irq_msk) {
1509                 if (irq_msk  & 1) {
1510                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1511                                                             CHL_INT0);
1512                         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1513                         int rdy = phy_state & (1 << phy_no);
1514
1515                         if (rdy) {
1516                                 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1517                                         /* phy up */
1518                                         if (phy_up_v3_hw(phy_no, hisi_hba)
1519                                                         == IRQ_HANDLED)
1520                                                 res = IRQ_HANDLED;
1521                                 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1522                                         /* phy bcast */
1523                                         if (phy_bcast_v3_hw(phy_no, hisi_hba)
1524                                                         == IRQ_HANDLED)
1525                                                 res = IRQ_HANDLED;
1526                         } else {
1527                                 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1528                                         /* phy down */
1529                                         if (phy_down_v3_hw(phy_no, hisi_hba)
1530                                                         == IRQ_HANDLED)
1531                                                 res = IRQ_HANDLED;
1532                         }
1533                 }
1534                 irq_msk >>= 4;
1535                 phy_no++;
1536         }
1537
1538         return res;
1539 }
1540
1541 static const struct hisi_sas_hw_error port_axi_error[] = {
1542         {
1543                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1544                 .msg = "dma_tx_axi_wr_err",
1545         },
1546         {
1547                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1548                 .msg = "dma_tx_axi_rd_err",
1549         },
1550         {
1551                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1552                 .msg = "dma_rx_axi_wr_err",
1553         },
1554         {
1555                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1556                 .msg = "dma_rx_axi_rd_err",
1557         },
1558 };
1559
1560 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1561 {
1562         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1563         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1564         struct device *dev = hisi_hba->dev;
1565         int i;
1566
1567         irq_value &= ~irq_msk;
1568         if (!irq_value)
1569                 return;
1570
1571         for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1572                 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1573
1574                 if (!(irq_value & error->irq_msk))
1575                         continue;
1576
1577                 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1578                         error->msg, phy_no, irq_value);
1579                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1580         }
1581
1582         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1583 }
1584
1585 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1586 {
1587         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1588         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1589         struct sas_phy *sphy = sas_phy->phy;
1590         unsigned long flags;
1591         u32 reg_value;
1592
1593         spin_lock_irqsave(&phy->lock, flags);
1594
1595         /* loss dword sync */
1596         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1597         sphy->loss_of_dword_sync_count += reg_value;
1598
1599         /* phy reset problem */
1600         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1601         sphy->phy_reset_problem_count += reg_value;
1602
1603         /* invalid dword */
1604         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1605         sphy->invalid_dword_count += reg_value;
1606
1607         /* disparity err */
1608         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1609         sphy->running_disparity_error_count += reg_value;
1610
1611         /* code violation error */
1612         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1613         phy->code_violation_err_count += reg_value;
1614
1615         spin_unlock_irqrestore(&phy->lock, flags);
1616 }
1617
1618 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1619 {
1620         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1621         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1622         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1623         struct pci_dev *pci_dev = hisi_hba->pci_dev;
1624         struct device *dev = hisi_hba->dev;
1625         static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1626                         BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1627                         BIT(CHL_INT2_RX_INVLD_DW_OFF);
1628
1629         irq_value &= ~irq_msk;
1630         if (!irq_value)
1631                 return;
1632
1633         if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1634                 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1635                 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1636         }
1637
1638         if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1639                 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1640                                 STP_LINK_TIMEOUT_STATE);
1641
1642                 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1643                          phy_no, reg_value);
1644                 if (reg_value & BIT(4))
1645                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1646         }
1647
1648         if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1649                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1650                 struct sas_phy *sphy = sas_phy->phy;
1651
1652                 phy_get_events_v3_hw(hisi_hba, phy_no);
1653
1654                 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1655                         dev_info(dev, "phy%d invalid dword cnt:   %u\n", phy_no,
1656                                  sphy->invalid_dword_count);
1657
1658                 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1659                         dev_info(dev, "phy%d code violation cnt:  %u\n", phy_no,
1660                                  phy->code_violation_err_count);
1661
1662                 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1663                         dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1664                                  sphy->running_disparity_error_count);
1665         }
1666
1667         if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1668             (pci_dev->revision == 0x20)) {
1669                 u32 reg_value;
1670                 int rc;
1671
1672                 rc = hisi_sas_read32_poll_timeout_atomic(
1673                                 HILINK_ERR_DFX, reg_value,
1674                                 !((reg_value >> 8) & BIT(phy_no)),
1675                                 1000, 10000);
1676                 if (rc)
1677                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1678         }
1679
1680         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1681 }
1682
1683 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1684 {
1685         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1686
1687         if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1688                 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1689
1690         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1691                              irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1692                              & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1693                              & (~CHL_INT0_NOT_RDY_MSK));
1694 }
1695
1696 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1697 {
1698         struct hisi_hba *hisi_hba = p;
1699         u32 irq_msk;
1700         int phy_no = 0;
1701
1702         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1703                                 & 0xeeeeeeee;
1704
1705         while (irq_msk) {
1706                 if (irq_msk & (2 << (phy_no * 4)))
1707                         handle_chl_int0_v3_hw(hisi_hba, phy_no);
1708
1709                 if (irq_msk & (4 << (phy_no * 4)))
1710                         handle_chl_int1_v3_hw(hisi_hba, phy_no);
1711
1712                 if (irq_msk & (8 << (phy_no * 4)))
1713                         handle_chl_int2_v3_hw(hisi_hba, phy_no);
1714
1715                 irq_msk &= ~(0xe << (phy_no * 4));
1716                 phy_no++;
1717         }
1718
1719         return IRQ_HANDLED;
1720 }
1721
1722 static const struct hisi_sas_hw_error axi_error[] = {
1723         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1724         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1725         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1726         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1727         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1728         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1729         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1730         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1731         {},
1732 };
1733
1734 static const struct hisi_sas_hw_error fifo_error[] = {
1735         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
1736         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
1737         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1738         { .msk = BIT(11), .msg = "CMDP_FIFO" },
1739         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1740         {},
1741 };
1742
1743 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1744         {
1745                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1746                 .msg = "write pointer and depth",
1747         },
1748         {
1749                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1750                 .msg = "iptt no match slot",
1751         },
1752         {
1753                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1754                 .msg = "read pointer and depth",
1755         },
1756         {
1757                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1758                 .reg = HGC_AXI_FIFO_ERR_INFO,
1759                 .sub = axi_error,
1760         },
1761         {
1762                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1763                 .reg = HGC_AXI_FIFO_ERR_INFO,
1764                 .sub = fifo_error,
1765         },
1766         {
1767                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1768                 .msg = "LM add/fetch list",
1769         },
1770         {
1771                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1772                 .msg = "SAS_HGC_ABT fetch LM list",
1773         },
1774 };
1775
1776 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1777 {
1778         u32 irq_value, irq_msk;
1779         struct hisi_hba *hisi_hba = p;
1780         struct device *dev = hisi_hba->dev;
1781         struct pci_dev *pdev = hisi_hba->pci_dev;
1782         int i;
1783
1784         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1785         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1786
1787         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1788         irq_value &= ~irq_msk;
1789
1790         for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1791                 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1792
1793                 if (!(irq_value & error->irq_msk))
1794                         continue;
1795
1796                 if (error->sub) {
1797                         const struct hisi_sas_hw_error *sub = error->sub;
1798                         u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1799
1800                         for (; sub->msk || sub->msg; sub++) {
1801                                 if (!(err_value & sub->msk))
1802                                         continue;
1803
1804                                 dev_err(dev, "%s error (0x%x) found!\n",
1805                                         sub->msg, irq_value);
1806                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1807                         }
1808                 } else {
1809                         dev_err(dev, "%s error (0x%x) found!\n",
1810                                 error->msg, irq_value);
1811                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1812                 }
1813
1814                 if (pdev->revision < 0x21) {
1815                         u32 reg_val;
1816
1817                         reg_val = hisi_sas_read32(hisi_hba,
1818                                                   AXI_MASTER_CFG_BASE +
1819                                                   AM_CTRL_GLOBAL);
1820                         reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
1821                         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1822                                          AM_CTRL_GLOBAL, reg_val);
1823                 }
1824         }
1825
1826         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1827                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1828                 u32 dev_id = reg_val & ITCT_DEV_MSK;
1829                 struct hisi_sas_device *sas_dev =
1830                                 &hisi_hba->devices[dev_id];
1831
1832                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1833                 dev_dbg(dev, "clear ITCT ok\n");
1834                 complete(sas_dev->completion);
1835         }
1836
1837         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1838         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1839
1840         return IRQ_HANDLED;
1841 }
1842
1843 static void
1844 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1845                struct hisi_sas_slot *slot)
1846 {
1847         struct task_status_struct *ts = &task->task_status;
1848         struct hisi_sas_complete_v3_hdr *complete_queue =
1849                         hisi_hba->complete_hdr[slot->cmplt_queue];
1850         struct hisi_sas_complete_v3_hdr *complete_hdr =
1851                         &complete_queue[slot->cmplt_queue_slot];
1852         struct hisi_sas_err_record_v3 *record =
1853                         hisi_sas_status_buf_addr_mem(slot);
1854         u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
1855         u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
1856         u32 dw3 = le32_to_cpu(complete_hdr->dw3);
1857
1858         switch (task->task_proto) {
1859         case SAS_PROTOCOL_SSP:
1860                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1861                         ts->residual = trans_tx_fail_type;
1862                         ts->stat = SAS_DATA_UNDERRUN;
1863                 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1864                         ts->stat = SAS_QUEUE_FULL;
1865                         slot->abort = 1;
1866                 } else {
1867                         ts->stat = SAS_OPEN_REJECT;
1868                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1869                 }
1870                 break;
1871         case SAS_PROTOCOL_SATA:
1872         case SAS_PROTOCOL_STP:
1873         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1874                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1875                         ts->residual = trans_tx_fail_type;
1876                         ts->stat = SAS_DATA_UNDERRUN;
1877                 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1878                         ts->stat = SAS_PHY_DOWN;
1879                         slot->abort = 1;
1880                 } else {
1881                         ts->stat = SAS_OPEN_REJECT;
1882                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1883                 }
1884                 hisi_sas_sata_done(task, slot);
1885                 break;
1886         case SAS_PROTOCOL_SMP:
1887                 ts->stat = SAM_STAT_CHECK_CONDITION;
1888                 break;
1889         default:
1890                 break;
1891         }
1892 }
1893
1894 static int
1895 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1896 {
1897         struct sas_task *task = slot->task;
1898         struct hisi_sas_device *sas_dev;
1899         struct device *dev = hisi_hba->dev;
1900         struct task_status_struct *ts;
1901         struct domain_device *device;
1902         struct sas_ha_struct *ha;
1903         enum exec_status sts;
1904         struct hisi_sas_complete_v3_hdr *complete_queue =
1905                         hisi_hba->complete_hdr[slot->cmplt_queue];
1906         struct hisi_sas_complete_v3_hdr *complete_hdr =
1907                         &complete_queue[slot->cmplt_queue_slot];
1908         unsigned long flags;
1909         bool is_internal = slot->is_internal;
1910         u32 dw0, dw1, dw3;
1911
1912         if (unlikely(!task || !task->lldd_task || !task->dev))
1913                 return -EINVAL;
1914
1915         ts = &task->task_status;
1916         device = task->dev;
1917         ha = device->port->ha;
1918         sas_dev = device->lldd_dev;
1919
1920         spin_lock_irqsave(&task->task_state_lock, flags);
1921         task->task_state_flags &=
1922                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1923         spin_unlock_irqrestore(&task->task_state_lock, flags);
1924
1925         memset(ts, 0, sizeof(*ts));
1926         ts->resp = SAS_TASK_COMPLETE;
1927
1928         if (unlikely(!sas_dev)) {
1929                 dev_dbg(dev, "slot complete: port has not device\n");
1930                 ts->stat = SAS_PHY_DOWN;
1931                 goto out;
1932         }
1933
1934         dw0 = le32_to_cpu(complete_hdr->dw0);
1935         dw1 = le32_to_cpu(complete_hdr->dw1);
1936         dw3 = le32_to_cpu(complete_hdr->dw3);
1937
1938         /*
1939          * Use SAS+TMF status codes
1940          */
1941         switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
1942         case STAT_IO_ABORTED:
1943                 /* this IO has been aborted by abort command */
1944                 ts->stat = SAS_ABORTED_TASK;
1945                 goto out;
1946         case STAT_IO_COMPLETE:
1947                 /* internal abort command complete */
1948                 ts->stat = TMF_RESP_FUNC_SUCC;
1949                 goto out;
1950         case STAT_IO_NO_DEVICE:
1951                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1952                 goto out;
1953         case STAT_IO_NOT_VALID:
1954                 /*
1955                  * abort single IO, the controller can't find the IO
1956                  */
1957                 ts->stat = TMF_RESP_FUNC_FAILED;
1958                 goto out;
1959         default:
1960                 break;
1961         }
1962
1963         /* check for erroneous completion */
1964         if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1965                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1966
1967                 slot_err_v3_hw(hisi_hba, task, slot);
1968                 if (ts->stat != SAS_DATA_UNDERRUN)
1969                         dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1970                                 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1971                                 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1972                                 slot->idx, task, sas_dev->device_id,
1973                                 dw0, dw1, complete_hdr->act, dw3,
1974                                 error_info[0], error_info[1],
1975                                 error_info[2], error_info[3]);
1976                 if (unlikely(slot->abort))
1977                         return ts->stat;
1978                 goto out;
1979         }
1980
1981         switch (task->task_proto) {
1982         case SAS_PROTOCOL_SSP: {
1983                 struct ssp_response_iu *iu =
1984                         hisi_sas_status_buf_addr_mem(slot) +
1985                         sizeof(struct hisi_sas_err_record);
1986
1987                 sas_ssp_task_response(dev, task, iu);
1988                 break;
1989         }
1990         case SAS_PROTOCOL_SMP: {
1991                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1992                 void *to;
1993
1994                 ts->stat = SAM_STAT_GOOD;
1995                 to = kmap_atomic(sg_page(sg_resp));
1996
1997                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1998                              DMA_FROM_DEVICE);
1999                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2000                              DMA_TO_DEVICE);
2001                 memcpy(to + sg_resp->offset,
2002                         hisi_sas_status_buf_addr_mem(slot) +
2003                        sizeof(struct hisi_sas_err_record),
2004                        sg_dma_len(sg_resp));
2005                 kunmap_atomic(to);
2006                 break;
2007         }
2008         case SAS_PROTOCOL_SATA:
2009         case SAS_PROTOCOL_STP:
2010         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2011                 ts->stat = SAM_STAT_GOOD;
2012                 hisi_sas_sata_done(task, slot);
2013                 break;
2014         default:
2015                 ts->stat = SAM_STAT_CHECK_CONDITION;
2016                 break;
2017         }
2018
2019         if (!slot->port->port_attached) {
2020                 dev_warn(dev, "slot complete: port %d has removed\n",
2021                         slot->port->sas_port.id);
2022                 ts->stat = SAS_PHY_DOWN;
2023         }
2024
2025 out:
2026         sts = ts->stat;
2027         spin_lock_irqsave(&task->task_state_lock, flags);
2028         if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2029                 spin_unlock_irqrestore(&task->task_state_lock, flags);
2030                 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2031                 return SAS_ABORTED_TASK;
2032         }
2033         task->task_state_flags |= SAS_TASK_STATE_DONE;
2034         spin_unlock_irqrestore(&task->task_state_lock, flags);
2035         hisi_sas_slot_task_free(hisi_hba, task, slot);
2036
2037         if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2038                 spin_lock_irqsave(&device->done_lock, flags);
2039                 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2040                         spin_unlock_irqrestore(&device->done_lock, flags);
2041                         dev_info(dev, "slot complete: task(%p) ignored\n ",
2042                                  task);
2043                         return sts;
2044                 }
2045                 spin_unlock_irqrestore(&device->done_lock, flags);
2046         }
2047
2048         if (task->task_done)
2049                 task->task_done(task);
2050
2051         return sts;
2052 }
2053
2054 static void cq_tasklet_v3_hw(unsigned long val)
2055 {
2056         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
2057         struct hisi_hba *hisi_hba = cq->hisi_hba;
2058         struct hisi_sas_slot *slot;
2059         struct hisi_sas_complete_v3_hdr *complete_queue;
2060         u32 rd_point = cq->rd_point, wr_point;
2061         int queue = cq->id;
2062
2063         complete_queue = hisi_hba->complete_hdr[queue];
2064
2065         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2066                                    (0x14 * queue));
2067
2068         while (rd_point != wr_point) {
2069                 struct hisi_sas_complete_v3_hdr *complete_hdr;
2070                 struct device *dev = hisi_hba->dev;
2071                 u32 dw1;
2072                 int iptt;
2073
2074                 complete_hdr = &complete_queue[rd_point];
2075                 dw1 = le32_to_cpu(complete_hdr->dw1);
2076
2077                 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2078                 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2079                         slot = &hisi_hba->slot_info[iptt];
2080                         slot->cmplt_queue_slot = rd_point;
2081                         slot->cmplt_queue = queue;
2082                         slot_complete_v3_hw(hisi_hba, slot);
2083                 } else
2084                         dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2085
2086                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2087                         rd_point = 0;
2088         }
2089
2090         /* update rd_point */
2091         cq->rd_point = rd_point;
2092         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2093 }
2094
2095 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2096 {
2097         struct hisi_sas_cq *cq = p;
2098         struct hisi_hba *hisi_hba = cq->hisi_hba;
2099         int queue = cq->id;
2100
2101         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2102
2103         tasklet_schedule(&cq->tasklet);
2104
2105         return IRQ_HANDLED;
2106 }
2107
2108 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs)
2109 {
2110         const struct cpumask *mask;
2111         int queue, cpu;
2112
2113         for (queue = 0; queue < nvecs; queue++) {
2114                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue];
2115
2116                 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue +
2117                                             BASE_VECTORS_V3_HW);
2118                 if (!mask)
2119                         goto fallback;
2120                 cq->pci_irq_mask = mask;
2121                 for_each_cpu(cpu, mask)
2122                         hisi_hba->reply_map[cpu] = queue;
2123         }
2124         return;
2125
2126 fallback:
2127         for_each_possible_cpu(cpu)
2128                 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count;
2129         /* Don't clean all CQ masks */
2130 }
2131
2132 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2133 {
2134         struct device *dev = hisi_hba->dev;
2135         struct pci_dev *pdev = hisi_hba->pci_dev;
2136         int vectors, rc;
2137         int i, k;
2138         int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2139
2140         if (auto_affine_msi_experimental) {
2141                 struct irq_affinity desc = {
2142                         .pre_vectors = BASE_VECTORS_V3_HW,
2143                 };
2144
2145                 min_msi = MIN_AFFINE_VECTORS_V3_HW;
2146
2147                 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids,
2148                                                    sizeof(unsigned int),
2149                                                    GFP_KERNEL);
2150                 if (!hisi_hba->reply_map)
2151                         return -ENOMEM;
2152                 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev,
2153                                                          min_msi, max_msi,
2154                                                          PCI_IRQ_MSI |
2155                                                          PCI_IRQ_AFFINITY,
2156                                                          &desc);
2157                 if (vectors < 0)
2158                         return -ENOENT;
2159                 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW);
2160         } else {
2161                 min_msi = max_msi;
2162                 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi,
2163                                                 max_msi, PCI_IRQ_MSI);
2164                 if (vectors < 0)
2165                         return vectors;
2166         }
2167
2168         hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2169
2170         rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2171                               int_phy_up_down_bcast_v3_hw, 0,
2172                               DRV_NAME " phy", hisi_hba);
2173         if (rc) {
2174                 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2175                 rc = -ENOENT;
2176                 goto free_irq_vectors;
2177         }
2178
2179         rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2180                               int_chnl_int_v3_hw, 0,
2181                               DRV_NAME " channel", hisi_hba);
2182         if (rc) {
2183                 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2184                 rc = -ENOENT;
2185                 goto free_phy_irq;
2186         }
2187
2188         rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2189                               fatal_axi_int_v3_hw, 0,
2190                               DRV_NAME " fatal", hisi_hba);
2191         if (rc) {
2192                 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2193                 rc = -ENOENT;
2194                 goto free_chnl_interrupt;
2195         }
2196
2197         /* Init tasklets for cq only */
2198         for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2199                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2200                 struct tasklet_struct *t = &cq->tasklet;
2201                 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2202                 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0;
2203
2204                 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr),
2205                                       cq_interrupt_v3_hw, irqflags,
2206                                       DRV_NAME " cq", cq);
2207                 if (rc) {
2208                         dev_err(dev,
2209                                 "could not request cq%d interrupt, rc=%d\n",
2210                                 i, rc);
2211                         rc = -ENOENT;
2212                         goto free_cq_irqs;
2213                 }
2214
2215                 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
2216         }
2217
2218         return 0;
2219
2220 free_cq_irqs:
2221         for (k = 0; k < i; k++) {
2222                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
2223                 int nr = hisi_sas_intr_conv ? 16 : 16 + k;
2224
2225                 free_irq(pci_irq_vector(pdev, nr), cq);
2226         }
2227         free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2228 free_chnl_interrupt:
2229         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2230 free_phy_irq:
2231         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2232 free_irq_vectors:
2233         pci_free_irq_vectors(pdev);
2234         return rc;
2235 }
2236
2237 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2238 {
2239         int rc;
2240
2241         rc = hw_init_v3_hw(hisi_hba);
2242         if (rc)
2243                 return rc;
2244
2245         rc = interrupt_init_v3_hw(hisi_hba);
2246         if (rc)
2247                 return rc;
2248
2249         return 0;
2250 }
2251
2252 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2253                 struct sas_phy_linkrates *r)
2254 {
2255         enum sas_linkrate max = r->maximum_linkrate;
2256         u32 prog_phy_link_rate = 0x800;
2257
2258         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2259         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2260                              prog_phy_link_rate);
2261 }
2262
2263 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2264 {
2265         struct pci_dev *pdev = hisi_hba->pci_dev;
2266         int i;
2267
2268         synchronize_irq(pci_irq_vector(pdev, 1));
2269         synchronize_irq(pci_irq_vector(pdev, 2));
2270         synchronize_irq(pci_irq_vector(pdev, 11));
2271         for (i = 0; i < hisi_hba->queue_count; i++) {
2272                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2273                 synchronize_irq(pci_irq_vector(pdev, i + 16));
2274         }
2275
2276         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2277         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2278         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2279         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2280
2281         for (i = 0; i < hisi_hba->n_phy; i++) {
2282                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2283                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2284                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2285                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2286                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2287         }
2288 }
2289
2290 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2291 {
2292         return hisi_sas_read32(hisi_hba, PHY_STATE);
2293 }
2294
2295 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2296 {
2297         struct device *dev = hisi_hba->dev;
2298         u32 status, reg_val;
2299         int rc;
2300
2301         interrupt_disable_v3_hw(hisi_hba);
2302         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2303         hisi_sas_kill_tasklets(hisi_hba);
2304
2305         hisi_sas_stop_phys(hisi_hba);
2306
2307         mdelay(10);
2308
2309         reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2310                                   AM_CTRL_GLOBAL);
2311         reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2312         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2313                          AM_CTRL_GLOBAL, reg_val);
2314
2315         /* wait until bus idle */
2316         rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2317                                           AM_CURR_TRANS_RETURN, status,
2318                                           status == 0x3, 10, 100);
2319         if (rc) {
2320                 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2321                 return rc;
2322         }
2323
2324         return 0;
2325 }
2326
2327 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2328 {
2329         struct device *dev = hisi_hba->dev;
2330         int rc;
2331
2332         rc = disable_host_v3_hw(hisi_hba);
2333         if (rc) {
2334                 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2335                 return rc;
2336         }
2337
2338         hisi_sas_init_mem(hisi_hba);
2339
2340         return hw_init_v3_hw(hisi_hba);
2341 }
2342
2343 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2344                         u8 reg_index, u8 reg_count, u8 *write_data)
2345 {
2346         struct device *dev = hisi_hba->dev;
2347         u32 *data = (u32 *)write_data;
2348         int i;
2349
2350         switch (reg_type) {
2351         case SAS_GPIO_REG_TX:
2352                 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2353                         dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2354                                 reg_index, reg_index + reg_count - 1);
2355                         return -EINVAL;
2356                 }
2357
2358                 for (i = 0; i < reg_count; i++)
2359                         hisi_sas_write32(hisi_hba,
2360                                          SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2361                                          data[i]);
2362                 break;
2363         default:
2364                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2365                                 reg_type);
2366                 return -EINVAL;
2367         }
2368
2369         return 0;
2370 }
2371
2372 static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2373                                             int delay_ms, int timeout_ms)
2374 {
2375         struct device *dev = hisi_hba->dev;
2376         int entries, entries_old = 0, time;
2377
2378         for (time = 0; time < timeout_ms; time += delay_ms) {
2379                 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2380                 if (entries == entries_old)
2381                         break;
2382
2383                 entries_old = entries;
2384                 msleep(delay_ms);
2385         }
2386
2387         if (time >= timeout_ms)
2388                 return -ETIMEDOUT;
2389
2390         dev_dbg(dev, "wait commands complete %dms\n", time);
2391
2392         return 0;
2393 }
2394
2395 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2396                                     struct device_attribute *attr, char *buf)
2397 {
2398         return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2399 }
2400 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2401
2402 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2403 {
2404         /* config those registers between enable and disable PHYs */
2405         hisi_sas_stop_phys(hisi_hba);
2406
2407         if (hisi_hba->intr_coal_ticks == 0 ||
2408             hisi_hba->intr_coal_count == 0) {
2409                 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2410                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2411                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2412         } else {
2413                 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2414                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2415                                  hisi_hba->intr_coal_ticks);
2416                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2417                                  hisi_hba->intr_coal_count);
2418         }
2419         phys_init_v3_hw(hisi_hba);
2420 }
2421
2422 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2423                                           struct device_attribute *attr,
2424                                           char *buf)
2425 {
2426         struct Scsi_Host *shost = class_to_shost(dev);
2427         struct hisi_hba *hisi_hba = shost_priv(shost);
2428
2429         return scnprintf(buf, PAGE_SIZE, "%u\n",
2430                          hisi_hba->intr_coal_ticks);
2431 }
2432
2433 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2434                                            struct device_attribute *attr,
2435                                            const char *buf, size_t count)
2436 {
2437         struct Scsi_Host *shost = class_to_shost(dev);
2438         struct hisi_hba *hisi_hba = shost_priv(shost);
2439         u32 intr_coal_ticks;
2440         int ret;
2441
2442         ret = kstrtou32(buf, 10, &intr_coal_ticks);
2443         if (ret) {
2444                 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2445                 return -EINVAL;
2446         }
2447
2448         if (intr_coal_ticks >= BIT(24)) {
2449                 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2450                 return -EINVAL;
2451         }
2452
2453         hisi_hba->intr_coal_ticks = intr_coal_ticks;
2454
2455         config_intr_coal_v3_hw(hisi_hba);
2456
2457         return count;
2458 }
2459 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2460
2461 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2462                                           struct device_attribute
2463                                           *attr, char *buf)
2464 {
2465         struct Scsi_Host *shost = class_to_shost(dev);
2466         struct hisi_hba *hisi_hba = shost_priv(shost);
2467
2468         return scnprintf(buf, PAGE_SIZE, "%u\n",
2469                          hisi_hba->intr_coal_count);
2470 }
2471
2472 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2473                 struct device_attribute
2474                 *attr, const char *buf, size_t count)
2475 {
2476         struct Scsi_Host *shost = class_to_shost(dev);
2477         struct hisi_hba *hisi_hba = shost_priv(shost);
2478         u32 intr_coal_count;
2479         int ret;
2480
2481         ret = kstrtou32(buf, 10, &intr_coal_count);
2482         if (ret) {
2483                 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2484                 return -EINVAL;
2485         }
2486
2487         if (intr_coal_count >= BIT(8)) {
2488                 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2489                 return -EINVAL;
2490         }
2491
2492         hisi_hba->intr_coal_count = intr_coal_count;
2493
2494         config_intr_coal_v3_hw(hisi_hba);
2495
2496         return count;
2497 }
2498 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2499
2500 static struct device_attribute *host_attrs_v3_hw[] = {
2501         &dev_attr_phy_event_threshold,
2502         &dev_attr_intr_conv_v3_hw,
2503         &dev_attr_intr_coal_ticks_v3_hw,
2504         &dev_attr_intr_coal_count_v3_hw,
2505         NULL
2506 };
2507
2508 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2509         HISI_SAS_DEBUGFS_REG(PHY_CFG),
2510         HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2511         HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2512         HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2513         HISI_SAS_DEBUGFS_REG(SL_CFG),
2514         HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2515         HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2516         HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2517         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2518         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2519         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2520         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2521         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2522         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2523         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2524         HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2525         HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2526         HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2527         HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2528         HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2529         HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2530         HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2531         HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2532         HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2533         HISI_SAS_DEBUGFS_REG(CHL_INT0),
2534         HISI_SAS_DEBUGFS_REG(CHL_INT1),
2535         HISI_SAS_DEBUGFS_REG(CHL_INT2),
2536         HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2537         HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2538         HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2539         HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2540         HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2541         HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2542         HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2543         HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2544         HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2545         HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2546         HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2547         HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2548         HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2549         HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2550         HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2551         HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2552         HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2553         HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2554         HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2555         HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2556         {}
2557 };
2558
2559 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2560         .lu = debugfs_port_reg_lu,
2561         .count = 0x100,
2562         .base_off = PORT_BASE,
2563         .read_port_reg = hisi_sas_phy_read32,
2564 };
2565
2566 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2567         HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2568         HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2569         HISI_SAS_DEBUGFS_REG(PHY_STATE),
2570         HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2571         HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2572         HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2573         HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2574         HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2575         HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2576         HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2577         HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2578         HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2579         HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2580         HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2581         HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2582         HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2583         HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2584         HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2585         HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2586         HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2587         HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2588         HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2589         HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2590         HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2591         HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2592         HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2593         HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2594         HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2595         HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2596         HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2597         HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2598         HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2599         HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2600         HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2601         HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2602         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2603         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2604         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2605         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2606         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2607         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2608         HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2609         HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2610         HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2611         HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2612         HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2613         HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2614         HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2615         HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2616         HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2617         HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2618         HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2619         HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2620         HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2621         HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2622         HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2623         HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2624         HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2625         HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2626         HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2627         HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2628         HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2629         HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2630         {}
2631 };
2632
2633 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2634         .lu = debugfs_global_reg_lu,
2635         .count = 0x800,
2636         .read_global_reg = hisi_sas_read32,
2637 };
2638
2639 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2640 {
2641         struct device *dev = hisi_hba->dev;
2642
2643         set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2644
2645         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
2646
2647         if (wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000) == -ETIMEDOUT)
2648                 dev_dbg(dev, "Wait commands complete timeout!\n");
2649
2650         hisi_sas_kill_tasklets(hisi_hba);
2651 }
2652
2653 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
2654 {
2655         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
2656                          (u32)((1ULL << hisi_hba->queue_count) - 1));
2657
2658         clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2659 }
2660
2661 static struct scsi_host_template sht_v3_hw = {
2662         .name                   = DRV_NAME,
2663         .module                 = THIS_MODULE,
2664         .queuecommand           = sas_queuecommand,
2665         .target_alloc           = sas_target_alloc,
2666         .slave_configure        = hisi_sas_slave_configure,
2667         .scan_finished          = hisi_sas_scan_finished,
2668         .scan_start             = hisi_sas_scan_start,
2669         .change_queue_depth     = sas_change_queue_depth,
2670         .bios_param             = sas_bios_param,
2671         .this_id                = -1,
2672         .sg_tablesize           = HISI_SAS_SGE_PAGE_CNT,
2673         .sg_prot_tablesize      = HISI_SAS_SGE_PAGE_CNT,
2674         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
2675         .eh_device_reset_handler = sas_eh_device_reset_handler,
2676         .eh_target_reset_handler = sas_eh_target_reset_handler,
2677         .target_destroy         = sas_target_destroy,
2678         .ioctl                  = sas_ioctl,
2679         .shost_attrs            = host_attrs_v3_hw,
2680         .tag_alloc_policy       = BLK_TAG_ALLOC_RR,
2681 };
2682
2683 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2684         .hw_init = hisi_sas_v3_init,
2685         .setup_itct = setup_itct_v3_hw,
2686         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2687         .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2688         .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2689         .clear_itct = clear_itct_v3_hw,
2690         .sl_notify_ssp = sl_notify_ssp_v3_hw,
2691         .prep_ssp = prep_ssp_v3_hw,
2692         .prep_smp = prep_smp_v3_hw,
2693         .prep_stp = prep_ata_v3_hw,
2694         .prep_abort = prep_abort_v3_hw,
2695         .get_free_slot = get_free_slot_v3_hw,
2696         .start_delivery = start_delivery_v3_hw,
2697         .slot_complete = slot_complete_v3_hw,
2698         .phys_init = phys_init_v3_hw,
2699         .phy_start = start_phy_v3_hw,
2700         .phy_disable = disable_phy_v3_hw,
2701         .phy_hard_reset = phy_hard_reset_v3_hw,
2702         .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2703         .phy_set_linkrate = phy_set_linkrate_v3_hw,
2704         .dereg_device = dereg_device_v3_hw,
2705         .soft_reset = soft_reset_v3_hw,
2706         .get_phys_state = get_phys_state_v3_hw,
2707         .get_events = phy_get_events_v3_hw,
2708         .write_gpio = write_gpio_v3_hw,
2709         .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
2710         .debugfs_reg_global = &debugfs_global_reg,
2711         .debugfs_reg_port = &debugfs_port_reg,
2712         .snapshot_prepare = debugfs_snapshot_prepare_v3_hw,
2713         .snapshot_restore = debugfs_snapshot_restore_v3_hw,
2714 };
2715
2716 static struct Scsi_Host *
2717 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2718 {
2719         struct Scsi_Host *shost;
2720         struct hisi_hba *hisi_hba;
2721         struct device *dev = &pdev->dev;
2722
2723         shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
2724         if (!shost) {
2725                 dev_err(dev, "shost alloc failed\n");
2726                 return NULL;
2727         }
2728         hisi_hba = shost_priv(shost);
2729
2730         INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2731         INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler);
2732         hisi_hba->hw = &hisi_sas_v3_hw;
2733         hisi_hba->pci_dev = pdev;
2734         hisi_hba->dev = dev;
2735         hisi_hba->shost = shost;
2736         SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2737
2738         if (prot_mask & ~HISI_SAS_PROT_MASK)
2739                 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
2740                         prot_mask);
2741         else
2742                 hisi_hba->prot_mask = prot_mask;
2743
2744         timer_setup(&hisi_hba->timer, NULL, 0);
2745
2746         if (hisi_sas_get_fw_info(hisi_hba) < 0)
2747                 goto err_out;
2748
2749         if (hisi_sas_alloc(hisi_hba)) {
2750                 hisi_sas_free(hisi_hba);
2751                 goto err_out;
2752         }
2753
2754         return shost;
2755 err_out:
2756         scsi_host_put(shost);
2757         dev_err(dev, "shost alloc failed\n");
2758         return NULL;
2759 }
2760
2761 static int
2762 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2763 {
2764         struct Scsi_Host *shost;
2765         struct hisi_hba *hisi_hba;
2766         struct device *dev = &pdev->dev;
2767         struct asd_sas_phy **arr_phy;
2768         struct asd_sas_port **arr_port;
2769         struct sas_ha_struct *sha;
2770         int rc, phy_nr, port_nr, i;
2771
2772         rc = pci_enable_device(pdev);
2773         if (rc)
2774                 goto err_out;
2775
2776         pci_set_master(pdev);
2777
2778         rc = pci_request_regions(pdev, DRV_NAME);
2779         if (rc)
2780                 goto err_out_disable_device;
2781
2782         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2783         if (rc)
2784                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2785         if (rc) {
2786                 dev_err(dev, "No usable DMA addressing method\n");
2787                 rc = -ENODEV;
2788                 goto err_out_regions;
2789         }
2790
2791         shost = hisi_sas_shost_alloc_pci(pdev);
2792         if (!shost) {
2793                 rc = -ENOMEM;
2794                 goto err_out_regions;
2795         }
2796
2797         sha = SHOST_TO_SAS_HA(shost);
2798         hisi_hba = shost_priv(shost);
2799         dev_set_drvdata(dev, sha);
2800
2801         hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2802         if (!hisi_hba->regs) {
2803                 dev_err(dev, "cannot map register.\n");
2804                 rc = -ENOMEM;
2805                 goto err_out_ha;
2806         }
2807
2808         phy_nr = port_nr = hisi_hba->n_phy;
2809
2810         arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2811         arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2812         if (!arr_phy || !arr_port) {
2813                 rc = -ENOMEM;
2814                 goto err_out_ha;
2815         }
2816
2817         sha->sas_phy = arr_phy;
2818         sha->sas_port = arr_port;
2819         sha->core.shost = shost;
2820         sha->lldd_ha = hisi_hba;
2821
2822         shost->transportt = hisi_sas_stt;
2823         shost->max_id = HISI_SAS_MAX_DEVICES;
2824         shost->max_lun = ~0;
2825         shost->max_channel = 1;
2826         shost->max_cmd_len = 16;
2827         shost->can_queue = hisi_hba->hw->max_command_entries -
2828                 HISI_SAS_RESERVED_IPTT_CNT;
2829         shost->cmd_per_lun = hisi_hba->hw->max_command_entries -
2830                 HISI_SAS_RESERVED_IPTT_CNT;
2831
2832         sha->sas_ha_name = DRV_NAME;
2833         sha->dev = dev;
2834         sha->lldd_module = THIS_MODULE;
2835         sha->sas_addr = &hisi_hba->sas_addr[0];
2836         sha->num_phys = hisi_hba->n_phy;
2837         sha->core.shost = hisi_hba->shost;
2838
2839         for (i = 0; i < hisi_hba->n_phy; i++) {
2840                 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2841                 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2842         }
2843
2844         if (hisi_hba->prot_mask) {
2845                 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
2846                          prot_mask);
2847                 scsi_host_set_prot(hisi_hba->shost, prot_mask);
2848                 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
2849                         scsi_host_set_guard(hisi_hba->shost,
2850                                             SHOST_DIX_GUARD_CRC);
2851         }
2852
2853         if (hisi_sas_debugfs_enable)
2854                 hisi_sas_debugfs_init(hisi_hba);
2855
2856         rc = scsi_add_host(shost, dev);
2857         if (rc)
2858                 goto err_out_ha;
2859
2860         rc = sas_register_ha(sha);
2861         if (rc)
2862                 goto err_out_register_ha;
2863
2864         rc = hisi_hba->hw->hw_init(hisi_hba);
2865         if (rc)
2866                 goto err_out_register_ha;
2867
2868         scsi_scan_host(shost);
2869
2870         return 0;
2871
2872 err_out_register_ha:
2873         scsi_remove_host(shost);
2874 err_out_ha:
2875         scsi_host_put(shost);
2876 err_out_regions:
2877         pci_release_regions(pdev);
2878 err_out_disable_device:
2879         pci_disable_device(pdev);
2880 err_out:
2881         return rc;
2882 }
2883
2884 static void
2885 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2886 {
2887         int i;
2888
2889         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2890         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2891         free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2892         for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2893                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2894                 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2895
2896                 free_irq(pci_irq_vector(pdev, nr), cq);
2897         }
2898         pci_free_irq_vectors(pdev);
2899 }
2900
2901 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2902 {
2903         struct device *dev = &pdev->dev;
2904         struct sas_ha_struct *sha = dev_get_drvdata(dev);
2905         struct hisi_hba *hisi_hba = sha->lldd_ha;
2906         struct Scsi_Host *shost = sha->core.shost;
2907
2908         hisi_sas_debugfs_exit(hisi_hba);
2909
2910         if (timer_pending(&hisi_hba->timer))
2911                 del_timer(&hisi_hba->timer);
2912
2913         sas_unregister_ha(sha);
2914         sas_remove_host(sha->core.shost);
2915
2916         hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2917         hisi_sas_kill_tasklets(hisi_hba);
2918         pci_release_regions(pdev);
2919         pci_disable_device(pdev);
2920         hisi_sas_free(hisi_hba);
2921         scsi_host_put(shost);
2922 }
2923
2924 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2925         { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2926         { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2927         { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2928         { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2929         { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2930         { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2931         { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2932         { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2933         { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2934         { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2935         { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2936         { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2937         { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2938 };
2939
2940 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2941         { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2942         { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2943         { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2944         { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2945         { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2946         { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2947         { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2948         { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2949         { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2950         { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2951         { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2952         { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2953         { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2954         { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2955         { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2956         { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2957         { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2958         { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2959         { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2960         { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2961         { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2962         { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2963         { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2964         { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2965         { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2966         { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2967         { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2968         { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2969         { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2970         { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2971         { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2972 };
2973
2974 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2975         { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2976         { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2977         { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2978         { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2979         { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2980         { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2981         { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2982         { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2983         { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2984         { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2985         { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2986         { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2987         { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2988         { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2989         { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2990         { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2991         { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2992         { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2993         { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2994         { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2995 };
2996
2997 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2998 {
2999         struct device *dev = hisi_hba->dev;
3000         const struct hisi_sas_hw_error *ras_error;
3001         bool need_reset = false;
3002         u32 irq_value;
3003         int i;
3004
3005         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
3006         for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
3007                 ras_error = &sas_ras_intr0_nfe[i];
3008                 if (ras_error->irq_msk & irq_value) {
3009                         dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
3010                                         ras_error->msg, irq_value);
3011                         need_reset = true;
3012                 }
3013         }
3014         hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
3015
3016         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
3017         for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
3018                 ras_error = &sas_ras_intr1_nfe[i];
3019                 if (ras_error->irq_msk & irq_value) {
3020                         dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
3021                                         ras_error->msg, irq_value);
3022                         need_reset = true;
3023                 }
3024         }
3025         hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
3026
3027         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
3028         for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
3029                 ras_error = &sas_ras_intr2_nfe[i];
3030                 if (ras_error->irq_msk & irq_value) {
3031                         dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
3032                                         ras_error->msg, irq_value);
3033                         need_reset = true;
3034                 }
3035         }
3036         hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
3037
3038         return need_reset;
3039 }
3040
3041 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
3042                 pci_channel_state_t state)
3043 {
3044         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3045         struct hisi_hba *hisi_hba = sha->lldd_ha;
3046         struct device *dev = hisi_hba->dev;
3047
3048         dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
3049         if (state == pci_channel_io_perm_failure)
3050                 return PCI_ERS_RESULT_DISCONNECT;
3051
3052         if (process_non_fatal_error_v3_hw(hisi_hba))
3053                 return PCI_ERS_RESULT_NEED_RESET;
3054
3055         return PCI_ERS_RESULT_CAN_RECOVER;
3056 }
3057
3058 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
3059 {
3060         return PCI_ERS_RESULT_RECOVERED;
3061 }
3062
3063 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
3064 {
3065         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3066         struct hisi_hba *hisi_hba = sha->lldd_ha;
3067         struct device *dev = hisi_hba->dev;
3068         HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
3069
3070         dev_info(dev, "PCI error: slot reset callback!!\n");
3071         queue_work(hisi_hba->wq, &r.work);
3072         wait_for_completion(r.completion);
3073         if (r.done)
3074                 return PCI_ERS_RESULT_RECOVERED;
3075
3076         return PCI_ERS_RESULT_DISCONNECT;
3077 }
3078
3079 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
3080 {
3081         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3082         struct hisi_hba *hisi_hba = sha->lldd_ha;
3083         struct device *dev = hisi_hba->dev;
3084         int rc;
3085
3086         dev_info(dev, "FLR prepare\n");
3087         set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3088         hisi_sas_controller_reset_prepare(hisi_hba);
3089
3090         rc = disable_host_v3_hw(hisi_hba);
3091         if (rc)
3092                 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
3093 }
3094
3095 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
3096 {
3097         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3098         struct hisi_hba *hisi_hba = sha->lldd_ha;
3099         struct device *dev = hisi_hba->dev;
3100         int rc;
3101
3102         hisi_sas_init_mem(hisi_hba);
3103
3104         rc = hw_init_v3_hw(hisi_hba);
3105         if (rc) {
3106                 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
3107                 return;
3108         }
3109
3110         hisi_sas_controller_reset_done(hisi_hba);
3111         dev_info(dev, "FLR done\n");
3112 }
3113
3114 enum {
3115         /* instances of the controller */
3116         hip08,
3117 };
3118
3119 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
3120 {
3121         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3122         struct hisi_hba *hisi_hba = sha->lldd_ha;
3123         struct device *dev = hisi_hba->dev;
3124         struct Scsi_Host *shost = hisi_hba->shost;
3125         pci_power_t device_state;
3126         int rc;
3127
3128         if (!pdev->pm_cap) {
3129                 dev_err(dev, "PCI PM not supported\n");
3130                 return -ENODEV;
3131         }
3132
3133         if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
3134                 return -1;
3135
3136         scsi_block_requests(shost);
3137         set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3138         flush_workqueue(hisi_hba->wq);
3139
3140         rc = disable_host_v3_hw(hisi_hba);
3141         if (rc) {
3142                 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
3143                 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3144                 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3145                 scsi_unblock_requests(shost);
3146                 return rc;
3147         }
3148
3149         hisi_sas_init_mem(hisi_hba);
3150
3151         device_state = pci_choose_state(pdev, state);
3152         dev_warn(dev, "entering operating state [D%d]\n",
3153                         device_state);
3154         pci_save_state(pdev);
3155         pci_disable_device(pdev);
3156         pci_set_power_state(pdev, device_state);
3157
3158         hisi_sas_release_tasks(hisi_hba);
3159
3160         sas_suspend_ha(sha);
3161         return 0;
3162 }
3163
3164 static int hisi_sas_v3_resume(struct pci_dev *pdev)
3165 {
3166         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3167         struct hisi_hba *hisi_hba = sha->lldd_ha;
3168         struct Scsi_Host *shost = hisi_hba->shost;
3169         struct device *dev = hisi_hba->dev;
3170         unsigned int rc;
3171         pci_power_t device_state = pdev->current_state;
3172
3173         dev_warn(dev, "resuming from operating state [D%d]\n",
3174                         device_state);
3175         pci_set_power_state(pdev, PCI_D0);
3176         pci_enable_wake(pdev, PCI_D0, 0);
3177         pci_restore_state(pdev);
3178         rc = pci_enable_device(pdev);
3179         if (rc)
3180                 dev_err(dev, "enable device failed during resume (%d)\n", rc);
3181
3182         pci_set_master(pdev);
3183         scsi_unblock_requests(shost);
3184         clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3185
3186         sas_prep_resume_ha(sha);
3187         init_reg_v3_hw(hisi_hba);
3188         hisi_hba->hw->phys_init(hisi_hba);
3189         sas_resume_ha(sha);
3190         clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3191
3192         return 0;
3193 }
3194
3195 static const struct pci_device_id sas_v3_pci_table[] = {
3196         { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
3197         {}
3198 };
3199 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
3200
3201 static const struct pci_error_handlers hisi_sas_err_handler = {
3202         .error_detected = hisi_sas_error_detected_v3_hw,
3203         .mmio_enabled   = hisi_sas_mmio_enabled_v3_hw,
3204         .slot_reset     = hisi_sas_slot_reset_v3_hw,
3205         .reset_prepare  = hisi_sas_reset_prepare_v3_hw,
3206         .reset_done     = hisi_sas_reset_done_v3_hw,
3207 };
3208
3209 static struct pci_driver sas_v3_pci_driver = {
3210         .name           = DRV_NAME,
3211         .id_table       = sas_v3_pci_table,
3212         .probe          = hisi_sas_v3_probe,
3213         .remove         = hisi_sas_v3_remove,
3214         .suspend        = hisi_sas_v3_suspend,
3215         .resume         = hisi_sas_v3_resume,
3216         .err_handler    = &hisi_sas_err_handler,
3217 };
3218
3219 module_pci_driver(sas_v3_pci_driver);
3220 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
3221
3222 MODULE_LICENSE("GPL");
3223 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3224 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
3225 MODULE_ALIAS("pci:" DRV_NAME);