drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/of_address.h>
  29 #include <linux/reset.h>
  30
  31 #include <linux/usb/ch9.h>
  32 #include <linux/usb/gadget.h>
  33 #include <linux/usb/of.h>
  34 #include <linux/usb/otg.h>
  35
  36 #include "core.h"
  37 #include "gadget.h"
  38 #include "io.h"
  39
  40 #include "debug.h"
  41
  42 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  43
  44 /**
  45  * dwc3_get_dr_mode - Validates and sets dr_mode
  46  * @dwc: pointer to our context structure
  47  */
  48 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  49 {
  50         enum usb_dr_mode mode;
  51         struct device *dev = dwc->dev;
  52         unsigned int hw_mode;
  53
  54         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  55                 dwc->dr_mode = USB_DR_MODE_OTG;
  56
  57         mode = dwc->dr_mode;
  58         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  59
  60         switch (hw_mode) {
  61         case DWC3_GHWPARAMS0_MODE_GADGET:
  62                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  63                         dev_err(dev,
  64                                 "Controller does not support host mode.\n");
  65                         return -EINVAL;
  66                 }
  67                 mode = USB_DR_MODE_PERIPHERAL;
  68                 break;
  69         case DWC3_GHWPARAMS0_MODE_HOST:
  70                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  71                         dev_err(dev,
  72                                 "Controller does not support device mode.\n");
  73                         return -EINVAL;
  74                 }
  75                 mode = USB_DR_MODE_HOST;
  76                 break;
  77         default:
  78                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  79                         mode = USB_DR_MODE_HOST;
  80                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  81                         mode = USB_DR_MODE_PERIPHERAL;
  82
  83                 /*
  84                  * dwc_usb31 does not support OTG mode. If the controller
  85                  * supports DRD but the dr_mode is not specified or set to OTG,
  86                  * then set the mode to peripheral.
  87                  */
  88                 if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96
  97                 dwc->dr_mode = mode;
  98         }
  99
 100         return 0;
 101 }
 102
 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 104 {
 105         u32 reg;
 106
 107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 111
 112         dwc->current_dr_role = mode;
 113 }
 114
 115 static void __dwc3_set_mode(struct work_struct *work)
 116 {
 117         struct dwc3 *dwc = work_to_dwc(work);
 118         unsigned long flags;
 119         int ret;
 120
 121         if (dwc->dr_mode != USB_DR_MODE_OTG)
 122                 return;
 123
 124         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 125                 dwc3_otg_update(dwc, 0);
 126
 127         if (!dwc->desired_dr_role)
 128                 return;
 129
 130         if (dwc->desired_dr_role == dwc->current_dr_role)
 131                 return;
 132
 133         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 134                 return;
 135
 136         switch (dwc->current_dr_role) {
 137         case DWC3_GCTL_PRTCAP_HOST:
 138                 dwc3_host_exit(dwc);
 139                 break;
 140         case DWC3_GCTL_PRTCAP_DEVICE:
 141                 dwc3_gadget_exit(dwc);
 142                 dwc3_event_buffers_cleanup(dwc);
 143                 break;
 144         case DWC3_GCTL_PRTCAP_OTG:
 145                 dwc3_otg_exit(dwc);
 146                 spin_lock_irqsave(&dwc->lock, flags);
 147                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 148                 spin_unlock_irqrestore(&dwc->lock, flags);
 149                 dwc3_otg_update(dwc, 1);
 150                 break;
 151         default:
 152                 break;
 153         }
 154
 155         spin_lock_irqsave(&dwc->lock, flags);
 156
 157         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 158
 159         spin_unlock_irqrestore(&dwc->lock, flags);
 160
 161         switch (dwc->desired_dr_role) {
 162         case DWC3_GCTL_PRTCAP_HOST:
 163                 ret = dwc3_host_init(dwc);
 164                 if (ret) {
 165                         dev_err(dwc->dev, "failed to initialize host\n");
 166                 } else {
 167                         if (dwc->usb2_phy)
 168                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 169                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 171                         phy_calibrate(dwc->usb2_generic_phy);
 172                 }
 173                 break;
 174         case DWC3_GCTL_PRTCAP_DEVICE:
 175                 dwc3_event_buffers_setup(dwc);
 176
 177                 if (dwc->usb2_phy)
 178                         otg_set_vbus(dwc->usb2_phy->otg, false);
 179                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 180                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 181
 182                 ret = dwc3_gadget_init(dwc);
 183                 if (ret)
 184                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 185                 break;
 186         case DWC3_GCTL_PRTCAP_OTG:
 187                 dwc3_otg_init(dwc);
 188                 dwc3_otg_update(dwc, 0);
 189                 break;
 190         default:
 191                 break;
 192         }
 193
 194 }
 195
 196 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 197 {
 198         unsigned long flags;
 199
 200         spin_lock_irqsave(&dwc->lock, flags);
 201         dwc->desired_dr_role = mode;
 202         spin_unlock_irqrestore(&dwc->lock, flags);
 203
 204         queue_work(system_freezable_wq, &dwc->drd_work);
 205 }
 206
 207 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 208 {
 209         struct dwc3             *dwc = dep->dwc;
 210         u32                     reg;
 211
 212         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 213                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 214                         DWC3_GDBGFIFOSPACE_TYPE(type));
 215
 216         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 217
 218         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 219 }
 220
 221 /**
 222  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 223  * @dwc: pointer to our context structure
 224  */
 225 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 226 {
 227         u32             reg;
 228         int             retries = 1000;
 229         int             ret;
 230
 231         usb_phy_init(dwc->usb2_phy);
 232         usb_phy_init(dwc->usb3_phy);
 233         ret = phy_init(dwc->usb2_generic_phy);
 234         if (ret < 0)
 235                 return ret;
 236
 237         ret = phy_init(dwc->usb3_generic_phy);
 238         if (ret < 0) {
 239                 phy_exit(dwc->usb2_generic_phy);
 240                 return ret;
 241         }
 242
 243         /*
 244          * We're resetting only the device side because, if we're in host mode,
 245          * XHCI driver will reset the host block. If dwc3 was configured for
 246          * host-only mode, then we can return early.
 247          */
 248         if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->is_hibernated == true)
 249                 return 0;
 250
 251         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 252                 return 0;
 253
 254         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 255         reg |= DWC3_DCTL_CSFTRST;
 256         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 257
 258         do {
 259                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 260                 if (!(reg & DWC3_DCTL_CSFTRST))
 261                         goto done;
 262
 263                 udelay(1);
 264         } while (--retries);
 265
 266         phy_exit(dwc->usb3_generic_phy);
 267         phy_exit(dwc->usb2_generic_phy);
 268
 269         return -ETIMEDOUT;
 270
 271 done:
 272         /*
 273          * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
 274          * we must wait at least 50ms before accessing the PHY domain
 275          * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
 276          */
 277         if (dwc3_is_usb31(dwc))
 278                 msleep(50);
 279
 280         return 0;
 281 }
 282
 283 static const struct clk_bulk_data dwc3_core_clks[] = {
 284         { .id = "ref" },
 285         { .id = "bus_early" },
 286         { .id = "suspend" },
 287 };
 288
 289 /*
 290  * dwc3_frame_length_adjustment - Adjusts frame length if required
 291  * @dwc3: Pointer to our controller context structure
 292  */
 293 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 294 {
 295         u32 reg, gfladj;
 296         u32 dft;
 297
 298         if (dwc->revision < DWC3_REVISION_250A)
 299                 return;
 300
 301         if (dwc->fladj == 0)
 302                 return;
 303
 304         /* Save the initial DWC3_GFLADJ register value */
 305         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 306         gfladj = reg;
 307
 308         if (dwc->refclk_fladj) {
 309                 if ((reg & DWC3_GFLADJ_REFCLK_FLADJ) !=
 310                                     (dwc->fladj & DWC3_GFLADJ_REFCLK_FLADJ)) {
 311                         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ;
 312                         reg |= (dwc->fladj & DWC3_GFLADJ_REFCLK_FLADJ);
 313                 }
 314         }
 315
 316         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 317         if (dft != dwc->fladj) {
 318                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 319                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 320         }
 321
 322         /* Update DWC3_GFLADJ if there is any change from initial value */
 323         if (reg != gfladj)
 324                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 325 }
 326
 327 /**
 328  * dwc3_free_one_event_buffer - Frees one event buffer
 329  * @dwc: Pointer to our controller context structure
 330  * @evt: Pointer to event buffer to be freed
 331  */
 332 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 333                 struct dwc3_event_buffer *evt)
 334 {
 335         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 336 }
 337
 338 /**
 339  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 340  * @dwc: Pointer to our controller context structure
 341  * @length: size of the event buffer
 342  *
 343  * Returns a pointer to the allocated event buffer structure on success
 344  * otherwise ERR_PTR(errno).
 345  */
 346 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 347                 unsigned length)
 348 {
 349         struct dwc3_event_buffer        *evt;
 350
 351         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 352         if (!evt)
 353                 return ERR_PTR(-ENOMEM);
 354
 355         evt->dwc        = dwc;
 356         evt->length     = length;
 357         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 358         if (!evt->cache)
 359                 return ERR_PTR(-ENOMEM);
 360
 361         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 362                         &evt->dma, GFP_KERNEL);
 363         if (!evt->buf)
 364                 return ERR_PTR(-ENOMEM);
 365
 366         return evt;
 367 }
 368
 369 /**
 370  * dwc3_free_event_buffers - frees all allocated event buffers
 371  * @dwc: Pointer to our controller context structure
 372  */
 373 void dwc3_free_event_buffers(struct dwc3 *dwc)
 374 {
 375         struct dwc3_event_buffer        *evt;
 376
 377         evt = dwc->ev_buf;
 378         if (evt)
 379                 dwc3_free_one_event_buffer(dwc, evt);
 380 }
 381
 382 /**
 383  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 384  * @dwc: pointer to our controller context structure
 385  * @length: size of event buffer
 386  *
 387  * Returns 0 on success otherwise negative errno. In the error case, dwc
 388  * may contain some buffers allocated but not all which were requested.
 389  */
 390 int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 391 {
 392         struct dwc3_event_buffer *evt;
 393
 394         evt = dwc3_alloc_one_event_buffer(dwc, length);
 395         if (IS_ERR(evt)) {
 396                 dev_err(dwc->dev, "can't allocate event buffer\n");
 397                 return PTR_ERR(evt);
 398         }
 399         dwc->ev_buf = evt;
 400
 401         return 0;
 402 }
 403
 404 /**
 405  * dwc3_event_buffers_setup - setup our allocated event buffers
 406  * @dwc: pointer to our controller context structure
 407  *
 408  * Returns 0 on success otherwise negative errno.
 409  */
 410 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 411 {
 412         struct dwc3_event_buffer        *evt;
 413
 414         if (dwc->dr_mode == USB_DR_MODE_HOST)
 415                 return 0;
 416
 417         evt = dwc->ev_buf;
 418         evt->lpos = 0;
 419         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 420                         lower_32_bits(evt->dma));
 421         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 422                         upper_32_bits(evt->dma));
 423         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 424                         DWC3_GEVNTSIZ_SIZE(evt->length));
 425         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 426
 427         return 0;
 428 }
 429
 430 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 431 {
 432         struct dwc3_event_buffer        *evt;
 433
 434         evt = dwc->ev_buf;
 435
 436         evt->lpos = 0;
 437
 438         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 439         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 440         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 441                         | DWC3_GEVNTSIZ_SIZE(0));
 442         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 443 }
 444
 445 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 446 {
 447         u32 size;
 448
 449         if (dwc->dr_mode == USB_DR_MODE_HOST)
 450                 return 0;
 451
 452         if (!dwc->has_hibernation)
 453                 return 0;
 454
 455         if (!dwc->nr_scratch)
 456                 return 0;
 457
 458         /* Allocate only if scratchbuf is NULL */
 459         if (dwc->scratchbuf)
 460                 return 0;
 461
 462         size = dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE;
 463
 464         dwc->scratchbuf = kzalloc(size, GFP_KERNEL);
 465
 466         if (!dwc->scratchbuf)
 467                 return -ENOMEM;
 468
 469         dwc->scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, size,
 470                                            DMA_BIDIRECTIONAL);
 471         if (dma_mapping_error(dwc->dev, dwc->scratch_addr)) {
 472                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 473                 return -EFAULT;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 480 {
 481         u32 param;
 482         int ret;
 483
 484         if (dwc->dr_mode == USB_DR_MODE_HOST)
 485                 return 0;
 486
 487         if (!dwc->has_hibernation)
 488                 return 0;
 489
 490         if (!dwc->nr_scratch)
 491                 return 0;
 492
 493          /* should never fall here */
 494         if (WARN_ON(!dwc->scratchbuf))
 495                 return 0;
 496
 497         param = lower_32_bits(dwc->scratch_addr);
 498
 499         ret = dwc3_send_gadget_generic_command(dwc,
 500                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 501         if (ret < 0)
 502                 goto err1;
 503
 504         param = upper_32_bits(dwc->scratch_addr);
 505
 506         ret = dwc3_send_gadget_generic_command(dwc,
 507                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 508         if (ret < 0)
 509                 goto err1;
 510
 511         return 0;
 512
 513 err1:
 514         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 515                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 516
 517         return ret;
 518 }
 519
 520 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 521 {
 522         if (!dwc->has_hibernation)
 523                 return;
 524
 525         if (!dwc->nr_scratch)
 526                 return;
 527
 528          /* should never fall here */
 529         if (WARN_ON(!dwc->scratchbuf))
 530                 return;
 531
 532         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 533                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 534         kfree(dwc->scratchbuf);
 535 }
 536
 537 static void dwc3_core_num_eps(struct dwc3 *dwc)
 538 {
 539         struct dwc3_hwparams    *parms = &dwc->hwparams;
 540
 541         dwc->num_eps = DWC3_NUM_EPS(parms);
 542 }
 543
 544 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 545 {
 546         struct dwc3_hwparams    *parms = &dwc->hwparams;
 547
 548         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 549         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 550         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 551         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 552         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 553         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 554         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 555         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 556         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 557 }
 558
 559 static int dwc3_config_soc_bus(struct dwc3 *dwc)
 560 {
 561         int ret;
 562
 563         /*
 564          * Check if CCI is enabled for USB. Returns true
 565          * if the node has property 'dma-coherent'. Otherwise
 566          * returns false.
 567          */
 568         if (of_dma_is_coherent(dwc->dev->of_node)) {
 569                 u32 reg;
 570
 571                 reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 572                 reg |= DWC3_GSBUSCFG0_DATRDREQINFO |
 573                         DWC3_GSBUSCFG0_DESRDREQINFO |
 574                         DWC3_GSBUSCFG0_DATWRREQINFO |
 575                         DWC3_GSBUSCFG0_DESWRREQINFO;
 576                 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
 577         }
 578
 579         /*
 580          * This routes the usb dma traffic to go through CCI path instead
 581          * of reaching DDR directly. This traffic routing is needed to
 582          * to make SMMU and CCI work with USB dma.
 583          */
 584         if (of_dma_is_coherent(dwc->dev->of_node) || dwc->dev->iommu_group) {
 585                 ret = dwc3_enable_hw_coherency(dwc->dev);
 586                 if (ret)
 587                         return ret;
 588         }
 589
 590         /* Send struct dwc3 to dwc3-of-simple for configuring VBUS
 591          * during suspend/resume
 592          */
 593         dwc3_set_simple_data(dwc);
 594
 595         return 0;
 596 }
 597
 598 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 599 {
 600         int intf;
 601         int ret = 0;
 602
 603         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 604
 605         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 606             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 607              dwc->hsphy_interface &&
 608              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 609                 ret = dwc3_ulpi_init(dwc);
 610
 611         return ret;
 612 }
 613
 614 /**
 615  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 616  * @dwc: Pointer to our controller context structure
 617  *
 618  * Returns 0 on success. The USB PHY interfaces are configured but not
 619  * initialized. The PHY interfaces and the PHYs get initialized together with
 620  * the core in dwc3_core_init.
 621  */
 622 static int dwc3_phy_setup(struct dwc3 *dwc)
 623 {
 624         u32 reg;
 625
 626         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 627
 628         /*
 629          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 630          * PHYs. Also, this bit is not supposed to be used in normal operation.
 631          */
 632         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 633
 634         /*
 635          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 636          * to '0' during coreConsultant configuration. So default value
 637          * will be '0' when the core is reset. Application needs to set it
 638          * to '1' after the core initialization is completed.
 639          */
 640         if (dwc->revision > DWC3_REVISION_194A)
 641                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 642
 643         if (dwc->u2ss_inp3_quirk)
 644                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 645
 646         if (dwc->dis_rxdet_inp3_quirk)
 647                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 648
 649         if (dwc->req_p1p2p3_quirk)
 650                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 651
 652         if (dwc->del_p1p2p3_quirk)
 653                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 654
 655         if (dwc->del_phy_power_chg_quirk)
 656                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 657
 658         if (dwc->lfps_filter_quirk)
 659                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 660
 661         if (dwc->rx_detect_poll_quirk)
 662                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 663
 664         if (dwc->tx_de_emphasis_quirk)
 665                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 666
 667         if (dwc->dis_u3_susphy_quirk)
 668                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 669
 670         if (dwc->dis_del_phy_power_chg_quirk)
 671                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 672
 673         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 674
 675         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 676
 677         /* Select the HS PHY interface */
 678         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 679         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 680                 if (dwc->hsphy_interface &&
 681                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 682                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 683                         break;
 684                 } else if (dwc->hsphy_interface &&
 685                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 686                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 687                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 688                 } else {
 689                         /* Relying on default value. */
 690                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 691                                 break;
 692                 }
 693                 /* FALLTHROUGH */
 694         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 695                 /* FALLTHROUGH */
 696         default:
 697                 break;
 698         }
 699
 700         switch (dwc->hsphy_mode) {
 701         case USBPHY_INTERFACE_MODE_UTMI:
 702                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 703                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 704                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 705                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 706                 break;
 707         case USBPHY_INTERFACE_MODE_UTMIW:
 708                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 709                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 710                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 711                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 712                 break;
 713         default:
 714                 break;
 715         }
 716
 717         /*
 718          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 719          * '0' during coreConsultant configuration. So default value will
 720          * be '0' when the core is reset. Application needs to set it to
 721          * '1' after the core initialization is completed.
 722          */
 723         if (dwc->revision > DWC3_REVISION_194A)
 724                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 725
 726         if (dwc->dis_u2_susphy_quirk)
 727                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 728
 729         if (dwc->dis_enblslpm_quirk)
 730                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 731
 732         if (dwc->dis_u2_freeclk_exists_quirk)
 733                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 734
 735         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 736
 737         return 0;
 738 }
 739
 740 static void dwc3_core_exit(struct dwc3 *dwc)
 741 {
 742         usb_phy_shutdown(dwc->usb2_phy);
 743         usb_phy_shutdown(dwc->usb3_phy);
 744         phy_exit(dwc->usb2_generic_phy);
 745         phy_exit(dwc->usb3_generic_phy);
 746
 747         usb_phy_set_suspend(dwc->usb2_phy, 1);
 748         usb_phy_set_suspend(dwc->usb3_phy, 1);
 749         phy_power_off(dwc->usb2_generic_phy);
 750         phy_power_off(dwc->usb3_generic_phy);
 751         clk_bulk_disable(dwc->num_clks, dwc->clks);
 752         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
 753         reset_control_assert(dwc->reset);
 754 }
 755
 756 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 757 {
 758         u32 reg;
 759
 760         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 761
 762         /* This should read as U3 followed by revision number */
 763         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 764                 /* Detected DWC_usb3 IP */
 765                 dwc->revision = reg;
 766         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 767                 /* Detected DWC_usb31 IP */
 768                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 769                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 770         } else {
 771                 return false;
 772         }
 773
 774         return true;
 775 }
 776
 777 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 778 {
 779         u32 hwparams4 = dwc->hwparams.hwparams4;
 780         u32 reg;
 781
 782         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 783         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 784
 785         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 786         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 787                 /**
 788                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 789                  * issue which would cause xHCI compliance tests to fail.
 790                  *
 791                  * Because of that we cannot enable clock gating on such
 792                  * configurations.
 793                  *
 794                  * Refers to:
 795                  *
 796                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 797                  * SOF/ITP Mode Used
 798                  */
 799                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 800                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 801                                 (dwc->revision >= DWC3_REVISION_210A &&
 802                                 dwc->revision <= DWC3_REVISION_250A))
 803                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 804                 else
 805                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 806                 break;
 807         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 808                 if (!device_property_read_bool(dwc->dev,
 809                                                "snps,enable-hibernation")) {
 810                         dev_dbg(dwc->dev, "Hibernation not enabled\n");
 811                 } else {
 812                         /* enable hibernation here */
 813                         dwc->nr_scratch =
 814                                 DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 815                         dwc->has_hibernation = 1;
 816                 }
 817
 818                 /*
 819                  * REVISIT Enabling this bit so that host-mode hibernation
 820                  * will work. Device-mode hibernation is not yet implemented.
 821                  */
 822                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 823                 break;
 824         default:
 825                 /* nothing */
 826                 break;
 827         }
 828
 829         /* check if current dwc3 is on simulation board */
 830         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 831                 dev_info(dwc->dev, "Running with FPGA optmizations\n");
 832                 dwc->is_fpga = true;
 833         }
 834
 835         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 836                         "disable_scramble cannot be used on non-FPGA builds\n");
 837
 838         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 839                 reg |= DWC3_GCTL_DISSCRAMBLE;
 840         else
 841                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 842
 843         if (dwc->u2exit_lfps_quirk)
 844                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 845
 846         /*
 847          * WORKAROUND: DWC3 revisions <1.90a have a bug
 848          * where the device can fail to connect at SuperSpeed
 849          * and falls back to high-speed mode which causes
 850          * the device to enter a Connect/Disconnect loop
 851          */
 852         if (dwc->revision < DWC3_REVISION_190A)
 853                 reg |= DWC3_GCTL_U2RSTECN;
 854
 855         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 856 }
 857
 858 static int dwc3_core_get_phy(struct dwc3 *dwc);
 859 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 860
 861 /* set global incr burst type configuration registers */
 862 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 863 {
 864         struct device *dev = dwc->dev;
 865         /* incrx_mode : for INCR burst type. */
 866         bool incrx_mode;
 867         /* incrx_size : for size of INCRX burst. */
 868         u32 incrx_size;
 869         u32 *vals;
 870         u32 cfg;
 871         int ntype;
 872         int ret;
 873         int i;
 874
 875         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 876
 877         /*
 878          * Handle property "snps,incr-burst-type-adjustment".
 879          * Get the number of value from this property:
 880          * result <= 0, means this property is not supported.
 881          * result = 1, means INCRx burst mode supported.
 882          * result > 1, means undefined length burst mode supported.
 883          */
 884         ntype = device_property_read_u32_array(dev,
 885                         "snps,incr-burst-type-adjustment", NULL, 0);
 886         if (ntype <= 0)
 887                 return;
 888
 889         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 890         if (!vals) {
 891                 dev_err(dev, "Error to get memory\n");
 892                 return;
 893         }
 894
 895         /* Get INCR burst type, and parse it */
 896         ret = device_property_read_u32_array(dev,
 897                         "snps,incr-burst-type-adjustment", vals, ntype);
 898         if (ret) {
 899                 dev_err(dev, "Error to get property\n");
 900                 return;
 901         }
 902
 903         incrx_size = *vals;
 904
 905         if (ntype > 1) {
 906                 /* INCRX (undefined length) burst mode */
 907                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 908                 for (i = 1; i < ntype; i++) {
 909                         if (vals[i] > incrx_size)
 910                                 incrx_size = vals[i];
 911                 }
 912         } else {
 913                 /* INCRX burst mode */
 914                 incrx_mode = INCRX_BURST_MODE;
 915         }
 916
 917         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 918         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 919         if (incrx_mode)
 920                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 921         switch (incrx_size) {
 922         case 256:
 923                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 924                 break;
 925         case 128:
 926                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 927                 break;
 928         case 64:
 929                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 930                 break;
 931         case 32:
 932                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 933                 break;
 934         case 16:
 935                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 936                 break;
 937         case 8:
 938                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 939                 break;
 940         case 4:
 941                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 942                 break;
 943         case 1:
 944                 break;
 945         default:
 946                 dev_err(dev, "Invalid property\n");
 947                 break;
 948         }
 949
 950         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 951 }
 952
 953 /**
 954  * dwc3_core_init - Low-level initialization of DWC3 Core
 955  * @dwc: Pointer to our controller context structure
 956  *
 957  * Returns 0 on success otherwise negative errno.
 958  */
 959 int dwc3_core_init(struct dwc3 *dwc)
 960 {
 961         u32                     reg;
 962         int                     ret;
 963
 964         if (!dwc3_core_is_valid(dwc)) {
 965                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 966                 ret = -ENODEV;
 967                 goto err0;
 968         }
 969
 970         /*
 971          * Write Linux Version Code to our GUID register so it's easy to figure
 972          * out which kernel version a bug was found.
 973          */
 974         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 975
 976         /* Handle USB2.0-only core configuration */
 977         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 978                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 979                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 980                         dwc->maximum_speed = USB_SPEED_HIGH;
 981         }
 982
 983         ret = dwc3_phy_setup(dwc);
 984         if (ret)
 985                 goto err0;
 986
 987         if (!dwc->ulpi_ready) {
 988                 ret = dwc3_core_ulpi_init(dwc);
 989                 if (ret)
 990                         goto err0;
 991                 dwc->ulpi_ready = true;
 992         }
 993
 994         if (!dwc->phys_ready) {
 995                 ret = dwc3_core_get_phy(dwc);
 996                 if (ret)
 997                         goto err0a;
 998                 dwc->phys_ready = true;
 999         }
1000
1001         ret = dwc3_core_soft_reset(dwc);
1002         if (ret)
1003                 goto err0a;
1004
1005         dwc3_core_setup_global_control(dwc);
1006         dwc3_core_num_eps(dwc);
1007
1008         if (dwc->scratchbuf == NULL) {
1009                 ret = dwc3_alloc_scratch_buffers(dwc);
1010                 if (ret) {
1011                         dev_err(dwc->dev,
1012                                 "Not enough memory for scratch buffers\n");
1013                         goto err1;
1014                 }
1015         }
1016
1017         ret = dwc3_setup_scratch_buffers(dwc);
1018         if (ret) {
1019                 dev_err(dwc->dev, "Failed to setup scratch buffers: %d\n", ret);
1020                 goto err1;
1021         }
1022
1023         /* Adjust Frame Length */
1024         dwc3_frame_length_adjustment(dwc);
1025
1026         dwc3_set_incr_burst_type(dwc);
1027
1028         ret = dwc3_config_soc_bus(dwc);
1029         if (ret)
1030                 goto err1;
1031
1032         usb_phy_set_suspend(dwc->usb2_phy, 0);
1033         usb_phy_set_suspend(dwc->usb3_phy, 0);
1034         ret = phy_power_on(dwc->usb2_generic_phy);
1035         if (ret < 0)
1036                 goto err2;
1037
1038         ret = phy_power_on(dwc->usb3_generic_phy);
1039         if (ret < 0)
1040                 goto err3;
1041
1042         ret = dwc3_event_buffers_setup(dwc);
1043         if (ret) {
1044                 dev_err(dwc->dev, "failed to setup event buffers\n");
1045                 goto err4;
1046         }
1047
1048         switch (dwc->dr_mode) {
1049         case USB_DR_MODE_PERIPHERAL:
1050                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1051                 break;
1052         case USB_DR_MODE_HOST:
1053                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1054                 break;
1055         case USB_DR_MODE_OTG:
1056                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG);
1057                 break;
1058         default:
1059                 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
1060                 break;
1061         }
1062
1063         /*
1064          * ENDXFER polling is available on version 3.10a and later of
1065          * the DWC_usb3 controller. It is NOT available in the
1066          * DWC_usb31 controller.
1067          */
1068         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
1069                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1070                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1071                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1072         }
1073
1074         /* When configured in HOST mode, after issuing U3/L2 exit controller
1075          * fails to send proper CRC checksum in CRC5 feild. Because of this
1076          * behaviour Transaction Error is generated, resulting in reset and
1077          * re-enumeration of usb device attached. Enabling bit 10 of GUCTL1
1078          * will correct this problem
1079          */
1080         if (dwc->enable_guctl1_resume_quirk) {
1081                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1082                 reg |= DWC3_GUCTL1_RESUME_QUIRK;
1083                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1084         }
1085
1086         /* SNPS controller when configureed in HOST mode maintains Inter Packet
1087          * Delay (IPD) of ~380ns which works with most of the super-speed hubs
1088          * except VIA-LAB hubs. When IPD is ~380ns HOST controller fails to
1089          * enumerate FS/LS devices when connected behind VIA-LAB hubs.
1090          * Enabling bit 9 of GUCTL1 enables the workaround in HW to reduce the
1091          * ULPI clock latency by 1 cycle, thus reducing the IPD (~360ns) and
1092          * making controller enumerate FS/LS devices connected behind VIA-LAB.
1093          */
1094         if (dwc->enable_guctl1_ipd_quirk) {
1095                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1096                 reg |= DWC3_GUCTL1_IPD_QUIRK;
1097                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1098         }
1099
1100         if (dwc->revision >= DWC3_REVISION_250A) {
1101                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1102
1103                 /*
1104                  * Enable hardware control of sending remote wakeup
1105                  * in HS when the device is in the L1 state.
1106                  */
1107                 if (dwc->revision >= DWC3_REVISION_290A)
1108                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1109
1110                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1111                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1112
1113                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1114         }
1115
1116         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1117             dwc->dr_mode == USB_DR_MODE_OTG) {
1118                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1119
1120                 /*
1121                  * Enable Auto retry Feature to make the controller operating in
1122                  * Host mode on seeing transaction errors(CRC errors or internal
1123                  * overrun scenerios) on IN transfers to reply to the device
1124                  * with a non-terminating retry ACK (i.e, an ACK transcation
1125                  * packet with Retry=1 & Nump != 0)
1126                  */
1127                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1128
1129                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1130         }
1131
1132         /*
1133          * Must config both number of packets and max burst settings to enable
1134          * RX and/or TX threshold.
1135          */
1136         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1137                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1138                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1139                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1140                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1141
1142                 if (rx_thr_num && rx_maxburst) {
1143                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1144                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1145
1146                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1147                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1148
1149                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1150                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1151
1152                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1153                 }
1154
1155                 if (tx_thr_num && tx_maxburst) {
1156                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1157                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1158
1159                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1160                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1161
1162                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1163                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1164
1165                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1166                 }
1167         }
1168
1169         return 0;
1170
1171 err4:
1172         phy_power_off(dwc->usb3_generic_phy);
1173
1174 err3:
1175         phy_power_off(dwc->usb2_generic_phy);
1176
1177 err2:
1178         usb_phy_set_suspend(dwc->usb2_phy, 1);
1179         usb_phy_set_suspend(dwc->usb3_phy, 1);
1180
1181 err1:
1182         usb_phy_shutdown(dwc->usb2_phy);
1183         usb_phy_shutdown(dwc->usb3_phy);
1184         phy_exit(dwc->usb2_generic_phy);
1185         phy_exit(dwc->usb3_generic_phy);
1186
1187 err0a:
1188         dwc3_ulpi_exit(dwc);
1189
1190 err0:
1191         return ret;
1192 }
1193
1194 static int dwc3_core_get_phy(struct dwc3 *dwc)
1195 {
1196         struct device           *dev = dwc->dev;
1197         struct device_node      *node = dev->of_node;
1198         int ret;
1199
1200         if (node) {
1201                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1202                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1203         } else {
1204                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1205                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1206         }
1207
1208         if (IS_ERR(dwc->usb2_phy)) {
1209                 ret = PTR_ERR(dwc->usb2_phy);
1210                 if (ret == -ENXIO || ret == -ENODEV) {
1211                         dwc->usb2_phy = NULL;
1212                 } else if (ret == -EPROBE_DEFER) {
1213                         return ret;
1214                 } else {
1215                         dev_err(dev, "no usb2 phy configured\n");
1216                         return ret;
1217                 }
1218         }
1219
1220         if (IS_ERR(dwc->usb3_phy)) {
1221                 ret = PTR_ERR(dwc->usb3_phy);
1222                 if (ret == -ENXIO || ret == -ENODEV) {
1223                         dwc->usb3_phy = NULL;
1224                 } else if (ret == -EPROBE_DEFER) {
1225                         return ret;
1226                 } else {
1227                         dev_err(dev, "no usb3 phy configured\n");
1228                         return ret;
1229                 }
1230         }
1231
1232         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1233         if (IS_ERR(dwc->usb2_generic_phy)) {
1234                 ret = PTR_ERR(dwc->usb2_generic_phy);
1235                 if (ret == -ENOSYS || ret == -ENODEV) {
1236                         dwc->usb2_generic_phy = NULL;
1237                 } else if (ret == -EPROBE_DEFER) {
1238                         return ret;
1239                 } else {
1240                         dev_err(dev, "no usb2 phy configured\n");
1241                         return ret;
1242                 }
1243         }
1244
1245         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1246         if (IS_ERR(dwc->usb3_generic_phy)) {
1247                 ret = PTR_ERR(dwc->usb3_generic_phy);
1248                 if (ret == -ENOSYS || ret == -ENODEV) {
1249                         dwc->usb3_generic_phy = NULL;
1250                 } else if (ret == -EPROBE_DEFER) {
1251                         return ret;
1252                 } else {
1253                         dev_err(dev, "no usb3 phy configured\n");
1254                         return ret;
1255                 }
1256         }
1257
1258         return 0;
1259 }
1260
1261 static int dwc3_core_init_mode(struct dwc3 *dwc)
1262 {
1263         struct device *dev = dwc->dev;
1264         int ret;
1265
1266         switch (dwc->dr_mode) {
1267         case USB_DR_MODE_PERIPHERAL:
1268                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1269
1270                 if (dwc->usb2_phy)
1271                         otg_set_vbus(dwc->usb2_phy->otg, false);
1272                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1273                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1274
1275                 ret = dwc3_gadget_init(dwc);
1276                 if (ret) {
1277                         if (ret != -EPROBE_DEFER)
1278                                 dev_err(dev, "failed to initialize gadget\n");
1279                         return ret;
1280                 }
1281                 break;
1282         case USB_DR_MODE_HOST:
1283                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1284
1285                 if (dwc->usb2_phy)
1286                         otg_set_vbus(dwc->usb2_phy->otg, true);
1287                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1288                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1289
1290                 ret = dwc3_host_init(dwc);
1291                 if (ret) {
1292                         if (ret != -EPROBE_DEFER)
1293                                 dev_err(dev, "failed to initialize host\n");
1294                         return ret;
1295                 }
1296                 phy_calibrate(dwc->usb2_generic_phy);
1297                 break;
1298         case USB_DR_MODE_OTG:
1299                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1300                 ret = dwc3_drd_init(dwc);
1301                 if (ret) {
1302                         if (ret != -EPROBE_DEFER)
1303                                 dev_err(dev, "failed to initialize dual-role\n");
1304                         return ret;
1305                 }
1306
1307 #if IS_ENABLED(CONFIG_USB_DWC3_OTG)
1308                 dwc->current_dr_role = 0;
1309                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
1310 #endif
1311                 break;
1312         default:
1313                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1314                 return -EINVAL;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1321 {
1322         switch (dwc->dr_mode) {
1323         case USB_DR_MODE_PERIPHERAL:
1324                 dwc3_gadget_exit(dwc);
1325                 break;
1326         case USB_DR_MODE_HOST:
1327                 dwc3_host_exit(dwc);
1328                 break;
1329         case USB_DR_MODE_OTG:
1330                 dwc3_drd_exit(dwc);
1331                 break;
1332         default:
1333                 /* do nothing */
1334                 break;
1335         }
1336 }
1337
1338 static void dwc3_get_properties(struct dwc3 *dwc)
1339 {
1340         struct device           *dev = dwc->dev;
1341         u8                      lpm_nyet_threshold;
1342         u8                      tx_de_emphasis;
1343         u8                      hird_threshold;
1344         u8                      rx_thr_num_pkt_prd;
1345         u8                      rx_max_burst_prd;
1346         u8                      tx_thr_num_pkt_prd;
1347         u8                      tx_max_burst_prd;
1348
1349         /* default to highest possible threshold */
1350         lpm_nyet_threshold = 0xff;
1351
1352         /* default to -3.5dB de-emphasis */
1353         tx_de_emphasis = 1;
1354
1355         /*
1356          * default to assert utmi_sleep_n and use maximum allowed HIRD
1357          * threshold value of 0b1100
1358          */
1359         hird_threshold = 12;
1360
1361         dwc->maximum_speed = usb_get_maximum_speed(dev);
1362         dwc->dr_mode = usb_get_dr_mode(dev);
1363         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1364
1365         dwc->sysdev_is_parent = device_property_read_bool(dev,
1366                                 "linux,sysdev_is_parent");
1367         if (dwc->sysdev_is_parent)
1368                 dwc->sysdev = dwc->dev->parent;
1369         else
1370                 dwc->sysdev = dwc->dev;
1371
1372         dwc->has_lpm_erratum = device_property_read_bool(dev,
1373                                 "snps,has-lpm-erratum");
1374         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1375                                 &lpm_nyet_threshold);
1376         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1377                                 "snps,is-utmi-l1-suspend");
1378         device_property_read_u8(dev, "snps,hird-threshold",
1379                                 &hird_threshold);
1380         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1381                                 "snps,usb3_lpm_capable");
1382         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1383                                 &rx_thr_num_pkt_prd);
1384         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1385                                 &rx_max_burst_prd);
1386         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1387                                 &tx_thr_num_pkt_prd);
1388         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1389                                 &tx_max_burst_prd);
1390
1391         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1392                                 "snps,disable_scramble_quirk");
1393         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1394                                 "snps,u2exit_lfps_quirk");
1395         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1396                                 "snps,u2ss_inp3_quirk");
1397         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1398                                 "snps,req_p1p2p3_quirk");
1399         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1400                                 "snps,del_p1p2p3_quirk");
1401         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1402                                 "snps,del_phy_power_chg_quirk");
1403         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1404                                 "snps,lfps_filter_quirk");
1405         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1406                                 "snps,rx_detect_poll_quirk");
1407         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1408                                 "snps,dis_u3_susphy_quirk");
1409         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1410                                 "snps,dis_u2_susphy_quirk");
1411         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1412                                 "snps,dis_enblslpm_quirk");
1413         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1414                                 "snps,dis_rxdet_inp3_quirk");
1415         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1416                                 "snps,dis-u2-freeclk-exists-quirk");
1417         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1418                                 "snps,dis-del-phy-power-chg-quirk");
1419         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1420                                 "snps,dis-tx-ipgap-linecheck-quirk");
1421
1422         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1423                                 "snps,tx_de_emphasis_quirk");
1424         device_property_read_u8(dev, "snps,tx_de_emphasis",
1425                                 &tx_de_emphasis);
1426         device_property_read_string(dev, "snps,hsphy_interface",
1427                                     &dwc->hsphy_interface);
1428         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1429                                  &dwc->fladj);
1430
1431         dwc->refclk_fladj = device_property_read_bool(dev,
1432                                                       "snps,refclk_fladj");
1433         dwc->enable_guctl1_resume_quirk = device_property_read_bool(dev,
1434                                 "snps,enable_guctl1_resume_quirk");
1435         dwc->enable_guctl1_ipd_quirk = device_property_read_bool(dev,
1436                                 "snps,enable_guctl1_ipd_quirk");
1437         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1438                                 "snps,dis_metastability_quirk");
1439
1440         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1441         dwc->tx_de_emphasis = tx_de_emphasis;
1442
1443         dwc->hird_threshold = hird_threshold
1444                 | (dwc->is_utmi_l1_suspend << 4);
1445
1446         /* Check if extra quirks to be added */
1447         dwc3_simple_check_quirks(dwc);
1448
1449         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1450         dwc->rx_max_burst_prd = rx_max_burst_prd;
1451
1452         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1453         dwc->tx_max_burst_prd = tx_max_burst_prd;
1454
1455         dwc->imod_interval = 0;
1456 }
1457
1458 /* check whether the core supports IMOD */
1459 bool dwc3_has_imod(struct dwc3 *dwc)
1460 {
1461         return ((dwc3_is_usb3(dwc) &&
1462                  dwc->revision >= DWC3_REVISION_300A) ||
1463                 (dwc3_is_usb31(dwc) &&
1464                  dwc->revision >= DWC3_USB31_REVISION_120A));
1465 }
1466
1467 static void dwc3_check_params(struct dwc3 *dwc)
1468 {
1469         struct device *dev = dwc->dev;
1470
1471         /* Check for proper value of imod_interval */
1472         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1473                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1474                 dwc->imod_interval = 0;
1475         }
1476
1477         /*
1478          * Workaround for STAR 9000961433 which affects only version
1479          * 3.00a of the DWC_usb3 core. This prevents the controller
1480          * interrupt from being masked while handling events. IMOD
1481          * allows us to work around this issue. Enable it for the
1482          * affected version.
1483          */
1484         if (!dwc->imod_interval &&
1485             (dwc->revision == DWC3_REVISION_300A))
1486                 dwc->imod_interval = 1;
1487
1488         /* Check the maximum_speed parameter */
1489         switch (dwc->maximum_speed) {
1490         case USB_SPEED_LOW:
1491         case USB_SPEED_FULL:
1492         case USB_SPEED_HIGH:
1493         case USB_SPEED_SUPER:
1494         case USB_SPEED_SUPER_PLUS:
1495                 break;
1496         default:
1497                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1498                         dwc->maximum_speed);
1499                 /* fall through */
1500         case USB_SPEED_UNKNOWN:
1501                 /* default to superspeed */
1502                 dwc->maximum_speed = USB_SPEED_SUPER;
1503
1504                 /*
1505                  * default to superspeed plus if we are capable.
1506                  */
1507                 if (dwc3_is_usb31(dwc) &&
1508                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1509                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1510                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1511
1512                 break;
1513         }
1514 }
1515
1516 static int dwc3_probe(struct platform_device *pdev)
1517 {
1518         struct device           *dev = &pdev->dev;
1519         struct resource         *res, dwc_res;
1520         struct dwc3             *dwc;
1521         int                     ret;
1522         u32                     mdwidth;
1523         void __iomem            *regs;
1524
1525         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1526         if (!dwc)
1527                 return -ENOMEM;
1528
1529         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1530                                  GFP_KERNEL);
1531         if (!dwc->clks)
1532                 return -ENOMEM;
1533
1534         dwc->dev = dev;
1535
1536         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537         if (!res) {
1538                 dev_err(dev, "missing memory resource\n");
1539                 return -ENODEV;
1540         }
1541
1542         dwc->xhci_resources[0].start = res->start;
1543         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1544                                         DWC3_XHCI_REGS_END;
1545         dwc->xhci_resources[0].flags = res->flags;
1546         dwc->xhci_resources[0].name = res->name;
1547
1548         /*
1549          * Request memory region but exclude xHCI regs,
1550          * since it will be requested by the xhci-plat driver.
1551          */
1552         dwc_res = *res;
1553         dwc_res.start += DWC3_GLOBALS_REGS_START;
1554
1555         regs = devm_ioremap_resource(dev, &dwc_res);
1556         if (IS_ERR(regs))
1557                 return PTR_ERR(regs);
1558
1559         dwc->regs       = regs;
1560         dwc->regs_size  = resource_size(&dwc_res);
1561
1562         dwc3_get_properties(dwc);
1563
1564         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1565         if (IS_ERR(dwc->reset))
1566                 return PTR_ERR(dwc->reset);
1567
1568         if (dev->of_node) {
1569                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1570
1571                 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1572                 if (ret == -EPROBE_DEFER)
1573                         return ret;
1574                 /*
1575                  * Clocks are optional, but new DT platforms should support all
1576                  * clocks as required by the DT-binding.
1577                  */
1578                 if (ret)
1579                         dwc->num_clks = 0;
1580         }
1581
1582         ret = reset_control_deassert(dwc->reset);
1583         if (ret)
1584                 goto put_clks;
1585
1586         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1587         if (ret)
1588                 goto assert_reset;
1589
1590         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1591         if (ret)
1592                 goto unprepare_clks;
1593
1594         platform_set_drvdata(pdev, dwc);
1595         dwc3_cache_hwparams(dwc);
1596
1597         spin_lock_init(&dwc->lock);
1598
1599         /* Set dma coherent mask to DMA BUS data width */
1600         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1601         dev_dbg(dev, "Enabling %d-bit DMA addresses.\n", mdwidth);
1602         dma_set_coherent_mask(dev, DMA_BIT_MASK(mdwidth));
1603
1604         pm_runtime_set_active(dev);
1605         pm_runtime_use_autosuspend(dev);
1606         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1607         pm_runtime_enable(dev);
1608         ret = pm_runtime_get_sync(dev);
1609         if (ret < 0)
1610                 goto err1;
1611
1612         pm_runtime_forbid(dev);
1613
1614         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1615         if (ret) {
1616                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1617                 ret = -ENOMEM;
1618                 goto err2;
1619         }
1620
1621         ret = dwc3_get_dr_mode(dwc);
1622         if (ret)
1623                 goto err3;
1624
1625         ret = dwc3_core_init(dwc);
1626         if (ret) {
1627                 dev_err(dev, "failed to initialize core\n");
1628                 goto err4;
1629         }
1630
1631         dwc3_check_params(dwc);
1632
1633         ret = dwc3_core_init_mode(dwc);
1634         if (ret)
1635                 goto err5;
1636
1637         dwc3_debugfs_init(dwc);
1638         pm_runtime_put(dev);
1639
1640         return 0;
1641
1642 err5:
1643         dwc3_event_buffers_cleanup(dwc);
1644
1645 err4:
1646         dwc3_free_scratch_buffers(dwc);
1647
1648 err3:
1649         dwc3_free_event_buffers(dwc);
1650
1651 err2:
1652         pm_runtime_allow(&pdev->dev);
1653
1654 err1:
1655         pm_runtime_put_sync(&pdev->dev);
1656         pm_runtime_disable(&pdev->dev);
1657
1658         clk_bulk_disable(dwc->num_clks, dwc->clks);
1659 unprepare_clks:
1660         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1661 assert_reset:
1662         reset_control_assert(dwc->reset);
1663 put_clks:
1664         clk_bulk_put(dwc->num_clks, dwc->clks);
1665
1666         return ret;
1667 }
1668
1669 static int dwc3_remove(struct platform_device *pdev)
1670 {
1671         struct dwc3     *dwc = platform_get_drvdata(pdev);
1672
1673         pm_runtime_get_sync(&pdev->dev);
1674
1675         dwc3_debugfs_exit(dwc);
1676         dwc3_core_exit_mode(dwc);
1677
1678         dwc3_event_buffers_cleanup(dwc);
1679         dwc3_core_exit(dwc);
1680         dwc3_ulpi_exit(dwc);
1681
1682         pm_runtime_put_sync(&pdev->dev);
1683         pm_runtime_allow(&pdev->dev);
1684         pm_runtime_disable(&pdev->dev);
1685
1686         dwc3_free_event_buffers(dwc);
1687         dwc3_free_scratch_buffers(dwc);
1688         clk_bulk_put(dwc->num_clks, dwc->clks);
1689
1690         return 0;
1691 }
1692
1693 #ifdef CONFIG_PM
1694 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1695 {
1696         int ret;
1697
1698         ret = reset_control_deassert(dwc->reset);
1699         if (ret)
1700                 return ret;
1701
1702         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1703         if (ret)
1704                 goto assert_reset;
1705
1706         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1707         if (ret)
1708                 goto unprepare_clks;
1709
1710         ret = dwc3_core_init(dwc);
1711         if (ret)
1712                 goto disable_clks;
1713
1714         return 0;
1715
1716 disable_clks:
1717         clk_bulk_disable(dwc->num_clks, dwc->clks);
1718 unprepare_clks:
1719         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1720 assert_reset:
1721         reset_control_assert(dwc->reset);
1722
1723         return ret;
1724 }
1725
1726 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1727 {
1728         unsigned long   flags;
1729         u32 reg;
1730
1731         switch (dwc->current_dr_role) {
1732         case DWC3_GCTL_PRTCAP_DEVICE:
1733                 spin_lock_irqsave(&dwc->lock, flags);
1734                 dwc3_gadget_suspend(dwc);
1735                 spin_unlock_irqrestore(&dwc->lock, flags);
1736                 dwc3_core_exit(dwc);
1737                 break;
1738         case DWC3_GCTL_PRTCAP_HOST:
1739                 if (!PMSG_IS_AUTO(msg)) {
1740                         dwc3_core_exit(dwc);
1741                         break;
1742                 }
1743
1744                 /* Let controller to suspend HSPHY before PHY driver suspends */
1745                 if (dwc->dis_u2_susphy_quirk ||
1746                     dwc->dis_enblslpm_quirk) {
1747                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1748                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1749                                 DWC3_GUSB2PHYCFG_SUSPHY;
1750                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1751
1752                         /* Give some time for USB2 PHY to suspend */
1753                         usleep_range(5000, 6000);
1754                 }
1755
1756                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1757                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1758                 break;
1759         case DWC3_GCTL_PRTCAP_OTG:
1760                 /* do nothing during runtime_suspend */
1761                 if (PMSG_IS_AUTO(msg))
1762                         break;
1763
1764                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1765                         spin_lock_irqsave(&dwc->lock, flags);
1766                         dwc3_gadget_suspend(dwc);
1767                         spin_unlock_irqrestore(&dwc->lock, flags);
1768                 }
1769
1770                 dwc3_otg_exit(dwc);
1771                 dwc3_core_exit(dwc);
1772                 break;
1773         default:
1774                 /* do nothing */
1775                 break;
1776         }
1777
1778         dwc3_event_buffers_cleanup(dwc);
1779
1780         /* Put the core into D3 state */
1781         dwc3_set_usb_core_power(dwc, false);
1782
1783         /*
1784          * To avoid reinit of phy during resume, prevent calling the
1785          * dwc3_core_exit() when in D3 state
1786          */
1787         if (!dwc->is_d3)
1788                 dwc3_core_exit(dwc);
1789
1790         return 0;
1791 }
1792
1793 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1794 {
1795         unsigned long   flags;
1796         int             ret;
1797         u32             reg;
1798
1799         /* Bring core to D0 state */
1800         dwc3_set_usb_core_power(dwc, true);
1801
1802         ret = dwc3_core_init(dwc);
1803         if (ret)
1804                 return ret;
1805
1806         switch (dwc->current_dr_role) {
1807         case DWC3_GCTL_PRTCAP_DEVICE:
1808                 ret = dwc3_core_init_for_resume(dwc);
1809                 if (ret)
1810                         return ret;
1811
1812                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1813                 spin_lock_irqsave(&dwc->lock, flags);
1814                 dwc3_gadget_resume(dwc);
1815                 spin_unlock_irqrestore(&dwc->lock, flags);
1816                 break;
1817         case DWC3_GCTL_PRTCAP_HOST:
1818                 if (!PMSG_IS_AUTO(msg)) {
1819                         ret = dwc3_core_init_for_resume(dwc);
1820                         if (ret)
1821                                 return ret;
1822                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1823                         break;
1824                 }
1825                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1826                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1827                 if (dwc->dis_u2_susphy_quirk)
1828                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1829
1830                 if (dwc->dis_enblslpm_quirk)
1831                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1832
1833                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1834
1835                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1836                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1837                 break;
1838         case DWC3_GCTL_PRTCAP_OTG:
1839                 /* nothing to do on runtime_resume */
1840                 if (PMSG_IS_AUTO(msg))
1841                         break;
1842
1843                 ret = dwc3_core_init(dwc);
1844                 if (ret)
1845                         return ret;
1846
1847                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1848
1849                 dwc3_otg_init(dwc);
1850                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1851                         dwc3_otg_host_init(dwc);
1852                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1853                         spin_lock_irqsave(&dwc->lock, flags);
1854                         dwc3_gadget_resume(dwc);
1855                         spin_unlock_irqrestore(&dwc->lock, flags);
1856                 }
1857
1858                 break;
1859         default:
1860                 /* do nothing */
1861                 break;
1862         }
1863
1864         return 0;
1865 }
1866
1867 static int dwc3_runtime_checks(struct dwc3 *dwc)
1868 {
1869         switch (dwc->current_dr_role) {
1870         case DWC3_GCTL_PRTCAP_DEVICE:
1871                 if (dwc->connected)
1872                         return -EBUSY;
1873                 break;
1874         case DWC3_GCTL_PRTCAP_HOST:
1875         default:
1876                 /* do nothing */
1877                 break;
1878         }
1879
1880         return 0;
1881 }
1882
1883 static int dwc3_runtime_suspend(struct device *dev)
1884 {
1885         struct dwc3     *dwc = dev_get_drvdata(dev);
1886         int             ret;
1887
1888         if (dwc3_runtime_checks(dwc))
1889                 return -EBUSY;
1890
1891         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1892         if (ret)
1893                 return ret;
1894
1895         device_init_wakeup(dev, true);
1896
1897         return 0;
1898 }
1899
1900 static int dwc3_runtime_resume(struct device *dev)
1901 {
1902         struct dwc3     *dwc = dev_get_drvdata(dev);
1903         int             ret;
1904
1905         device_init_wakeup(dev, false);
1906
1907         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1908         if (ret)
1909                 return ret;
1910
1911         switch (dwc->current_dr_role) {
1912         case DWC3_GCTL_PRTCAP_DEVICE:
1913                 dwc3_gadget_process_pending_events(dwc);
1914                 break;
1915         case DWC3_GCTL_PRTCAP_HOST:
1916         default:
1917                 /* do nothing */
1918                 break;
1919         }
1920
1921         pm_runtime_mark_last_busy(dev);
1922
1923         return 0;
1924 }
1925
1926 static int dwc3_runtime_idle(struct device *dev)
1927 {
1928         struct dwc3     *dwc = dev_get_drvdata(dev);
1929
1930         switch (dwc->current_dr_role) {
1931         case DWC3_GCTL_PRTCAP_DEVICE:
1932                 if (dwc3_runtime_checks(dwc))
1933                         return -EBUSY;
1934                 break;
1935         case DWC3_GCTL_PRTCAP_HOST:
1936         default:
1937                 /* do nothing */
1938                 break;
1939         }
1940
1941         pm_runtime_mark_last_busy(dev);
1942         pm_runtime_autosuspend(dev);
1943
1944         return 0;
1945 }
1946 #endif /* CONFIG_PM */
1947
1948 #ifdef CONFIG_PM_SLEEP
1949 static int dwc3_suspend(struct device *dev)
1950 {
1951         struct dwc3     *dwc = dev_get_drvdata(dev);
1952         int             ret;
1953
1954         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1955         if (ret)
1956                 return ret;
1957
1958         pinctrl_pm_select_sleep_state(dev);
1959
1960         return 0;
1961 }
1962
1963 static int dwc3_resume(struct device *dev)
1964 {
1965         struct dwc3     *dwc = dev_get_drvdata(dev);
1966         int             ret;
1967
1968         pinctrl_pm_select_default_state(dev);
1969
1970         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1971         if (ret)
1972                 return ret;
1973
1974         pm_runtime_disable(dev);
1975         pm_runtime_set_active(dev);
1976         pm_runtime_enable(dev);
1977
1978         return 0;
1979 }
1980 #endif /* CONFIG_PM_SLEEP */
1981
1982 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1983         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1984         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1985                         dwc3_runtime_idle)
1986 };
1987
1988 #ifdef CONFIG_OF
1989 static const struct of_device_id of_dwc3_match[] = {
1990         {
1991                 .compatible = "snps,dwc3"
1992         },
1993         {
1994                 .compatible = "synopsys,dwc3"
1995         },
1996         { },
1997 };
1998 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1999 #endif
2000
2001 #ifdef CONFIG_ACPI
2002
2003 #define ACPI_ID_INTEL_BSW       "808622B7"
2004
2005 static const struct acpi_device_id dwc3_acpi_match[] = {
2006         { ACPI_ID_INTEL_BSW, 0 },
2007         { },
2008 };
2009 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2010 #endif
2011
2012 static struct platform_driver dwc3_driver = {
2013         .probe          = dwc3_probe,
2014         .remove         = dwc3_remove,
2015         .driver         = {
2016                 .name   = "dwc3",
2017                 .of_match_table = of_match_ptr(of_dwc3_match),
2018                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2019                 .pm     = &dwc3_dev_pm_ops,
2020         },
2021 };
2022
2023 module_platform_driver(dwc3_driver);
2024
2025 MODULE_ALIAS("platform:dwc3");
2026 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2027 MODULE_LICENSE("GPL v2");
2028 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");