drivers/watchdog/of_xilinx_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
   4  *
   5  * (C) Copyright 2013 - 2014 Xilinx, Inc.
   6  * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/err.h>
  11 #include <linux/module.h>
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/ioport.h>
  15 #include <linux/watchdog.h>
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/of_address.h>
  20
  21 /* Register offsets for the Wdt device */
  22 #define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
  23 #define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */
  24 #define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */
  25
  26 /* Control/Status Register Masks  */
  27 #define XWT_CSR0_WRS_MASK       BIT(3) /* Reset status */
  28 #define XWT_CSR0_WDS_MASK       BIT(2) /* Timer state  */
  29 #define XWT_CSR0_EWDT1_MASK     BIT(1) /* Enable bit 1 */
  30
  31 /* Control/Status Register 0/1 bits  */
  32 #define XWT_CSRX_EWDT2_MASK     BIT(0) /* Enable bit 2 */
  33
  34 /* SelfTest constants */
  35 #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
  36 #define XWT_TIMER_FAILED            0xFFFFFFFF
  37
  38 #define WATCHDOG_NAME     "Xilinx Watchdog"
  39
  40 struct xwdt_device {
  41         void __iomem *base;
  42         u32 wdt_interval;
  43         spinlock_t spinlock; /* spinlock for register handling */
  44         struct watchdog_device xilinx_wdt_wdd;
  45         struct clk              *clk;
  46 };
  47
  48 static int xilinx_wdt_start(struct watchdog_device *wdd)
  49 {
  50         int ret;
  51         u32 control_status_reg;
  52         struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  53         struct watchdog_device *xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
  54
  55         ret = clk_enable(xdev->clk);
  56         if (ret) {
  57                 dev_err(wdd->parent, "Failed to enable clock\n");
  58                 return ret;
  59         }
  60
  61         spin_lock(&xdev->spinlock);
  62
  63         /* Clean previous status and enable the watchdog timer */
  64         control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  65         control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
  66
  67         iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
  68                   xdev->base + XWT_TWCSR0_OFFSET);
  69
  70         iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
  71
  72         spin_unlock(&xdev->spinlock);
  73
  74         dev_dbg(xilinx_wdt_wdd->parent, "Watchdog Started!\n");
  75
  76         return 0;
  77 }
  78
  79 static int xilinx_wdt_stop(struct watchdog_device *wdd)
  80 {
  81         u32 control_status_reg;
  82         struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  83         struct watchdog_device *xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
  84
  85         spin_lock(&xdev->spinlock);
  86
  87         control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  88
  89         iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
  90                   xdev->base + XWT_TWCSR0_OFFSET);
  91
  92         iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
  93
  94         spin_unlock(&xdev->spinlock);
  95
  96         clk_disable(xdev->clk);
  97
  98         dev_dbg(xilinx_wdt_wdd->parent, "Watchdog Stopped!\n");
  99
 100         return 0;
 101 }
 102
 103 static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
 104 {
 105         u32 control_status_reg;
 106         struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
 107
 108         spin_lock(&xdev->spinlock);
 109
 110         control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
 111         control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
 112         iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
 113
 114         spin_unlock(&xdev->spinlock);
 115
 116         return 0;
 117 }
 118
 119 static const struct watchdog_info xilinx_wdt_ident = {
 120         .options =  WDIOF_MAGICCLOSE |
 121                     WDIOF_KEEPALIVEPING,
 122         .firmware_version =     1,
 123         .identity =     WATCHDOG_NAME,
 124 };
 125
 126 static const struct watchdog_ops xilinx_wdt_ops = {
 127         .owner = THIS_MODULE,
 128         .start = xilinx_wdt_start,
 129         .stop = xilinx_wdt_stop,
 130         .ping = xilinx_wdt_keepalive,
 131 };
 132
 133 static u32 xwdt_selftest(struct xwdt_device *xdev)
 134 {
 135         int i;
 136         u32 timer_value1;
 137         u32 timer_value2;
 138
 139         spin_lock(&xdev->spinlock);
 140
 141         timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
 142         timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
 143
 144         for (i = 0;
 145                 ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
 146                         (timer_value2 == timer_value1)); i++) {
 147                 timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
 148         }
 149
 150         spin_unlock(&xdev->spinlock);
 151
 152         if (timer_value2 != timer_value1)
 153                 return ~XWT_TIMER_FAILED;
 154         else
 155                 return XWT_TIMER_FAILED;
 156 }
 157
 158 static int xwdt_probe(struct platform_device *pdev)
 159 {
 160         int rc;
 161         u32 pfreq = 0, enable_once = 0;
 162         struct resource *res;
 163         struct xwdt_device *xdev;
 164         struct watchdog_device *xilinx_wdt_wdd;
 165
 166         xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
 167         if (!xdev)
 168                 return -ENOMEM;
 169
 170         xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
 171         xilinx_wdt_wdd->info = &xilinx_wdt_ident;
 172         xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
 173         xilinx_wdt_wdd->parent = &pdev->dev;
 174
 175         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 176         xdev->base = devm_ioremap_resource(&pdev->dev, res);
 177         if (IS_ERR(xdev->base))
 178                 return PTR_ERR(xdev->base);
 179
 180         rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
 181                                   &xdev->wdt_interval);
 182         if (rc)
 183                 dev_warn(&pdev->dev,
 184                          "Parameter \"xlnx,wdt-interval\" not found\n");
 185
 186         rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
 187                                   &enable_once);
 188         if (rc)
 189                 dev_warn(&pdev->dev,
 190                          "Parameter \"xlnx,wdt-enable-once\" not found\n");
 191
 192         watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
 193
 194         xdev->clk = devm_clk_get(&pdev->dev, NULL);
 195         if (IS_ERR(xdev->clk)) {
 196                 if (PTR_ERR(xdev->clk) != -ENOENT)
 197                         return PTR_ERR(xdev->clk);
 198
 199                 /*
 200                  * Clock framework support is optional, continue on
 201                  * anyways if we don't find a matching clock.
 202                  */
 203                 xdev->clk = NULL;
 204
 205                 rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 206                                           &pfreq);
 207                 if (rc)
 208                         dev_warn(&pdev->dev,
 209                                  "The watchdog clock freq cannot be obtained\n");
 210         } else {
 211                 pfreq = clk_get_rate(xdev->clk);
 212         }
 213
 214         /*
 215          * Twice of the 2^wdt_interval / freq  because the first wdt overflow is
 216          * ignored (interrupt), reset is only generated at second wdt overflow
 217          */
 218         if (pfreq && xdev->wdt_interval)
 219                 xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
 220                                           pfreq);
 221
 222         spin_lock_init(&xdev->spinlock);
 223         watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
 224
 225         rc = clk_prepare_enable(xdev->clk);
 226         if (rc) {
 227                 dev_err(&pdev->dev, "unable to enable clock\n");
 228                 return rc;
 229         }
 230
 231         rc = xwdt_selftest(xdev);
 232         if (rc == XWT_TIMER_FAILED) {
 233                 dev_err(&pdev->dev, "SelfTest routine error\n");
 234                 goto err_clk_disable;
 235         }
 236
 237         rc = watchdog_register_device(xilinx_wdt_wdd);
 238         if (rc) {
 239                 dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
 240                 goto err_clk_disable;
 241         }
 242
 243         clk_disable(xdev->clk);
 244
 245         dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
 246                  xdev->base, xilinx_wdt_wdd->timeout);
 247
 248         platform_set_drvdata(pdev, xdev);
 249
 250         return 0;
 251 err_clk_disable:
 252         clk_disable_unprepare(xdev->clk);
 253
 254         return rc;
 255 }
 256
 257 static int xwdt_remove(struct platform_device *pdev)
 258 {
 259         struct xwdt_device *xdev = platform_get_drvdata(pdev);
 260
 261         watchdog_unregister_device(&xdev->xilinx_wdt_wdd);
 262         clk_disable_unprepare(xdev->clk);
 263
 264         return 0;
 265 }
 266
 267 /**
 268  * xwdt_suspend - Suspend the device.
 269  *
 270  * @dev: handle to the device structure.
 271  * Return: 0 always.
 272  */
 273 static int __maybe_unused xwdt_suspend(struct device *dev)
 274 {
 275         struct xwdt_device *xdev = dev_get_drvdata(dev);
 276
 277         if (watchdog_active(&xdev->xilinx_wdt_wdd))
 278                 xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
 279
 280         return 0;
 281 }
 282
 283 /**
 284  * xwdt_resume - Resume the device.
 285  *
 286  * @dev: handle to the device structure.
 287  * Return: 0 on success, errno otherwise.
 288  */
 289 static int __maybe_unused xwdt_resume(struct device *dev)
 290 {
 291         struct xwdt_device *xdev = dev_get_drvdata(dev);
 292         int ret = 0;
 293
 294         if (watchdog_active(&xdev->xilinx_wdt_wdd))
 295                 ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
 296
 297         return ret;
 298 }
 299
 300 static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
 301
 302 /* Match table for of_platform binding */
 303 static const struct of_device_id xwdt_of_match[] = {
 304         { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
 305         { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
 306         {},
 307 };
 308 MODULE_DEVICE_TABLE(of, xwdt_of_match);
 309
 310 static struct platform_driver xwdt_driver = {
 311         .probe       = xwdt_probe,
 312         .remove      = xwdt_remove,
 313         .driver = {
 314                 .name  = WATCHDOG_NAME,
 315                 .of_match_table = xwdt_of_match,
 316                 .pm = &xwdt_pm_ops,
 317         },
 318 };
 319
 320 module_platform_driver(xwdt_driver);
 321
 322 MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
 323 MODULE_DESCRIPTION("Xilinx Watchdog driver");
 324 MODULE_LICENSE("GPL");