4 * Copyright (C) 2016 - 2017 Xilinx, Inc.
7 * This driver is developed for SDFEC16 IP. It provides a char device
8 * in sysfs and supports file operations like open(), close() and ioctl().
10 * This program is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef __XILINX_SDFEC_H__
24 #define __XILINX_SDFEC_H__
26 /* Shared LDPC Tables */
27 #define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
28 #define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x103FC)
29 #define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
30 #define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x18FFC)
31 #define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
32 #define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x27FFC)
35 XSDFEC_CODE_INVALID = 0,
41 XSDFEC_INVALID_ORDER = 0,
42 XSDFEC_MAINTAIN_ORDER,
55 XSDFEC_UNKNOWN_MODE = 0,
61 * struct xsdfec_turbo - User data for Turbo Codes
62 * @alg: Algorithm used by Turbo Codes
63 * @scale: Scale Factor
64 * Turbo Code structure to communicate parameters to XSDFEC driver
72 * struct xsdfec_ldpc_params - User data for LDPC Codes
73 * @n: Number of code word bits
74 * @k: Number of information bits
75 * @psize: Size of sub-matrix
76 * @nlayers: Number of layers in code
77 * @nqc: Quasi Cyclic Number
78 * @nmqc: Number of M-sized QC operations in parity check matrix
79 * @nm: Number of M-size vectors in N
80 * @norm_type: Normalization required or not
81 * @no_packing: Determines if multiple QC ops should be performed
82 * @special_qc: Sub-Matrix property for Circulant weight > 0
83 * @no_final_parity: Decide if final parity check needs to be performed
84 * @max_schedule: Experimental code word scheduling limit
93 * This structure describes the LDPC code that is passed to the driver
96 struct xsdfec_ldpc_params {
112 u32 sc_table[XSDFEC_LDPC_SC_TABLE_ADDR_HIGH -
113 XSDFEC_LDPC_SC_TABLE_ADDR_BASE];
114 u32 la_table[XSDFEC_LDPC_LA_TABLE_ADDR_HIGH -
115 XSDFEC_LDPC_LA_TABLE_ADDR_BASE];
116 u32 qc_table[XSDFEC_LDPC_QC_TABLE_ADDR_HIGH -
117 XSDFEC_LDPC_QC_TABLE_ADDR_BASE];
122 * struct xsdfec_status - Status of SDFEC device
123 * @fec_id: ID of SDFEC instance
124 * @code: The codes being used by the SDFEC instance
125 * @order: Order of Operation
126 * @state: State of the SDFEC device
127 * @mode: Mode of Operation
128 * @activity: Describes if the SDFEC instance is Active
129 * @cecc_count: Count of the Correctable ECC Errors occurred
131 struct xsdfec_status {
133 enum xsdfec_code code;
134 enum xsdfec_order order;
135 enum xsdfec_state state;
136 enum xsdfec_op_mode mode;
142 * struct xsdfec_config - Configuration of SDFEC device
143 * @fec_id: ID of SDFEC instance
144 * @code: The codes being used by the SDFEC instance
145 * @mode: Mode that the SDFEC is operating
146 * @order: Order of Operation
147 * @state: State of the SDFEC device
149 struct xsdfec_config {
151 enum xsdfec_code code;
152 enum xsdfec_op_mode mode;
153 enum xsdfec_order order;
154 enum xsdfec_state state;
158 * struct xsdfec_irq - Enabling or Disabling Interrupts
159 * @enable_isr: If true enables the ISR
160 * @enable_ecc_isr: If true enables the ECC ISR
170 #define XSDFEC_MAGIC 'f'
171 /* ioctl to start sdfec device */
172 #define XSDFEC_START_DEV _IO(XSDFEC_MAGIC, 0)
173 /* ioctl to stop the device */
174 #define XSDFEC_STOP_DEV _IO(XSDFEC_MAGIC, 1)
175 /* ioctl to communicate to the driver that device has been reset */
176 #define XSDFEC_RESET_REQ _IO(XSDFEC_MAGIC, 2)
177 /* ioctl that returns status of sdfec device */
178 #define XSDFEC_GET_STATUS _IOR(XSDFEC_MAGIC, 3, struct xsdfec_status *)
179 /* ioctl to enable or disable irq */
180 #define XSDFEC_SET_IRQ _IOW(XSDFEC_MAGIC, 4, struct xsdfec_irq *)
181 /* ioctl to enable turbo params for sdfec device */
182 #define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 5, struct xsdfec_turbo *)
183 /* ioctl to add an LDPC code to the sdfec ldpc codes */
184 #define XSDFEC_ADD_LDPC_CODE_PARAMS \
185 _IOW(XSDFEC_MAGIC, 6, struct xsdfec_ldpc_params *)
186 /* ioctl that returns sdfec device configuration */
187 #define XSDFEC_GET_CONFIG _IOR(XSDFEC_MAGIC, 7, struct xsdfec_config *)
188 /* ioctl that returns sdfec turbo param values */
189 #define XSDFEC_GET_TURBO _IOR(XSDFEC_MAGIC, 8, struct xsdfec_turbo *)
190 /* ioctl that returns sdfec LDPC code param values, code_id must be specified */
191 #define XSDFEC_GET_LDPC_CODE_PARAMS \
192 _IOWR(XSDFEC_MAGIC, 9, struct xsdfec_ldpc_params *)
193 /* ioctl that sets order, if order of blocks can change from input to output */
194 #define XSDFEC_SET_ORDER _IOW(XSDFEC_MAGIC, 10, enum xsdfec_order)
196 #endif /* __XILINX_SDFEC_H__ */