arch/arm64/boot/dts/xilinx/zynqmp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 / {
  16         compatible = "xlnx,zynqmp";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "arm,cortex-a53", "arm,armv8";
  26                         device_type = "cpu";
  27                         enable-method = "psci";
  28                         operating-points-v2 = <&cpu_opp_table>;
  29                         reg = <0x0>;
  30                         cpu-idle-states = <&CPU_SLEEP_0>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         compatible = "arm,cortex-a53", "arm,armv8";
  35                         device_type = "cpu";
  36                         enable-method = "psci";
  37                         reg = <0x1>;
  38                         operating-points-v2 = <&cpu_opp_table>;
  39                         cpu-idle-states = <&CPU_SLEEP_0>;
  40                 };
  41
  42                 cpu2: cpu@2 {
  43                         compatible = "arm,cortex-a53", "arm,armv8";
  44                         device_type = "cpu";
  45                         enable-method = "psci";
  46                         reg = <0x2>;
  47                         operating-points-v2 = <&cpu_opp_table>;
  48                         cpu-idle-states = <&CPU_SLEEP_0>;
  49                 };
  50
  51                 cpu3: cpu@3 {
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         device_type = "cpu";
  54                         enable-method = "psci";
  55                         reg = <0x3>;
  56                         operating-points-v2 = <&cpu_opp_table>;
  57                         cpu-idle-states = <&CPU_SLEEP_0>;
  58                 };
  59
  60                 idle-states {
  61                         entry-method = "arm,psci";
  62
  63                         CPU_SLEEP_0: cpu-sleep-0 {
  64                                 compatible = "arm,idle-state";
  65                                 arm,psci-suspend-param = <0x40000000>;
  66                                 local-timer-stop;
  67                                 entry-latency-us = <300>;
  68                                 exit-latency-us = <600>;
  69                                 min-residency-us = <10000>;
  70                         };
  71                 };
  72         };
  73
  74         cpu_opp_table: cpu_opp_table {
  75                 compatible = "operating-points-v2";
  76                 opp-shared;
  77                 opp00 {
  78                         opp-hz = /bits/ 64 <1199999988>;
  79                         opp-microvolt = <1000000>;
  80                         clock-latency-ns = <500000>;
  81                 };
  82                 opp01 {
  83                         opp-hz = /bits/ 64 <599999994>;
  84                         opp-microvolt = <1000000>;
  85                         clock-latency-ns = <500000>;
  86                 };
  87                 opp02 {
  88                         opp-hz = /bits/ 64 <399999996>;
  89                         opp-microvolt = <1000000>;
  90                         clock-latency-ns = <500000>;
  91                 };
  92                 opp03 {
  93                         opp-hz = /bits/ 64 <299999997>;
  94                         opp-microvolt = <1000000>;
  95                         clock-latency-ns = <500000>;
  96                 };
  97         };
  98
  99         dcc: dcc {
 100                 compatible = "arm,dcc";
 101                 status = "disabled";
 102                 u-boot,dm-pre-reloc;
 103         };
 104
 105         pinctrl0: pinctrl {
 106                 compatible = "xlnx,zynqmp-pinctrl";
 107                 status = "disabled";
 108         };
 109
 110         power-domains {
 111                 compatible = "xlnx,zynqmp-genpd";
 112
 113                 pd_usb0: pd-usb0 {
 114                         #power-domain-cells = <0x0>;
 115                         pd-id = <0x16>;
 116                 };
 117
 118                 pd_usb1: pd-usb1 {
 119                         #power-domain-cells = <0x0>;
 120                         pd-id = <0x17>;
 121                 };
 122
 123                 pd_sata: pd-sata {
 124                         #power-domain-cells = <0x0>;
 125                         pd-id = <0x1c>;
 126                 };
 127
 128                 pd_spi0: pd-spi0 {
 129                         #power-domain-cells = <0x0>;
 130                         pd-id = <0x23>;
 131                 };
 132
 133                 pd_spi1: pd-spi1 {
 134                         #power-domain-cells = <0x0>;
 135                         pd-id = <0x24>;
 136                 };
 137
 138                 pd_uart0: pd-uart0 {
 139                         #power-domain-cells = <0x0>;
 140                         pd-id = <0x21>;
 141                 };
 142
 143                 pd_uart1: pd-uart1 {
 144                         #power-domain-cells = <0x0>;
 145                         pd-id = <0x22>;
 146                 };
 147
 148                 pd_eth0: pd-eth0 {
 149                         #power-domain-cells = <0x0>;
 150                         pd-id = <0x1d>;
 151                 };
 152
 153                 pd_eth1: pd-eth1 {
 154                         #power-domain-cells = <0x0>;
 155                         pd-id = <0x1e>;
 156                 };
 157
 158                 pd_eth2: pd-eth2 {
 159                         #power-domain-cells = <0x0>;
 160                         pd-id = <0x1f>;
 161                 };
 162
 163                 pd_eth3: pd-eth3 {
 164                         #power-domain-cells = <0x0>;
 165                         pd-id = <0x20>;
 166                 };
 167
 168                 pd_i2c0: pd-i2c0 {
 169                         #power-domain-cells = <0x0>;
 170                         pd-id = <0x25>;
 171                 };
 172
 173                 pd_i2c1: pd-i2c1 {
 174                         #power-domain-cells = <0x0>;
 175                         pd-id = <0x26>;
 176                 };
 177
 178                 pd_dp: pd-dp {
 179                         #power-domain-cells = <0x0>;
 180                         pd-id = <0x29>;
 181                 };
 182
 183                 pd_gdma: pd-gdma {
 184                         #power-domain-cells = <0x0>;
 185                         pd-id = <0x2a>;
 186                 };
 187
 188                 pd_adma: pd-adma {
 189                         #power-domain-cells = <0x0>;
 190                         pd-id = <0x2b>;
 191                 };
 192
 193                 pd_ttc0: pd-ttc0 {
 194                         #power-domain-cells = <0x0>;
 195                         pd-id = <0x18>;
 196                 };
 197
 198                 pd_ttc1: pd-ttc1 {
 199                         #power-domain-cells = <0x0>;
 200                         pd-id = <0x19>;
 201                 };
 202
 203                 pd_ttc2: pd-ttc2 {
 204                         #power-domain-cells = <0x0>;
 205                         pd-id = <0x1a>;
 206                 };
 207
 208                 pd_ttc3: pd-ttc3 {
 209                         #power-domain-cells = <0x0>;
 210                         pd-id = <0x1b>;
 211                 };
 212
 213                 pd_sd0: pd-sd0 {
 214                         #power-domain-cells = <0x0>;
 215                         pd-id = <0x27>;
 216                 };
 217
 218                 pd_sd1: pd-sd1 {
 219                         #power-domain-cells = <0x0>;
 220                         pd-id = <0x28>;
 221                 };
 222
 223                 pd_nand: pd-nand {
 224                         #power-domain-cells = <0x0>;
 225                         pd-id = <0x2c>;
 226                 };
 227
 228                 pd_qspi: pd-qspi {
 229                         #power-domain-cells = <0x0>;
 230                         pd-id = <0x2d>;
 231                 };
 232
 233                 pd_gpio: pd-gpio {
 234                         #power-domain-cells = <0x0>;
 235                         pd-id = <0x2e>;
 236                 };
 237
 238                 pd_can0: pd-can0 {
 239                         #power-domain-cells = <0x0>;
 240                         pd-id = <0x2f>;
 241                 };
 242
 243                 pd_can1: pd-can1 {
 244                         #power-domain-cells = <0x0>;
 245                         pd-id = <0x30>;
 246                 };
 247
 248                 pd_pcie: pd-pcie {
 249                         #power-domain-cells = <0x0>;
 250                         pd-id = <0x3b>;
 251                 };
 252
 253                 pd_gpu: pd-gpu {
 254                         #power-domain-cells = <0x0>;
 255                         pd-id = <0x3a 0x14 0x15>;
 256                 };
 257         };
 258
 259         /* PMU1<->APU IPI mailbox controller */
 260         ipi_mailbox_pmu1: mailbox@ff990400 {
 261                 compatible = "xlnx,zynqmp-ipi-mailbox";
 262                 reg = <0x0 0xff9905c0 0x0 0x20>,
 263                       <0x0 0xff9905e0 0x0 0x20>,
 264                       <0x0 0xff990e80 0x0 0x20>,
 265                       <0x0 0xff990ea0 0x0 0x20>;
 266                 reg-names = "local_request_region", "local_response_region",
 267                             "remote_request_region", "remote_response_region";
 268                 #mbox-cells = <1>;
 269                 xlnx,ipi-ids = <0 4>;
 270                 interrupt-parent = <&gic>;
 271                 interrupts = <0 35 4>;
 272         };
 273
 274         pmu {
 275                 compatible = "arm,armv8-pmuv3";
 276                 interrupt-parent = <&gic>;
 277                 interrupts = <0 143 4>,
 278                              <0 144 4>,
 279                              <0 145 4>,
 280                              <0 146 4>;
 281         };
 282
 283         psci {
 284                 compatible = "arm,psci-0.2";
 285                 method = "smc";
 286         };
 287
 288         firmware {
 289                 zynqmp_firmware: zynqmp-firmware {
 290                         compatible = "xlnx,zynqmp-firmware";
 291                         method = "smc";
 292                 };
 293         };
 294
 295         zynqmp_power: zynqmp-power {
 296                 compatible = "xlnx,zynqmp-power";
 297                 mboxes = <&ipi_mailbox_pmu1 0>,
 298                          <&ipi_mailbox_pmu1 1>;
 299                 mbox-names = "tx", "rx";
 300         };
 301
 302         timer {
 303                 compatible = "arm,armv8-timer";
 304                 interrupt-parent = <&gic>;
 305                 interrupts = <1 13 0xf08>,
 306                              <1 14 0xf08>,
 307                              <1 11 0xf08>,
 308                              <1 10 0xf08>;
 309         };
 310
 311         edac {
 312                 compatible = "arm,cortex-a53-edac";
 313         };
 314
 315         fpga_full: fpga-full {
 316                 compatible = "fpga-region";
 317                 fpga-mgr = <&pcap>;
 318                 #address-cells = <2>;
 319                 #size-cells = <2>;
 320         };
 321
 322         nvmem_firmware {
 323                 compatible = "xlnx,zynqmp-nvmem-fw";
 324                 #address-cells = <1>;
 325                 #size-cells = <1>;
 326
 327                 soc_revision: soc_revision@0 {
 328                         reg = <0x0 0x4>;
 329                 };
 330         };
 331
 332         pcap: pcap {
 333                 compatible = "xlnx,zynqmp-pcap-fpga";
 334         };
 335
 336         rst: reset-controller {
 337                 compatible = "xlnx,zynqmp-reset";
 338                 #reset-cells = <1>;
 339         };
 340
 341         xlnx_rsa: zynqmp_rsa {
 342                 compatible = "xlnx,zynqmp-rsa";
 343         };
 344
 345         xlnx_keccak_384: sha384 {
 346                 compatible = "xlnx,zynqmp-keccak-384";
 347         };
 348
 349         amba_apu: amba_apu@0 {
 350                 compatible = "simple-bus";
 351                 #address-cells = <2>;
 352                 #size-cells = <1>;
 353                 ranges = <0 0 0 0 0xffffffff>;
 354
 355                 gic: interrupt-controller@f9010000 {
 356                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 357                         #interrupt-cells = <3>;
 358                         reg = <0x0 0xf9010000 0x10000>,
 359                               <0x0 0xf9020000 0x20000>,
 360                               <0x0 0xf9040000 0x20000>,
 361                               <0x0 0xf9060000 0x20000>;
 362                         interrupt-controller;
 363                         interrupt-parent = <&gic>;
 364                         interrupts = <1 9 0xf04>;
 365                 };
 366         };
 367
 368         amba: amba {
 369                 compatible = "simple-bus";
 370                 u-boot,dm-pre-reloc;
 371                 #address-cells = <2>;
 372                 #size-cells = <2>;
 373                 ranges;
 374
 375                 can0: can@ff060000 {
 376                         compatible = "xlnx,zynq-can-1.0";
 377                         status = "disabled";
 378                         clock-names = "can_clk", "pclk";
 379                         reg = <0x0 0xff060000 0x0 0x1000>;
 380                         interrupts = <0 23 4>;
 381                         interrupt-parent = <&gic>;
 382                         tx-fifo-depth = <0x40>;
 383                         rx-fifo-depth = <0x40>;
 384                         power-domains = <&pd_can0>;
 385                 };
 386
 387                 can1: can@ff070000 {
 388                         compatible = "xlnx,zynq-can-1.0";
 389                         status = "disabled";
 390                         clock-names = "can_clk", "pclk";
 391                         reg = <0x0 0xff070000 0x0 0x1000>;
 392                         interrupts = <0 24 4>;
 393                         interrupt-parent = <&gic>;
 394                         tx-fifo-depth = <0x40>;
 395                         rx-fifo-depth = <0x40>;
 396                         power-domains = <&pd_can1>;
 397                 };
 398
 399                 cci: cci@fd6e0000 {
 400                         compatible = "arm,cci-400";
 401                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 402                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 403                         #address-cells = <1>;
 404                         #size-cells = <1>;
 405
 406                         pmu@9000 {
 407                                 compatible = "arm,cci-400-pmu,r1";
 408                                 reg = <0x9000 0x5000>;
 409                                 interrupt-parent = <&gic>;
 410                                 interrupts = <0 123 4>,
 411                                              <0 123 4>,
 412                                              <0 123 4>,
 413                                              <0 123 4>,
 414                                              <0 123 4>;
 415                         };
 416                 };
 417
 418                 /* GDMA */
 419                 fpd_dma_chan1: dma@fd500000 {
 420                         status = "disabled";
 421                         compatible = "xlnx,zynqmp-dma-1.0";
 422                         reg = <0x0 0xfd500000 0x0 0x1000>;
 423                         interrupt-parent = <&gic>;
 424                         interrupts = <0 124 4>;
 425                         clock-names = "clk_main", "clk_apb";
 426                         xlnx,bus-width = <128>;
 427                         #stream-id-cells = <1>;
 428                         iommus = <&smmu 0x14e8>;
 429                         power-domains = <&pd_gdma>;
 430                 };
 431
 432                 fpd_dma_chan2: dma@fd510000 {
 433                         status = "disabled";
 434                         compatible = "xlnx,zynqmp-dma-1.0";
 435                         reg = <0x0 0xfd510000 0x0 0x1000>;
 436                         interrupt-parent = <&gic>;
 437                         interrupts = <0 125 4>;
 438                         clock-names = "clk_main", "clk_apb";
 439                         xlnx,bus-width = <128>;
 440                         #stream-id-cells = <1>;
 441                         iommus = <&smmu 0x14e9>;
 442                         power-domains = <&pd_gdma>;
 443                 };
 444
 445                 fpd_dma_chan3: dma@fd520000 {
 446                         status = "disabled";
 447                         compatible = "xlnx,zynqmp-dma-1.0";
 448                         reg = <0x0 0xfd520000 0x0 0x1000>;
 449                         interrupt-parent = <&gic>;
 450                         interrupts = <0 126 4>;
 451                         clock-names = "clk_main", "clk_apb";
 452                         xlnx,bus-width = <128>;
 453                         #stream-id-cells = <1>;
 454                         iommus = <&smmu 0x14ea>;
 455                         power-domains = <&pd_gdma>;
 456                 };
 457
 458                 fpd_dma_chan4: dma@fd530000 {
 459                         status = "disabled";
 460                         compatible = "xlnx,zynqmp-dma-1.0";
 461                         reg = <0x0 0xfd530000 0x0 0x1000>;
 462                         interrupt-parent = <&gic>;
 463                         interrupts = <0 127 4>;
 464                         clock-names = "clk_main", "clk_apb";
 465                         xlnx,bus-width = <128>;
 466                         #stream-id-cells = <1>;
 467                         iommus = <&smmu 0x14eb>;
 468                         power-domains = <&pd_gdma>;
 469                 };
 470
 471                 fpd_dma_chan5: dma@fd540000 {
 472                         status = "disabled";
 473                         compatible = "xlnx,zynqmp-dma-1.0";
 474                         reg = <0x0 0xfd540000 0x0 0x1000>;
 475                         interrupt-parent = <&gic>;
 476                         interrupts = <0 128 4>;
 477                         clock-names = "clk_main", "clk_apb";
 478                         xlnx,bus-width = <128>;
 479                         #stream-id-cells = <1>;
 480                         iommus = <&smmu 0x14ec>;
 481                         power-domains = <&pd_gdma>;
 482                 };
 483
 484                 fpd_dma_chan6: dma@fd550000 {
 485                         status = "disabled";
 486                         compatible = "xlnx,zynqmp-dma-1.0";
 487                         reg = <0x0 0xfd550000 0x0 0x1000>;
 488                         interrupt-parent = <&gic>;
 489                         interrupts = <0 129 4>;
 490                         clock-names = "clk_main", "clk_apb";
 491                         xlnx,bus-width = <128>;
 492                         #stream-id-cells = <1>;
 493                         iommus = <&smmu 0x14ed>;
 494                         power-domains = <&pd_gdma>;
 495                 };
 496
 497                 fpd_dma_chan7: dma@fd560000 {
 498                         status = "disabled";
 499                         compatible = "xlnx,zynqmp-dma-1.0";
 500                         reg = <0x0 0xfd560000 0x0 0x1000>;
 501                         interrupt-parent = <&gic>;
 502                         interrupts = <0 130 4>;
 503                         clock-names = "clk_main", "clk_apb";
 504                         xlnx,bus-width = <128>;
 505                         #stream-id-cells = <1>;
 506                         iommus = <&smmu 0x14ee>;
 507                         power-domains = <&pd_gdma>;
 508                 };
 509
 510                 fpd_dma_chan8: dma@fd570000 {
 511                         status = "disabled";
 512                         compatible = "xlnx,zynqmp-dma-1.0";
 513                         reg = <0x0 0xfd570000 0x0 0x1000>;
 514                         interrupt-parent = <&gic>;
 515                         interrupts = <0 131 4>;
 516                         clock-names = "clk_main", "clk_apb";
 517                         xlnx,bus-width = <128>;
 518                         #stream-id-cells = <1>;
 519                         iommus = <&smmu 0x14ef>;
 520                         power-domains = <&pd_gdma>;
 521                 };
 522
 523                 gpu: gpu@fd4b0000 {
 524                         status = "disabled";
 525                         compatible = "arm,mali-400", "arm,mali-utgard";
 526                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 527                         interrupt-parent = <&gic>;
 528                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 529                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 530                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 531                         power-domains = <&pd_gpu>;
 532                 };
 533
 534                 /* LPDDMA default allows only secured access. inorder to enable
 535                  * These dma channels, Users should ensure that these dma
 536                  * Channels are allowed for non secure access.
 537                  */
 538                 lpd_dma_chan1: dma@ffa80000 {
 539                         status = "disabled";
 540                         compatible = "xlnx,zynqmp-dma-1.0";
 541                         reg = <0x0 0xffa80000 0x0 0x1000>;
 542                         interrupt-parent = <&gic>;
 543                         interrupts = <0 77 4>;
 544                         clock-names = "clk_main", "clk_apb";
 545                         xlnx,bus-width = <64>;
 546                         #stream-id-cells = <1>;
 547                         /* iommus = <&smmu 0x868>; */
 548                         power-domains = <&pd_adma>;
 549                 };
 550
 551                 lpd_dma_chan2: dma@ffa90000 {
 552                         status = "disabled";
 553                         compatible = "xlnx,zynqmp-dma-1.0";
 554                         reg = <0x0 0xffa90000 0x0 0x1000>;
 555                         interrupt-parent = <&gic>;
 556                         interrupts = <0 78 4>;
 557                         clock-names = "clk_main", "clk_apb";
 558                         xlnx,bus-width = <64>;
 559                         #stream-id-cells = <1>;
 560                         /* iommus = <&smmu 0x869>; */
 561                         power-domains = <&pd_adma>;
 562                 };
 563
 564                 lpd_dma_chan3: dma@ffaa0000 {
 565                         status = "disabled";
 566                         compatible = "xlnx,zynqmp-dma-1.0";
 567                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 568                         interrupt-parent = <&gic>;
 569                         interrupts = <0 79 4>;
 570                         clock-names = "clk_main", "clk_apb";
 571                         xlnx,bus-width = <64>;
 572                         #stream-id-cells = <1>;
 573                         /* iommus = <&smmu 0x86a>; */
 574                         power-domains = <&pd_adma>;
 575                 };
 576
 577                 lpd_dma_chan4: dma@ffab0000 {
 578                         status = "disabled";
 579                         compatible = "xlnx,zynqmp-dma-1.0";
 580                         reg = <0x0 0xffab0000 0x0 0x1000>;
 581                         interrupt-parent = <&gic>;
 582                         interrupts = <0 80 4>;
 583                         clock-names = "clk_main", "clk_apb";
 584                         xlnx,bus-width = <64>;
 585                         #stream-id-cells = <1>;
 586                         /* iommus = <&smmu 0x86b>; */
 587                         power-domains = <&pd_adma>;
 588                 };
 589
 590                 lpd_dma_chan5: dma@ffac0000 {
 591                         status = "disabled";
 592                         compatible = "xlnx,zynqmp-dma-1.0";
 593                         reg = <0x0 0xffac0000 0x0 0x1000>;
 594                         interrupt-parent = <&gic>;
 595                         interrupts = <0 81 4>;
 596                         clock-names = "clk_main", "clk_apb";
 597                         xlnx,bus-width = <64>;
 598                         #stream-id-cells = <1>;
 599                         /* iommus = <&smmu 0x86c>; */
 600                         power-domains = <&pd_adma>;
 601                 };
 602
 603                 lpd_dma_chan6: dma@ffad0000 {
 604                         status = "disabled";
 605                         compatible = "xlnx,zynqmp-dma-1.0";
 606                         reg = <0x0 0xffad0000 0x0 0x1000>;
 607                         interrupt-parent = <&gic>;
 608                         interrupts = <0 82 4>;
 609                         clock-names = "clk_main", "clk_apb";
 610                         xlnx,bus-width = <64>;
 611                         #stream-id-cells = <1>;
 612                         /* iommus = <&smmu 0x86d>; */
 613                         power-domains = <&pd_adma>;
 614                 };
 615
 616                 lpd_dma_chan7: dma@ffae0000 {
 617                         status = "disabled";
 618                         compatible = "xlnx,zynqmp-dma-1.0";
 619                         reg = <0x0 0xffae0000 0x0 0x1000>;
 620                         interrupt-parent = <&gic>;
 621                         interrupts = <0 83 4>;
 622                         clock-names = "clk_main", "clk_apb";
 623                         xlnx,bus-width = <64>;
 624                         #stream-id-cells = <1>;
 625                         /* iommus = <&smmu 0x86e>; */
 626                         power-domains = <&pd_adma>;
 627                 };
 628
 629                 lpd_dma_chan8: dma@ffaf0000 {
 630                         status = "disabled";
 631                         compatible = "xlnx,zynqmp-dma-1.0";
 632                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 633                         interrupt-parent = <&gic>;
 634                         interrupts = <0 84 4>;
 635                         clock-names = "clk_main", "clk_apb";
 636                         xlnx,bus-width = <64>;
 637                         #stream-id-cells = <1>;
 638                         /* iommus = <&smmu 0x86f>; */
 639                         power-domains = <&pd_adma>;
 640                 };
 641
 642                 mc: memory-controller@fd070000 {
 643                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 644                         reg = <0x0 0xfd070000 0x0 0x30000>;
 645                         interrupt-parent = <&gic>;
 646                         interrupts = <0 112 4>;
 647                 };
 648
 649                 nand0: nand@ff100000 {
 650                         compatible = "arasan,nfc-v3p10";
 651                         status = "disabled";
 652                         reg = <0x0 0xff100000 0x0 0x1000>;
 653                         clock-names = "clk_sys", "clk_flash";
 654                         interrupt-parent = <&gic>;
 655                         interrupts = <0 14 4>;
 656                         #address-cells = <1>;
 657                         #size-cells = <0>;
 658                         #stream-id-cells = <1>;
 659                         iommus = <&smmu 0x872>;
 660                         power-domains = <&pd_nand>;
 661                 };
 662
 663                 gem0: ethernet@ff0b0000 {
 664                         compatible = "cdns,zynqmp-gem";
 665                         status = "disabled";
 666                         interrupt-parent = <&gic>;
 667                         interrupts = <0 57 4>, <0 57 4>;
 668                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 669                         clock-names = "pclk", "hclk", "tx_clk";
 670                         #address-cells = <1>;
 671                         #size-cells = <0>;
 672                         #stream-id-cells = <1>;
 673                         iommus = <&smmu 0x874>;
 674                         power-domains = <&pd_eth0>;
 675                 };
 676
 677                 gem1: ethernet@ff0c0000 {
 678                         compatible = "cdns,zynqmp-gem";
 679                         status = "disabled";
 680                         interrupt-parent = <&gic>;
 681                         interrupts = <0 59 4>, <0 59 4>;
 682                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 683                         clock-names = "pclk", "hclk", "tx_clk";
 684                         #address-cells = <1>;
 685                         #size-cells = <0>;
 686                         #stream-id-cells = <1>;
 687                         iommus = <&smmu 0x875>;
 688                         power-domains = <&pd_eth1>;
 689                 };
 690
 691                 gem2: ethernet@ff0d0000 {
 692                         compatible = "cdns,zynqmp-gem";
 693                         status = "disabled";
 694                         interrupt-parent = <&gic>;
 695                         interrupts = <0 61 4>, <0 61 4>;
 696                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 697                         clock-names = "pclk", "hclk", "tx_clk";
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                         #stream-id-cells = <1>;
 701                         iommus = <&smmu 0x876>;
 702                         power-domains = <&pd_eth2>;
 703                 };
 704
 705                 gem3: ethernet@ff0e0000 {
 706                         compatible = "cdns,zynqmp-gem";
 707                         status = "disabled";
 708                         interrupt-parent = <&gic>;
 709                         interrupts = <0 63 4>, <0 63 4>;
 710                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 711                         clock-names = "pclk", "hclk", "tx_clk";
 712                         #address-cells = <1>;
 713                         #size-cells = <0>;
 714                         #stream-id-cells = <1>;
 715                         iommus = <&smmu 0x877>;
 716                         power-domains = <&pd_eth3>;
 717                 };
 718
 719                 gpio: gpio@ff0a0000 {
 720                         compatible = "xlnx,zynqmp-gpio-1.0";
 721                         status = "disabled";
 722                         #gpio-cells = <0x2>;
 723                         interrupt-parent = <&gic>;
 724                         interrupts = <0 16 4>;
 725                         interrupt-controller;
 726                         #interrupt-cells = <2>;
 727                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 728                         gpio-controller;
 729                         power-domains = <&pd_gpio>;
 730                 };
 731
 732                 i2c0: i2c@ff020000 {
 733                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 734                         status = "disabled";
 735                         interrupt-parent = <&gic>;
 736                         interrupts = <0 17 4>;
 737                         reg = <0x0 0xff020000 0x0 0x1000>;
 738                         #address-cells = <1>;
 739                         #size-cells = <0>;
 740                         power-domains = <&pd_i2c0>;
 741                 };
 742
 743                 i2c1: i2c@ff030000 {
 744                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 745                         status = "disabled";
 746                         interrupt-parent = <&gic>;
 747                         interrupts = <0 18 4>;
 748                         reg = <0x0 0xff030000 0x0 0x1000>;
 749                         #address-cells = <1>;
 750                         #size-cells = <0>;
 751                         power-domains = <&pd_i2c1>;
 752                 };
 753
 754                 ocm: memory-controller@ff960000 {
 755                         compatible = "xlnx,zynqmp-ocmc-1.0";
 756                         reg = <0x0 0xff960000 0x0 0x1000>;
 757                         interrupt-parent = <&gic>;
 758                         interrupts = <0 10 4>;
 759                 };
 760
 761                 perf_monitor_ocm: perf-monitor@ffa00000 {
 762                         compatible = "xlnx,axi-perf-monitor";
 763                         reg = <0x0 0xffa00000 0x0 0x10000>;
 764                         interrupts = <0 25 4>;
 765                         interrupt-parent = <&gic>;
 766                         xlnx,enable-profile = <0>;
 767                         xlnx,enable-trace = <0>;
 768                         xlnx,num-monitor-slots = <4>;
 769                         xlnx,enable-event-count = <1>;
 770                         xlnx,enable-event-log = <1>;
 771                         xlnx,have-sampled-metric-cnt = <1>;
 772                         xlnx,num-of-counters = <8>;
 773                         xlnx,metric-count-width = <32>;
 774                         xlnx,metrics-sample-count-width = <32>;
 775                         xlnx,global-count-width = <32>;
 776                         xlnx,metric-count-scale = <1>;
 777                 };
 778
 779                 pcie: pcie@fd0e0000 {
 780                         compatible = "xlnx,nwl-pcie-2.11";
 781                         status = "disabled";
 782                         #address-cells = <3>;
 783                         #size-cells = <2>;
 784                         #interrupt-cells = <1>;
 785                         msi-controller;
 786                         device_type = "pci";
 787                         interrupt-parent = <&gic>;
 788                         interrupts = <0 118 4>,
 789                                      <0 117 4>,
 790                                      <0 116 4>,
 791                                      <0 115 4>, /* MSI_1 [63...32] */
 792                                      <0 114 4>; /* MSI_0 [31...0] */
 793                         interrupt-names = "misc", "dummy", "intx",
 794                                           "msi1", "msi0";
 795                         msi-parent = <&pcie>;
 796                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 797                               <0x0 0xfd480000 0x0 0x1000>,
 798                               <0x80 0x00000000 0x0 0x1000000>;
 799                         reg-names = "breg", "pcireg", "cfg";
 800                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 801                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 802                         bus-range = <0x00 0xff>;
 803                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 804                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 805                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 806                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 807                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 808                         power-domains = <&pd_pcie>;
 809                         pcie_intc: legacy-interrupt-controller {
 810                                 interrupt-controller;
 811                                 #address-cells = <0>;
 812                                 #interrupt-cells = <1>;
 813                         };
 814                 };
 815
 816                 qspi: spi@ff0f0000 {
 817                         u-boot,dm-pre-reloc;
 818                         compatible = "xlnx,zynqmp-qspi-1.0";
 819                         status = "disabled";
 820                         clock-names = "ref_clk", "pclk";
 821                         interrupts = <0 15 4>;
 822                         interrupt-parent = <&gic>;
 823                         num-cs = <1>;
 824                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 825                               <0x0 0xc0000000 0x0 0x8000000>;
 826                         #address-cells = <1>;
 827                         #size-cells = <0>;
 828                         #stream-id-cells = <1>;
 829                         iommus = <&smmu 0x873>;
 830                         power-domains = <&pd_qspi>;
 831                 };
 832
 833                 rtc: rtc@ffa60000 {
 834                         compatible = "xlnx,zynqmp-rtc";
 835                         status = "disabled";
 836                         reg = <0x0 0xffa60000 0x0 0x100>;
 837                         interrupt-parent = <&gic>;
 838                         interrupts = <0 26 4>, <0 27 4>;
 839                         interrupt-names = "alarm", "sec";
 840                         calibration = <0x8000>;
 841                 };
 842
 843                 serdes: zynqmp_phy@fd400000 {
 844                         compatible = "xlnx,zynqmp-psgtr-v1.1";
 845                         status = "disabled";
 846                         reg = <0x0 0xfd400000 0x0 0x40000>,
 847                               <0x0 0xfd3d0000 0x0 0x1000>;
 848                         reg-names = "serdes", "siou";
 849                         nvmem-cells = <&soc_revision>;
 850                         nvmem-cell-names = "soc_revision";
 851                         resets = <&rst 16>, <&rst 59>, <&rst 60>,
 852                                  <&rst 61>, <&rst 62>, <&rst 63>,
 853                                  <&rst 64>, <&rst 3>, <&rst 29>,
 854                                  <&rst 30>, <&rst 31>, <&rst 32>;
 855                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 856                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 857                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 858                                       "gem1_rst", "gem2_rst", "gem3_rst";
 859                         lane0: lane0 {
 860                                 #phy-cells = <4>;
 861                         };
 862                         lane1: lane1 {
 863                                 #phy-cells = <4>;
 864                         };
 865                         lane2: lane2 {
 866                                 #phy-cells = <4>;
 867                         };
 868                         lane3: lane3 {
 869                                 #phy-cells = <4>;
 870                         };
 871                 };
 872
 873                 sata: ahci@fd0c0000 {
 874                         compatible = "ceva,ahci-1v84";
 875                         status = "disabled";
 876                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 877                         interrupt-parent = <&gic>;
 878                         interrupts = <0 133 4>;
 879                         power-domains = <&pd_sata>;
 880                         #stream-id-cells = <4>;
 881                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 882                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 883                         /* dma-coherent; */
 884                 };
 885
 886                 sdhci0: sdhci@ff160000 {
 887                         u-boot,dm-pre-reloc;
 888                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 889                         status = "disabled";
 890                         interrupt-parent = <&gic>;
 891                         interrupts = <0 48 4>;
 892                         reg = <0x0 0xff160000 0x0 0x1000>;
 893                         clock-names = "clk_xin", "clk_ahb";
 894                         xlnx,device_id = <0>;
 895                         #stream-id-cells = <1>;
 896                         iommus = <&smmu 0x870>;
 897                         power-domains = <&pd_sd0>;
 898                         nvmem-cells = <&soc_revision>;
 899                         nvmem-cell-names = "soc_revision";
 900                 };
 901
 902                 sdhci1: sdhci@ff170000 {
 903                         u-boot,dm-pre-reloc;
 904                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 905                         status = "disabled";
 906                         interrupt-parent = <&gic>;
 907                         interrupts = <0 49 4>;
 908                         reg = <0x0 0xff170000 0x0 0x1000>;
 909                         clock-names = "clk_xin", "clk_ahb";
 910                         xlnx,device_id = <1>;
 911                         #stream-id-cells = <1>;
 912                         iommus = <&smmu 0x871>;
 913                         power-domains = <&pd_sd1>;
 914                         nvmem-cells = <&soc_revision>;
 915                         nvmem-cell-names = "soc_revision";
 916                 };
 917
 918                 smmu: smmu@fd800000 {
 919                         compatible = "arm,mmu-500";
 920                         reg = <0x0 0xfd800000 0x0 0x20000>;
 921                         #iommu-cells = <1>;
 922                         status = "disabled";
 923                         #global-interrupts = <1>;
 924                         interrupt-parent = <&gic>;
 925                         interrupts = <0 155 4>,
 926                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 927                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 928                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 929                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 930                 };
 931
 932                 spi0: spi@ff040000 {
 933                         compatible = "cdns,spi-r1p6";
 934                         status = "disabled";
 935                         interrupt-parent = <&gic>;
 936                         interrupts = <0 19 4>;
 937                         reg = <0x0 0xff040000 0x0 0x1000>;
 938                         clock-names = "ref_clk", "pclk";
 939                         #address-cells = <1>;
 940                         #size-cells = <0>;
 941                         power-domains = <&pd_spi0>;
 942                 };
 943
 944                 spi1: spi@ff050000 {
 945                         compatible = "cdns,spi-r1p6";
 946                         status = "disabled";
 947                         interrupt-parent = <&gic>;
 948                         interrupts = <0 20 4>;
 949                         reg = <0x0 0xff050000 0x0 0x1000>;
 950                         clock-names = "ref_clk", "pclk";
 951                         #address-cells = <1>;
 952                         #size-cells = <0>;
 953                         power-domains = <&pd_spi1>;
 954                 };
 955
 956                 ttc0: timer@ff110000 {
 957                         compatible = "cdns,ttc";
 958                         status = "disabled";
 959                         interrupt-parent = <&gic>;
 960                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 961                         reg = <0x0 0xff110000 0x0 0x1000>;
 962                         timer-width = <32>;
 963                         power-domains = <&pd_ttc0>;
 964                 };
 965
 966                 ttc1: timer@ff120000 {
 967                         compatible = "cdns,ttc";
 968                         status = "disabled";
 969                         interrupt-parent = <&gic>;
 970                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 971                         reg = <0x0 0xff120000 0x0 0x1000>;
 972                         timer-width = <32>;
 973                         power-domains = <&pd_ttc1>;
 974                 };
 975
 976                 ttc2: timer@ff130000 {
 977                         compatible = "cdns,ttc";
 978                         status = "disabled";
 979                         interrupt-parent = <&gic>;
 980                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 981                         reg = <0x0 0xff130000 0x0 0x1000>;
 982                         timer-width = <32>;
 983                         power-domains = <&pd_ttc2>;
 984                 };
 985
 986                 ttc3: timer@ff140000 {
 987                         compatible = "cdns,ttc";
 988                         status = "disabled";
 989                         interrupt-parent = <&gic>;
 990                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 991                         reg = <0x0 0xff140000 0x0 0x1000>;
 992                         timer-width = <32>;
 993                         power-domains = <&pd_ttc3>;
 994                 };
 995
 996                 uart0: serial@ff000000 {
 997                         u-boot,dm-pre-reloc;
 998                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 999                         status = "disabled";
1000                         interrupt-parent = <&gic>;
1001                         interrupts = <0 21 4>;
1002                         reg = <0x0 0xff000000 0x0 0x1000>;
1003                         clock-names = "uart_clk", "pclk";
1004                         power-domains = <&pd_uart0>;
1005                 };
1006
1007                 uart1: serial@ff010000 {
1008                         u-boot,dm-pre-reloc;
1009                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
1010                         status = "disabled";
1011                         interrupt-parent = <&gic>;
1012                         interrupts = <0 22 4>;
1013                         reg = <0x0 0xff010000 0x0 0x1000>;
1014                         clock-names = "uart_clk", "pclk";
1015                         power-domains = <&pd_uart1>;
1016                 };
1017
1018                 usb0: usb0@ff9d0000 {
1019                         #address-cells = <2>;
1020                         #size-cells = <2>;
1021                         status = "disabled";
1022                         compatible = "xlnx,zynqmp-dwc3";
1023                         reg = <0x0 0xff9d0000 0x0 0x100>;
1024                         clock-names = "bus_clk", "ref_clk";
1025                         power-domains = <&pd_usb0>;
1026                         ranges;
1027                         nvmem-cells = <&soc_revision>;
1028                         nvmem-cell-names = "soc_revision";
1029
1030                         dwc3_0: dwc3@fe200000 {
1031                                 compatible = "snps,dwc3";
1032                                 status = "disabled";
1033                                 reg = <0x0 0xfe200000 0x0 0x40000>;
1034                                 interrupt-parent = <&gic>;
1035                                 interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
1036                                 #stream-id-cells = <1>;
1037                                 iommus = <&smmu 0x860>;
1038                                 snps,quirk-frame-length-adjustment = <0x20>;
1039                                 snps,refclk_fladj;
1040                                 snps,enable_guctl1_resume_quirk;
1041                                 snps,enable_guctl1_ipd_quirk;
1042                                 snps,xhci-stream-quirk;
1043                                 /* dma-coherent; */
1044                                 /* snps,enable-hibernation; */
1045                         };
1046                 };
1047
1048                 usb1: usb1@ff9e0000 {
1049                         #address-cells = <2>;
1050                         #size-cells = <2>;
1051                         status = "disabled";
1052                         compatible = "xlnx,zynqmp-dwc3";
1053                         reg = <0x0 0xff9e0000 0x0 0x100>;
1054                         clock-names = "bus_clk", "ref_clk";
1055                         power-domains = <&pd_usb1>;
1056                         ranges;
1057                         nvmem-cells = <&soc_revision>;
1058                         nvmem-cell-names = "soc_revision";
1059
1060                         dwc3_1: dwc3@fe300000 {
1061                                 compatible = "snps,dwc3";
1062                                 status = "disabled";
1063                                 reg = <0x0 0xfe300000 0x0 0x40000>;
1064                                 interrupt-parent = <&gic>;
1065                                 interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
1066                                 #stream-id-cells = <1>;
1067                                 iommus = <&smmu 0x861>;
1068                                 snps,quirk-frame-length-adjustment = <0x20>;
1069                                 snps,refclk_fladj;
1070                                 snps,enable_guctl1_resume_quirk;
1071                                 snps,enable_guctl1_ipd_quirk;
1072                                 snps,xhci-stream-quirk;
1073                                 /* dma-coherent; */
1074                         };
1075                 };
1076
1077                 watchdog0: watchdog@fd4d0000 {
1078                         compatible = "cdns,wdt-r1p2";
1079                         status = "disabled";
1080                         interrupt-parent = <&gic>;
1081                         interrupts = <0 113 1>;
1082                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
1083                         timeout-sec = <10>;
1084                 };
1085
1086                 xilinx_ams: ams@ffa50000 {
1087                         compatible = "xlnx,zynqmp-ams";
1088                         status = "disabled";
1089                         interrupt-parent = <&gic>;
1090                         interrupts = <0 56 4>;
1091                         interrupt-names = "ams-irq";
1092                         reg = <0x0 0xffa50000 0x0 0x800>;
1093                         reg-names = "ams-base";
1094                         #address-cells = <2>;
1095                         #size-cells = <2>;
1096                         #io-channel-cells = <1>;
1097                         ranges;
1098
1099                         ams_ps: ams_ps@ffa50800 {
1100                                 compatible = "xlnx,zynqmp-ams-ps";
1101                                 status = "disabled";
1102                                 reg = <0x0 0xffa50800 0x0 0x400>;
1103                         };
1104
1105                         ams_pl: ams_pl@ffa50c00 {
1106                                 compatible = "xlnx,zynqmp-ams-pl";
1107                                 status = "disabled";
1108                                 reg = <0x0 0xffa50c00 0x0 0x400>;
1109                         };
1110                 };
1111
1112                 xlnx_dpdma: dma@fd4c0000 {
1113                         compatible = "xlnx,dpdma";
1114                         status = "disabled";
1115                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1116                         interrupts = <0 122 4>;
1117                         interrupt-parent = <&gic>;
1118                         clock-names = "axi_clk";
1119                         power-domains = <&pd_dp>;
1120                         dma-channels = <6>;
1121                         #dma-cells = <1>;
1122                         dma-video0channel {
1123                                 compatible = "xlnx,video0";
1124                         };
1125                         dma-video1channel {
1126                                 compatible = "xlnx,video1";
1127                         };
1128                         dma-video2channel {
1129                                 compatible = "xlnx,video2";
1130                         };
1131                         dma-graphicschannel {
1132                                 compatible = "xlnx,graphics";
1133                         };
1134                         dma-audio0channel {
1135                                 compatible = "xlnx,audio0";
1136                         };
1137                         dma-audio1channel {
1138                                 compatible = "xlnx,audio1";
1139                         };
1140                 };
1141
1142                 zynqmp_dpsub: zynqmp-display@fd4a0000 {
1143                         compatible = "xlnx,zynqmp-dpsub-1.7";
1144                         status = "disabled";
1145                         reg = <0x0 0xfd4a0000 0x0 0x1000>,
1146                               <0x0 0xfd4aa000 0x0 0x1000>,
1147                               <0x0 0xfd4ab000 0x0 0x1000>,
1148                               <0x0 0xfd4ac000 0x0 0x1000>;
1149                         reg-names = "dp", "blend", "av_buf", "aud";
1150                         interrupts = <0 119 4>;
1151                         interrupt-parent = <&gic>;
1152
1153                         clock-names = "dp_apb_clk", "dp_aud_clk",
1154                                       "dp_vtc_pixel_clk_in";
1155
1156                         power-domains = <&pd_dp>;
1157
1158                         vid-layer {
1159                                 dma-names = "vid0", "vid1", "vid2";
1160                                 dmas = <&xlnx_dpdma 0>,
1161                                        <&xlnx_dpdma 1>,
1162                                        <&xlnx_dpdma 2>;
1163                         };
1164
1165                         gfx-layer {
1166                                 dma-names = "gfx0";
1167                                 dmas = <&xlnx_dpdma 3>;
1168                         };
1169
1170                         /* dummy node to indicate there's no child i2c device */
1171                         i2c-bus {
1172                         };
1173
1174                         zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
1175                                 compatible = "xlnx,dp-snd-codec";
1176                                 clock-names = "aud_clk";
1177                         };
1178
1179                         zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
1180                                 compatible = "xlnx,dp-snd-pcm";
1181                                 dmas = <&xlnx_dpdma 4>;
1182                                 dma-names = "tx";
1183                         };
1184
1185                         zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
1186                                 compatible = "xlnx,dp-snd-pcm";
1187                                 dmas = <&xlnx_dpdma 5>;
1188                                 dma-names = "tx";
1189                         };
1190
1191                         zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
1192                                 compatible = "xlnx,dp-snd-card";
1193                                 xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
1194                                                   <&zynqmp_dp_snd_pcm1>;
1195                                 xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
1196                         };
1197                 };
1198         };
1199 };