arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Clock specification for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 / {
  11         clk100: clk100 {
  12                 compatible = "fixed-clock";
  13                 #clock-cells = <0>;
  14                 clock-frequency = <100000000>;
  15                 u-boot,dm-pre-reloc;
  16         };
  17
  18         clk125: clk125 {
  19                 compatible = "fixed-clock";
  20                 #clock-cells = <0>;
  21                 clock-frequency = <125000000>;
  22         };
  23
  24         clk200: clk200 {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <200000000>;
  28         };
  29
  30         clk250: clk250 {
  31                 compatible = "fixed-clock";
  32                 #clock-cells = <0>;
  33                 clock-frequency = <250000000>;
  34         };
  35
  36         clk300: clk300 {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 clock-frequency = <300000000>;
  40         };
  41
  42         clk600: clk600 {
  43                 compatible = "fixed-clock";
  44                 #clock-cells = <0>;
  45                 clock-frequency = <600000000>;
  46         };
  47
  48         dp_aclk: clock0 {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <100000000>;
  52                 clock-accuracy = <100>;
  53         };
  54
  55         dp_aud_clk: clock1 {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <24576000>;
  59                 clock-accuracy = <100>;
  60         };
  61
  62         dpdma_clk: dpdma_clk {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0x0>;
  65                 clock-frequency = <533000000>;
  66         };
  67
  68         drm_clock: drm_clock {
  69                 compatible = "fixed-clock";
  70                 #clock-cells = <0x0>;
  71                 clock-frequency = <262750000>;
  72                 clock-accuracy = <0x64>;
  73         };
  74 };
  75
  76 &can0 {
  77         clocks = <&clk100 &clk100>;
  78 };
  79
  80 &can1 {
  81         clocks = <&clk100 &clk100>;
  82 };
  83
  84 &fpd_dma_chan1 {
  85         clocks = <&clk600>, <&clk100>;
  86 };
  87
  88 &fpd_dma_chan2 {
  89         clocks = <&clk600>, <&clk100>;
  90 };
  91
  92 &fpd_dma_chan3 {
  93         clocks = <&clk600>, <&clk100>;
  94 };
  95
  96 &fpd_dma_chan4 {
  97         clocks = <&clk600>, <&clk100>;
  98 };
  99
 100 &fpd_dma_chan5 {
 101         clocks = <&clk600>, <&clk100>;
 102 };
 103
 104 &fpd_dma_chan6 {
 105         clocks = <&clk600>, <&clk100>;
 106 };
 107
 108 &fpd_dma_chan7 {
 109         clocks = <&clk600>, <&clk100>;
 110 };
 111
 112 &fpd_dma_chan8 {
 113         clocks = <&clk600>, <&clk100>;
 114 };
 115
 116 &lpd_dma_chan1 {
 117         clocks = <&clk600>, <&clk100>;
 118 };
 119
 120 &lpd_dma_chan2 {
 121         clocks = <&clk600>, <&clk100>;
 122 };
 123
 124 &lpd_dma_chan3 {
 125         clocks = <&clk600>, <&clk100>;
 126 };
 127
 128 &lpd_dma_chan4 {
 129         clocks = <&clk600>, <&clk100>;
 130 };
 131
 132 &lpd_dma_chan5 {
 133         clocks = <&clk600>, <&clk100>;
 134 };
 135
 136 &lpd_dma_chan6 {
 137         clocks = <&clk600>, <&clk100>;
 138 };
 139
 140 &lpd_dma_chan7 {
 141         clocks = <&clk600>, <&clk100>;
 142 };
 143
 144 &lpd_dma_chan8 {
 145         clocks = <&clk600>, <&clk100>;
 146 };
 147
 148 &nand0 {
 149         clocks = <&clk100 &clk100>;
 150 };
 151
 152 &gem0 {
 153         clocks = <&clk125>, <&clk125>, <&clk125>;
 154 };
 155
 156 &gem1 {
 157         clocks = <&clk125>, <&clk125>, <&clk125>;
 158 };
 159
 160 &gem2 {
 161         clocks = <&clk125>, <&clk125>, <&clk125>;
 162 };
 163
 164 &gem3 {
 165         clocks = <&clk125>, <&clk125>, <&clk125>;
 166 };
 167
 168 &gpio {
 169         clocks = <&clk100>;
 170 };
 171
 172 &i2c0 {
 173         clocks = <&clk100>;
 174 };
 175
 176 &i2c1 {
 177         clocks = <&clk100>;
 178 };
 179
 180 &perf_monitor_ocm {
 181         clocks = <&clk100>;
 182 };
 183
 184 &qspi {
 185         clocks = <&clk300 &clk300>;
 186 };
 187
 188 &sata {
 189         clocks = <&clk250>;
 190 };
 191
 192 &sdhci0 {
 193         clocks = <&clk200 &clk200>;
 194 };
 195
 196 &sdhci1 {
 197         clocks = <&clk200 &clk200>;
 198 };
 199
 200 &spi0 {
 201         clocks = <&clk200 &clk200>;
 202 };
 203
 204 &spi1 {
 205         clocks = <&clk200 &clk200>;
 206 };
 207
 208 &uart0 {
 209         clocks = <&clk100 &clk100>;
 210 };
 211
 212 &uart1 {
 213         clocks = <&clk100 &clk100>;
 214 };
 215
 216 &usb0 {
 217         clocks = <&clk250>, <&clk250>;
 218 };
 219
 220 &usb1 {
 221         clocks = <&clk250>, <&clk250>;
 222 };
 223
 224 &watchdog0 {
 225         clocks = <&clk250>;
 226 };
 227
 228 &zynqmp_dpsub {
 229         clocks = <&dp_aclk>, <&dp_aud_clk>, <&drm_clock>;
 230 };
 231
 232 &xlnx_dpdma {
 233         clocks = <&dpdma_clk>;
 234 };
 235
 236 &zynqmp_dp_snd_codec0 {
 237         clocks = <&dp_aud_clk>;
 238 };