drivers/spi/spi-zynqmp-gqspi.c

   1 /*
   2  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
   3  * (master mode only)
   4  *
   5  * Copyright (C) 2009 - 2015 Xilinx, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_address.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/workqueue.h>
  26 #include <linux/soc/xilinx/zynqmp/pm.h>
  27
  28 /* Generic QSPI register offsets */
  29 #define GQSPI_CONFIG_OFST               0x00000100
  30 #define GQSPI_ISR_OFST                  0x00000104
  31 #define GQSPI_IDR_OFST                  0x0000010C
  32 #define GQSPI_IER_OFST                  0x00000108
  33 #define GQSPI_IMASK_OFST                0x00000110
  34 #define GQSPI_EN_OFST                   0x00000114
  35 #define GQSPI_TXD_OFST                  0x0000011C
  36 #define GQSPI_RXD_OFST                  0x00000120
  37 #define GQSPI_TX_THRESHOLD_OFST         0x00000128
  38 #define GQSPI_RX_THRESHOLD_OFST         0x0000012C
  39 #define GQSPI_LPBK_DLY_ADJ_OFST         0x00000138
  40 #define GQSPI_GEN_FIFO_OFST             0x00000140
  41 #define GQSPI_SEL_OFST                  0x00000144
  42 #define GQSPI_GF_THRESHOLD_OFST         0x00000150
  43 #define GQSPI_FIFO_CTRL_OFST            0x0000014C
  44 #define GQSPI_QSPIDMA_DST_CTRL_OFST     0x0000080C
  45 #define GQSPI_QSPIDMA_DST_SIZE_OFST     0x00000804
  46 #define GQSPI_QSPIDMA_DST_STS_OFST      0x00000808
  47 #define GQSPI_QSPIDMA_DST_I_STS_OFST    0x00000814
  48 #define GQSPI_QSPIDMA_DST_I_EN_OFST     0x00000818
  49 #define GQSPI_QSPIDMA_DST_I_DIS_OFST    0x0000081C
  50 #define GQSPI_QSPIDMA_DST_I_MASK_OFST   0x00000820
  51 #define GQSPI_QSPIDMA_DST_ADDR_OFST     0x00000800
  52 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
  53 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
  54 #define IOU_TAPDLY_BYPASS_OFST          0xFF180390
  55
  56 /* GQSPI register bit masks */
  57 #define GQSPI_SEL_MASK                          0x00000001
  58 #define GQSPI_EN_MASK                           0x00000001
  59 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK        0x00000020
  60 #define GQSPI_ISR_WR_TO_CLR_MASK                0x00000002
  61 #define GQSPI_IDR_ALL_MASK                      0x00000FBE
  62 #define GQSPI_CFG_MODE_EN_MASK                  0xC0000000
  63 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK      0x20000000
  64 #define GQSPI_CFG_ENDIAN_MASK                   0x04000000
  65 #define GQSPI_CFG_EN_POLL_TO_MASK               0x00100000
  66 #define GQSPI_CFG_WP_HOLD_MASK                  0x00080000
  67 #define GQSPI_CFG_BAUD_RATE_DIV_MASK            0x00000038
  68 #define GQSPI_CFG_CLK_PHA_MASK                  0x00000004
  69 #define GQSPI_CFG_CLK_POL_MASK                  0x00000002
  70 #define GQSPI_CFG_START_GEN_FIFO_MASK           0x10000000
  71 #define GQSPI_GENFIFO_IMM_DATA_MASK             0x000000FF
  72 #define GQSPI_GENFIFO_DATA_XFER                 0x00000100
  73 #define GQSPI_GENFIFO_EXP                       0x00000200
  74 #define GQSPI_GENFIFO_MODE_SPI                  0x00000400
  75 #define GQSPI_GENFIFO_MODE_DUALSPI              0x00000800
  76 #define GQSPI_GENFIFO_MODE_QUADSPI              0x00000C00
  77 #define GQSPI_GENFIFO_MODE_MASK                 0x00000C00
  78 #define GQSPI_GENFIFO_CS_LOWER                  0x00001000
  79 #define GQSPI_GENFIFO_CS_UPPER                  0x00002000
  80 #define GQSPI_GENFIFO_BUS_LOWER                 0x00004000
  81 #define GQSPI_GENFIFO_BUS_UPPER                 0x00008000
  82 #define GQSPI_GENFIFO_BUS_BOTH                  0x0000C000
  83 #define GQSPI_GENFIFO_BUS_MASK                  0x0000C000
  84 #define GQSPI_GENFIFO_TX                        0x00010000
  85 #define GQSPI_GENFIFO_RX                        0x00020000
  86 #define GQSPI_GENFIFO_STRIPE                    0x00040000
  87 #define GQSPI_GENFIFO_POLL                      0x00080000
  88 #define GQSPI_GENFIFO_EXP_START                 0x00000100
  89 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK        0x00000004
  90 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK        0x00000002
  91 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK       0x00000001
  92 #define GQSPI_ISR_RXEMPTY_MASK                  0x00000800
  93 #define GQSPI_ISR_GENFIFOFULL_MASK              0x00000400
  94 #define GQSPI_ISR_GENFIFONOT_FULL_MASK          0x00000200
  95 #define GQSPI_ISR_TXEMPTY_MASK                  0x00000100
  96 #define GQSPI_ISR_GENFIFOEMPTY_MASK             0x00000080
  97 #define GQSPI_ISR_RXFULL_MASK                   0x00000020
  98 #define GQSPI_ISR_RXNEMPTY_MASK                 0x00000010
  99 #define GQSPI_ISR_TXFULL_MASK                   0x00000008
 100 #define GQSPI_ISR_TXNOT_FULL_MASK               0x00000004
 101 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK         0x00000002
 102 #define GQSPI_IER_TXNOT_FULL_MASK               0x00000004
 103 #define GQSPI_IER_RXEMPTY_MASK                  0x00000800
 104 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK         0x00000002
 105 #define GQSPI_IER_RXNEMPTY_MASK                 0x00000010
 106 #define GQSPI_IER_GENFIFOEMPTY_MASK             0x00000080
 107 #define GQSPI_IER_TXEMPTY_MASK                  0x00000100
 108 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK         0x000000FE
 109 #define GQSPI_QSPIDMA_DST_STS_WTC               0x0000E000
 110 #define GQSPI_CFG_MODE_EN_DMA_MASK              0x80000000
 111 #define GQSPI_ISR_IDR_MASK                      0x00000994
 112 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK        0x00000002
 113 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK       0x00000002
 114 #define GQSPI_IRQ_MASK                          0x00000980
 115
 116 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT           3
 117 #define GQSPI_GENFIFO_CS_SETUP                  0x4
 118 #define GQSPI_GENFIFO_CS_HOLD                   0x3
 119 #define GQSPI_TXD_DEPTH                         64
 120 #define GQSPI_RX_FIFO_THRESHOLD                 32
 121 #define GQSPI_RX_FIFO_FILL      (GQSPI_RX_FIFO_THRESHOLD * 4)
 122 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL       32
 123 #define GQSPI_TX_FIFO_FILL      (GQSPI_TXD_DEPTH -\
 124                                 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
 125 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL      0X10
 126 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL        0x803FFA00
 127 #define GQSPI_SELECT_FLASH_CS_LOWER             0x1
 128 #define GQSPI_SELECT_FLASH_CS_UPPER             0x2
 129 #define GQSPI_SELECT_FLASH_CS_BOTH              0x3
 130 #define GQSPI_SELECT_FLASH_BUS_LOWER            0x1
 131 #define GQSPI_SELECT_FLASH_BUS_UPPER            0x2
 132 #define GQSPI_SELECT_FLASH_BUS_BOTH             0x3
 133 #define GQSPI_BAUD_DIV_MAX      7       /* Baud rate divisor maximum */
 134 #define GQSPI_BAUD_DIV_SHIFT    2       /* Baud rate divisor shift */
 135 #define GQSPI_SELECT_MODE_SPI           0x1
 136 #define GQSPI_SELECT_MODE_DUALSPI       0x2
 137 #define GQSPI_SELECT_MODE_QUADSPI       0x4
 138 #define GQSPI_DMA_UNALIGN               0x3
 139 #define GQSPI_DEFAULT_NUM_CS    1       /* Default number of chip selects */
 140 #define GQSPI_RX_BUS_WIDTH_QUAD         0x4
 141 #define GQSPI_RX_BUS_WIDTH_DUAL         0x2
 142 #define GQSPI_RX_BUS_WIDTH_SINGLE       0x1
 143 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
 144 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
 145 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
 146 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
 147 #define GQSPI_USE_DATA_DLY              0x1
 148 #define GQSPI_USE_DATA_DLY_SHIFT        31
 149 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
 150 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
 151 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
 152 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
 153
 154 #define GQSPI_FREQ_40MHZ        40000000
 155 #define GQSPI_FREQ_100MHZ       100000000
 156 #define GQSPI_FREQ_150MHZ       150000000
 157 #define IOU_TAPDLY_BYPASS_MASK  0x7
 158
 159 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
 160
 161 /**
 162  * struct zynqmp_qspi - Defines qspi driver instance
 163  * @regs:               Virtual address of the QSPI controller registers
 164  * @refclk:             Pointer to the peripheral clock
 165  * @pclk:               Pointer to the APB clock
 166  * @irq:                IRQ number
 167  * @dev:                Pointer to struct device
 168  * @txbuf:              Pointer to the TX buffer
 169  * @rxbuf:              Pointer to the RX buffer
 170  * @bytes_to_transfer:  Number of bytes left to transfer
 171  * @bytes_to_receive:   Number of bytes left to receive
 172  * @genfifocs:          Used for chip select
 173  * @genfifobus:         Used to select the upper or lower bus
 174  * @dma_rx_bytes:       Remaining bytes to receive by DMA mode
 175  * @dma_addr:           DMA address after mapping the kernel buffer
 176  * @genfifoentry:       Used for storing the genfifoentry instruction.
 177  * @isinstr:            To determine whether the transfer is instruction
 178  * @mode:               Defines the mode in which QSPI is operating
 179  * @speed_hz:           Current SPI bus clock speed in hz
 180  */
 181 struct zynqmp_qspi {
 182         void __iomem *regs;
 183         struct clk *refclk;
 184         struct clk *pclk;
 185         int irq;
 186         struct device *dev;
 187         const void *txbuf;
 188         void *rxbuf;
 189         int bytes_to_transfer;
 190         int bytes_to_receive;
 191         u32 genfifocs;
 192         u32 genfifobus;
 193         u32 dma_rx_bytes;
 194         dma_addr_t dma_addr;
 195         u32 rx_bus_width;
 196         u32 genfifoentry;
 197         bool isinstr;
 198         enum mode_type mode;
 199         u32 speed_hz;
 200 };
 201
 202 /**
 203  * zynqmp_gqspi_read:   For GQSPI controller read operation
 204  * @xqspi:      Pointer to the zynqmp_qspi structure
 205  * @offset:     Offset from where to read
 206  */
 207 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
 208 {
 209         return readl_relaxed(xqspi->regs + offset);
 210 }
 211
 212 /**
 213  * zynqmp_gqspi_write:  For GQSPI controller write operation
 214  * @xqspi:      Pointer to the zynqmp_qspi structure
 215  * @offset:     Offset where to write
 216  * @val:        Value to be written
 217  */
 218 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
 219                                       u32 val)
 220 {
 221         writel_relaxed(val, (xqspi->regs + offset));
 222 }
 223
 224 /**
 225  * zynqmp_gqspi_selectslave:    For selection of slave device
 226  * @instanceptr:        Pointer to the zynqmp_qspi structure
 227  * @flashcs:    For chip select
 228  * @flashbus:   To check which bus is selected- upper or lower
 229  */
 230 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
 231                                      u8 slavecs, u8 slavebus)
 232 {
 233         /*
 234          * Bus and CS lines selected here will be updated in the instance and
 235          * used for subsequent GENFIFO entries during transfer.
 236          */
 237
 238         /* Choose slave select line */
 239         switch (slavecs) {
 240         case GQSPI_SELECT_FLASH_CS_BOTH:
 241                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
 242                         GQSPI_GENFIFO_CS_UPPER;
 243                 break;
 244         case GQSPI_SELECT_FLASH_CS_UPPER:
 245                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
 246                 break;
 247         case GQSPI_SELECT_FLASH_CS_LOWER:
 248                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 249                 break;
 250         default:
 251                 dev_warn(instanceptr->dev, "Invalid slave select\n");
 252         }
 253
 254         /* Choose the bus */
 255         switch (slavebus) {
 256         case GQSPI_SELECT_FLASH_BUS_BOTH:
 257                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
 258                         GQSPI_GENFIFO_BUS_UPPER;
 259                 break;
 260         case GQSPI_SELECT_FLASH_BUS_UPPER:
 261                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
 262                 break;
 263         case GQSPI_SELECT_FLASH_BUS_LOWER:
 264                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 265                 break;
 266         default:
 267                 dev_warn(instanceptr->dev, "Invalid slave bus\n");
 268         }
 269 }
 270
 271 /**
 272  * zynqmp_qspi_set_tapdelay:    To configure qspi tap delays
 273  * @xqspi:              Pointer to the zynqmp_qspi structure
 274  * @baudrateval:        Buadrate to configure
 275  */
 276 void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
 277 {
 278         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 279         u32 reqhz = 0;
 280
 281         clk_rate = clk_get_rate(xqspi->refclk);
 282         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 283
 284         if (reqhz < GQSPI_FREQ_40MHZ) {
 285                 zynqmp_pm_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 286                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 287                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 288         } else if (reqhz < GQSPI_FREQ_100MHZ) {
 289                 zynqmp_pm_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 290                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 291                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 292                 lpbkdlyadj = zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST);
 293                 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 294                 datadlyadj = zynqmp_gqspi_read(xqspi, GQSPI_DATA_DLY_ADJ_OFST);
 295                 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 296                                 | (GQSPI_DATA_DLY_ADJ_VALUE <<
 297                                         GQSPI_DATA_DLY_ADJ_SHIFT));
 298         } else if (reqhz < GQSPI_FREQ_150MHZ) {
 299                 lpbkdlyadj = zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST);
 300                 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK) |
 301                                 GQSPI_LPBK_DLY_ADJ_DLY_0);
 302         }
 303
 304         zynqmp_pm_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
 305                         tapdlybypass);
 306         zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);
 307         zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);
 308 }
 309
 310 /**
 311  * zynqmp_qspi_init_hw: Initialize the hardware
 312  * @xqspi:      Pointer to the zynqmp_qspi structure
 313  *
 314  * The default settings of the QSPI controller's configurable parameters on
 315  * reset are
 316  *      - Master mode
 317  *      - TX threshold set to 1
 318  *      - RX threshold set to 1
 319  *      - Flash memory interface mode enabled
 320  * This function performs the following actions
 321  *      - Disable and clear all the interrupts
 322  *      - Enable manual slave select
 323  *      - Enable manual start
 324  *      - Deselect all the chip select lines
 325  *      - Set the little endian mode of TX FIFO and
 326  *      - Enable the QSPI controller
 327  */
 328 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 329 {
 330         u32 config_reg;
 331
 332         /* Select the GQSPI mode */
 333         zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
 334         /* Clear and disable interrupts */
 335         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
 336                            zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
 337                            GQSPI_ISR_WR_TO_CLR_MASK);
 338         /* Clear the DMA STS */
 339         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 340                            zynqmp_gqspi_read(xqspi,
 341                                              GQSPI_QSPIDMA_DST_I_STS_OFST));
 342         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
 343                            zynqmp_gqspi_read(xqspi,
 344                                              GQSPI_QSPIDMA_DST_STS_OFST) |
 345                                              GQSPI_QSPIDMA_DST_STS_WTC);
 346         zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
 347         zynqmp_gqspi_write(xqspi,
 348                            GQSPI_QSPIDMA_DST_I_DIS_OFST,
 349                            GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
 350         /* Disable the GQSPI */
 351         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 352         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 353         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 354         /* Manual start */
 355         config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
 356         /* Little endian by default */
 357         config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
 358         /* Disable poll time out */
 359         config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
 360         /* Set hold bit */
 361         config_reg |= GQSPI_CFG_WP_HOLD_MASK;
 362         /* Clear pre-scalar by default */
 363         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 364         /* CPHA 0 */
 365         config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
 366         /* CPOL 0 */
 367         config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
 368         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 369
 370         /* Clear the TX and RX FIFO */
 371         zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
 372                            GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
 373                            GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
 374                            GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
 375         /* Set by default to allow for high frequencies */
 376         zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
 377                            zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
 378                            GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 379         /* Reset thresholds */
 380         zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
 381                            GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
 382         zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
 383                            GQSPI_RX_FIFO_THRESHOLD);
 384         zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
 385                            GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
 386         zynqmp_gqspi_selectslave(xqspi,
 387                                  GQSPI_SELECT_FLASH_CS_LOWER,
 388                                  GQSPI_SELECT_FLASH_BUS_LOWER);
 389         /* Initialize DMA */
 390         zynqmp_gqspi_write(xqspi,
 391                         GQSPI_QSPIDMA_DST_CTRL_OFST,
 392                         GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
 393
 394         /* Enable the GQSPI */
 395         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 396 }
 397
 398 /**
 399  * zynqmp_qspi_copy_read_data:  Copy data to RX buffer
 400  * @xqspi:      Pointer to the zynqmp_qspi structure
 401  * @data:       The variable where data is stored
 402  * @size:       Number of bytes to be copied from data to RX buffer
 403  */
 404 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
 405                                        ulong data, u8 size)
 406 {
 407         memcpy(xqspi->rxbuf, &data, size);
 408         xqspi->rxbuf += size;
 409         xqspi->bytes_to_receive -= size;
 410 }
 411
 412 /**
 413  * zynqmp_prepare_transfer_hardware:    Prepares hardware for transfer.
 414  * @master:     Pointer to the spi_master structure which provides
 415  *              information about the controller.
 416  *
 417  * This function enables SPI master controller.
 418  *
 419  * Return:      0 on success; error value otherwise
 420  */
 421 static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
 422 {
 423         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 424         int ret;
 425
 426         ret = clk_enable(xqspi->refclk);
 427         if (ret)
 428                 return ret;
 429
 430         ret = clk_enable(xqspi->pclk);
 431         if (ret)
 432                 goto clk_err;
 433
 434         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 435         return 0;
 436 clk_err:
 437         clk_disable(xqspi->refclk);
 438         return ret;
 439 }
 440
 441 /**
 442  * zynqmp_unprepare_transfer_hardware:  Relaxes hardware after transfer
 443  * @master:     Pointer to the spi_master structure which provides
 444  *              information about the controller.
 445  *
 446  * This function disables the SPI master controller.
 447  *
 448  * Return:      Always 0
 449  */
 450 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
 451 {
 452         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 453
 454         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 455         clk_disable(xqspi->refclk);
 456         clk_disable(xqspi->pclk);
 457         return 0;
 458 }
 459
 460 /**
 461  * zynqmp_qspi_chipselect:      Select or deselect the chip select line
 462  * @qspi:       Pointer to the spi_device structure
 463  * @is_high:    Select(0) or deselect (1) the chip select line
 464  */
 465 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
 466 {
 467         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 468         ulong timeout;
 469         u32 genfifoentry = 0x0, statusreg;
 470
 471         genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 472
 473         if (qspi->master->flags & SPI_MASTER_BOTH_CS) {
 474                 zynqmp_gqspi_selectslave(xqspi,
 475                         GQSPI_SELECT_FLASH_CS_BOTH,
 476                         GQSPI_SELECT_FLASH_BUS_BOTH);
 477         } else if (qspi->master->flags & SPI_MASTER_U_PAGE) {
 478                 zynqmp_gqspi_selectslave(xqspi,
 479                         GQSPI_SELECT_FLASH_CS_UPPER,
 480                         GQSPI_SELECT_FLASH_BUS_LOWER);
 481         } else {
 482                 zynqmp_gqspi_selectslave(xqspi,
 483                         GQSPI_SELECT_FLASH_CS_LOWER,
 484                         GQSPI_SELECT_FLASH_BUS_LOWER);
 485         }
 486
 487         genfifoentry |= xqspi->genfifobus;
 488
 489         if (!is_high) {
 490                 genfifoentry |= xqspi->genfifocs;
 491                 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
 492                 xqspi->isinstr = true;
 493         } else {
 494                 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
 495         }
 496
 497         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 498
 499         /* Dummy generic FIFO entry */
 500         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 501
 502         /* Manually start the generic FIFO command */
 503         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 504                         zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 505                         GQSPI_CFG_START_GEN_FIFO_MASK);
 506
 507         timeout = jiffies + msecs_to_jiffies(1000);
 508
 509         /* Wait until the generic FIFO command is empty */
 510         do {
 511                 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 512
 513                 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
 514                         (statusreg & GQSPI_ISR_TXEMPTY_MASK))
 515                         break;
 516                 else
 517                         cpu_relax();
 518         } while (!time_after_eq(jiffies, timeout));
 519
 520         if (time_after_eq(jiffies, timeout))
 521                 dev_err(xqspi->dev, "Chip select timed out\n");
 522 }
 523
 524 /**
 525  * zynqmp_qspi_setup_transfer:  Configure QSPI controller for specified
 526  *                              transfer
 527  * @qspi:       Pointer to the spi_device structure
 528  * @transfer:   Pointer to the spi_transfer structure which provides
 529  *              information about next transfer setup parameters
 530  *
 531  * Sets the operational mode of QSPI controller for the next QSPI transfer and
 532  * sets the requested clock frequency.
 533  *
 534  * Return:      Always 0
 535  *
 536  * Note:
 537  *      If the requested frequency is not an exact match with what can be
 538  *      obtained using the pre-scalar value, the driver sets the clock
 539  *      frequency which is lower than the requested frequency (maximum lower)
 540  *      for the transfer.
 541  *
 542  *      If the requested frequency is higher or lower than that is supported
 543  *      by the QSPI controller the driver will set the highest or lowest
 544  *      frequency supported by controller.
 545  */
 546 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
 547                                       struct spi_transfer *transfer)
 548 {
 549         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 550         ulong clk_rate;
 551         u32 config_reg, req_hz, baud_rate_val = 0;
 552
 553         if (transfer)
 554                 req_hz = transfer->speed_hz;
 555         else
 556                 req_hz = qspi->max_speed_hz;
 557
 558         if (xqspi->speed_hz != req_hz) {
 559                 /* Set the clock frequency */
 560                 /* If req_hz == 0, default to lowest speed */
 561                 clk_rate = clk_get_rate(xqspi->refclk);
 562
 563                 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
 564                        (clk_rate /
 565                         (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
 566                         baud_rate_val++;
 567
 568                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 569
 570                 /* Set the QSPI clock phase and clock polarity */
 571                 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) &
 572                         (~GQSPI_CFG_CLK_POL_MASK);
 573
 574                 if (qspi->mode & SPI_CPHA)
 575                         config_reg |= GQSPI_CFG_CLK_PHA_MASK;
 576                 if (qspi->mode & SPI_CPOL)
 577                         config_reg |= GQSPI_CFG_CLK_POL_MASK;
 578                 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 579                 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
 580                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 581                 xqspi->speed_hz = clk_rate / (GQSPI_BAUD_DIV_SHIFT <<
 582                                 baud_rate_val);
 583                 zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
 584         }
 585
 586         return 0;
 587 }
 588
 589 /**
 590  * zynqmp_qspi_setup:   Configure the QSPI controller
 591  * @qspi:       Pointer to the spi_device structure
 592  *
 593  * Sets the operational mode of QSPI controller for the next QSPI transfer,
 594  * baud rate and divisor value to setup the requested qspi clock.
 595  *
 596  * Return:      0 on success; error value otherwise.
 597  */
 598 static int zynqmp_qspi_setup(struct spi_device *qspi)
 599 {
 600         if (qspi->master->busy)
 601                 return -EBUSY;
 602         return 0;
 603 }
 604
 605 /**
 606  * zynqmp_qspi_filltxfifo:      Fills the TX FIFO as long as there is room in
 607  *                              the FIFO or the bytes required to be
 608  *                              transmitted.
 609  * @xqspi:      Pointer to the zynqmp_qspi structure
 610  * @size:       Number of bytes to be copied from TX buffer to TX FIFO
 611  */
 612 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
 613 {
 614         u32 count = 0, intermediate;
 615
 616         while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
 617                 memcpy(&intermediate, xqspi->txbuf, 4);
 618                 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
 619
 620                 if (xqspi->bytes_to_transfer >= 4) {
 621                         xqspi->txbuf += 4;
 622                         xqspi->bytes_to_transfer -= 4;
 623                 } else {
 624                         xqspi->txbuf += xqspi->bytes_to_transfer;
 625                         xqspi->bytes_to_transfer = 0;
 626                 }
 627                 count++;
 628         }
 629 }
 630
 631 /**
 632  * zynqmp_qspi_readrxfifo:      Fills the RX FIFO as long as there is room in
 633  *                              the FIFO.
 634  * @xqspi:      Pointer to the zynqmp_qspi structure
 635  * @size:       Number of bytes to be copied from RX buffer to RX FIFO
 636  */
 637 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
 638 {
 639         ulong data;
 640         int count = 0;
 641
 642         while ((count < size) && (xqspi->bytes_to_receive > 0)) {
 643                 if (xqspi->bytes_to_receive >= 4) {
 644                         (*(u32 *) xqspi->rxbuf) =
 645                                 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 646                         xqspi->rxbuf += 4;
 647                         xqspi->bytes_to_receive -= 4;
 648                         count += 4;
 649                 } else {
 650                         data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 651                         count += xqspi->bytes_to_receive;
 652                         zynqmp_qspi_copy_read_data(xqspi, data,
 653                                                    xqspi->bytes_to_receive);
 654                         xqspi->bytes_to_receive = 0;
 655                 }
 656         }
 657 }
 658
 659 /**
 660  * zynqmp_qspi_preparedummy:    Prepares the dummy entry
 661  *
 662  * @xqspi:      Pointer to the zynqmp_qspi structure
 663  * @transfer:   It is a pointer to the structure containing transfer data.
 664  * @genfifoentry:       genfifoentry is pointer to the variable in which
 665  *                      GENFIFO mask is returned to calling function
 666  */
 667 static void zynqmp_qspi_preparedummy(struct zynqmp_qspi *xqspi,
 668                                         struct spi_transfer *transfer,
 669                                         u32 *genfifoentry)
 670 {
 671         /* For dummy Tx and Rx are NULL */
 672         *genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
 673
 674         /* SPI mode */
 675         *genfifoentry &= ~GQSPI_GENFIFO_MODE_QUADSPI;
 676         if (xqspi->rx_bus_width == GQSPI_RX_BUS_WIDTH_QUAD)
 677                 *genfifoentry |= GQSPI_GENFIFO_MODE_QUADSPI;
 678         else if (xqspi->rx_bus_width == GQSPI_RX_BUS_WIDTH_DUAL)
 679                 *genfifoentry |= GQSPI_GENFIFO_MODE_DUALSPI;
 680         else
 681                 *genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 682
 683         /* Immediate data */
 684         *genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 685         *genfifoentry |= transfer->dummy;
 686 }
 687
 688 /**
 689  * zynqmp_process_dma_irq:      Handler for DMA done interrupt of QSPI
 690  *                              controller
 691  * @xqspi:      zynqmp_qspi instance pointer
 692  *
 693  * This function handles DMA interrupt only.
 694  */
 695 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
 696 {
 697         u32 config_reg, genfifoentry;
 698
 699         dma_unmap_single(xqspi->dev, xqspi->dma_addr,
 700                                 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
 701         xqspi->rxbuf += xqspi->dma_rx_bytes;
 702         xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
 703         xqspi->dma_rx_bytes = 0;
 704
 705         /* Disabling the DMA interrupts */
 706         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
 707                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 708
 709         if (xqspi->bytes_to_receive > 0) {
 710                 /* Switch to IO mode,for remaining bytes to receive */
 711                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 712                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 713                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 714
 715                 /* Initiate the transfer of remaining bytes */
 716                 genfifoentry = xqspi->genfifoentry;
 717                 genfifoentry |= xqspi->bytes_to_receive;
 718                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 719
 720                 /* Dummy generic FIFO entry */
 721                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 722
 723                 /* Manual start */
 724                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 725                         (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 726                         GQSPI_CFG_START_GEN_FIFO_MASK));
 727
 728                 /* Enable the RX interrupts for IO mode */
 729                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 730                                 GQSPI_IER_GENFIFOEMPTY_MASK |
 731                                 GQSPI_IER_RXNEMPTY_MASK |
 732                                 GQSPI_IER_RXEMPTY_MASK);
 733         }
 734 }
 735
 736 /**
 737  * zynqmp_qspi_irq:     Interrupt service routine of the QSPI controller
 738  * @irq:        IRQ number
 739  * @dev_id:     Pointer to the xqspi structure
 740  *
 741  * This function handles TX empty only.
 742  * On TX empty interrupt this function reads the received data from RX FIFO
 743  * and fills the TX FIFO if there is any data remaining to be transferred.
 744  *
 745  * Return:      IRQ_HANDLED when interrupt is handled
 746  *              IRQ_NONE otherwise.
 747  */
 748 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
 749 {
 750         struct spi_master *master = dev_id;
 751         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 752         int ret = IRQ_NONE;
 753         u32 status, mask, dma_status = 0;
 754
 755         status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 756         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
 757         mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
 758
 759         /* Read and clear DMA status */
 760         if (xqspi->mode == GQSPI_MODE_DMA) {
 761                 dma_status =
 762                         zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
 763                 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 764                                                                 dma_status);
 765         }
 766
 767         if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
 768                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
 769                 ret = IRQ_HANDLED;
 770         }
 771
 772         if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
 773                 zynqmp_process_dma_irq(xqspi);
 774                 ret = IRQ_HANDLED;
 775         } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
 776                         (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
 777                 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
 778                 ret = IRQ_HANDLED;
 779         }
 780
 781         if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
 782                         && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
 783                 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
 784                 xqspi->isinstr = false;
 785                 spi_finalize_current_transfer(master);
 786                 ret = IRQ_HANDLED;
 787         }
 788         return ret;
 789 }
 790
 791 /**
 792  * zynqmp_qspi_selectspimode:   Selects SPI mode - x1 or x2 or x4.
 793  * @xqspi:      xqspi is a pointer to the GQSPI instance
 794  * @spimode:    spimode - SPI or DUAL or QUAD.
 795  * Return:      Mask to set desired SPI mode in GENFIFO entry.
 796  */
 797 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
 798                                                 u8 spimode)
 799 {
 800         u32 mask = 0;
 801
 802         switch (spimode) {
 803         case GQSPI_SELECT_MODE_DUALSPI:
 804                 mask = GQSPI_GENFIFO_MODE_DUALSPI;
 805                 break;
 806         case GQSPI_SELECT_MODE_QUADSPI:
 807                 mask = GQSPI_GENFIFO_MODE_QUADSPI;
 808                 break;
 809         case GQSPI_SELECT_MODE_SPI:
 810                 mask = GQSPI_GENFIFO_MODE_SPI;
 811                 break;
 812         default:
 813                 dev_warn(xqspi->dev, "Invalid SPI mode\n");
 814         }
 815
 816         return mask;
 817 }
 818
 819 /**
 820  * zynq_qspi_setuprxdma:        This function sets up the RX DMA operation
 821  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 822  */
 823 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
 824 {
 825         u32 rx_bytes, rx_rem, config_reg;
 826         dma_addr_t addr;
 827         u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
 828
 829         if ((xqspi->bytes_to_receive < 8) ||
 830                 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
 831                 /* Setting to IO mode */
 832                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 833                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 834                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 835                 xqspi->mode = GQSPI_MODE_IO;
 836                 xqspi->dma_rx_bytes = 0;
 837                 return;
 838         }
 839
 840         rx_rem = xqspi->bytes_to_receive % 4;
 841         rx_bytes = (xqspi->bytes_to_receive - rx_rem);
 842
 843         addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
 844                                                 rx_bytes, DMA_FROM_DEVICE);
 845         if (dma_mapping_error(xqspi->dev, addr))
 846                 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
 847
 848         xqspi->dma_rx_bytes = rx_bytes;
 849         xqspi->dma_addr = addr;
 850         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
 851                                 (u32)(addr & 0xffffffff));
 852         addr = ((addr >> 16) >> 16);
 853         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
 854                                 ((u32)addr) & 0xfff);
 855
 856         /* Enabling the DMA mode */
 857         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 858         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 859         config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
 860         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 861
 862         /* Switch to DMA mode */
 863         xqspi->mode = GQSPI_MODE_DMA;
 864
 865         /* Write the number of bytes to transfer */
 866         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
 867 }
 868
 869 /**
 870  * zynqmp_qspi_txrxsetup:       This function checks the TX/RX buffers in
 871  *                              the transfer and sets up the GENFIFO entries,
 872  *                              TX FIFO as required.
 873  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 874  * @transfer:   It is a pointer to the structure containing transfer data.
 875  * @genfifoentry:       genfifoentry is pointer to the variable in which
 876  *                      GENFIFO mask is returned to calling function
 877  */
 878 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
 879                                   struct spi_transfer *transfer,
 880                                   u32 *genfifoentry)
 881 {
 882         u32 config_reg;
 883
 884         /* Transmit */
 885         if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
 886                 /* Setup data to be TXed */
 887                 *genfifoentry &= ~GQSPI_GENFIFO_RX;
 888                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 889                 *genfifoentry |= GQSPI_GENFIFO_TX;
 890                 *genfifoentry |=
 891                         zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
 892                 xqspi->bytes_to_transfer = transfer->len - (transfer->dummy/8);
 893                 if (xqspi->mode == GQSPI_MODE_DMA) {
 894                         config_reg = zynqmp_gqspi_read(xqspi,
 895                                                         GQSPI_CONFIG_OFST);
 896                         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 897                         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 898                                                                 config_reg);
 899                         xqspi->mode = GQSPI_MODE_IO;
 900                 }
 901                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
 902                 /* Discard RX data */
 903                 xqspi->bytes_to_receive = 0;
 904         } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
 905                 /* Receive */
 906
 907                 /* TX auto fill */
 908                 *genfifoentry &= ~GQSPI_GENFIFO_TX;
 909                 /* Setup RX */
 910                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 911                 *genfifoentry |= GQSPI_GENFIFO_RX;
 912                 *genfifoentry |=
 913                         zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
 914                 xqspi->bytes_to_transfer = 0;
 915                 xqspi->bytes_to_receive = transfer->len;
 916                 zynq_qspi_setuprxdma(xqspi);
 917         }
 918 }
 919
 920 /**
 921  * zynqmp_qspi_start_transfer:  Initiates the QSPI transfer
 922  * @master:     Pointer to the spi_master structure which provides
 923  *              information about the controller.
 924  * @qspi:       Pointer to the spi_device structure
 925  * @transfer:   Pointer to the spi_transfer structure which provide information
 926  *              about next transfer parameters
 927  *
 928  * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 929  * transfer to be completed.
 930  *
 931  * Return:      Number of bytes transferred in the last transfer
 932  */
 933 static int zynqmp_qspi_start_transfer(struct spi_master *master,
 934                                       struct spi_device *qspi,
 935                                       struct spi_transfer *transfer)
 936 {
 937         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 938         u32 genfifoentry = 0x0, transfer_len;
 939
 940         xqspi->txbuf = transfer->tx_buf;
 941         xqspi->rxbuf = transfer->rx_buf;
 942
 943         zynqmp_qspi_setup_transfer(qspi, transfer);
 944
 945         genfifoentry |= xqspi->genfifocs;
 946         genfifoentry |= xqspi->genfifobus;
 947
 948         if ((!xqspi->isinstr) &&
 949                 (master->flags & SPI_MASTER_DATA_STRIPE))
 950                 genfifoentry |= GQSPI_GENFIFO_STRIPE;
 951
 952         zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
 953
 954         if (xqspi->mode == GQSPI_MODE_DMA)
 955                 transfer_len = xqspi->dma_rx_bytes;
 956         else
 957                 transfer_len = transfer->len - (transfer->dummy/8);
 958
 959         xqspi->genfifoentry = genfifoentry;
 960         if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
 961                 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 962                 genfifoentry |= transfer_len;
 963                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 964                 if (transfer->dummy) {
 965                         zynqmp_qspi_preparedummy(xqspi, transfer,
 966                                         &genfifoentry);
 967                         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
 968                                         genfifoentry);
 969                 }
 970         } else {
 971                 int tempcount = transfer_len;
 972                 u32 exponent = 8;       /* 2^8 = 256 */
 973                 u8 imm_data = tempcount & 0xFF;
 974
 975                 tempcount &= ~(tempcount & 0xFF);
 976                 /* Immediate entry */
 977                 if (tempcount != 0) {
 978                         /* Exponent entries */
 979                         genfifoentry |= GQSPI_GENFIFO_EXP;
 980                         while (tempcount != 0) {
 981                                 if (tempcount & GQSPI_GENFIFO_EXP_START) {
 982                                         genfifoentry &=
 983                                             ~GQSPI_GENFIFO_IMM_DATA_MASK;
 984                                         genfifoentry |= exponent;
 985                                         zynqmp_gqspi_write(xqspi,
 986                                                            GQSPI_GEN_FIFO_OFST,
 987                                                            genfifoentry);
 988                                 }
 989                                 tempcount = tempcount >> 1;
 990                                 exponent++;
 991                         }
 992                 }
 993                 if (imm_data != 0) {
 994                         genfifoentry &= ~GQSPI_GENFIFO_EXP;
 995                         genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 996                         genfifoentry |= (u8) (imm_data & 0xFF);
 997                         zynqmp_gqspi_write(xqspi,
 998                                            GQSPI_GEN_FIFO_OFST, genfifoentry);
 999                 }
1000         }
1001
1002         if ((xqspi->mode == GQSPI_MODE_IO) &&
1003                         (xqspi->rxbuf != NULL)) {
1004                 /* Dummy generic FIFO entry */
1005                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
1006         }
1007
1008         /* Since we are using manual mode */
1009         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1010                            zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1011                            GQSPI_CFG_START_GEN_FIFO_MASK);
1012
1013         if (xqspi->txbuf != NULL)
1014                 /* Enable interrupts for TX */
1015                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1016                                    GQSPI_IER_TXEMPTY_MASK |
1017                                         GQSPI_IER_GENFIFOEMPTY_MASK |
1018                                         GQSPI_IER_TXNOT_FULL_MASK);
1019
1020         if (xqspi->rxbuf != NULL) {
1021                 /* Enable interrupts for RX */
1022                 if (xqspi->mode == GQSPI_MODE_DMA) {
1023                         /* Enable DMA interrupts */
1024                         zynqmp_gqspi_write(xqspi,
1025                                         GQSPI_QSPIDMA_DST_I_EN_OFST,
1026                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1027                 } else {
1028                         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1029                                         GQSPI_IER_GENFIFOEMPTY_MASK |
1030                                         GQSPI_IER_RXNEMPTY_MASK |
1031                                         GQSPI_IER_RXEMPTY_MASK);
1032                 }
1033         }
1034
1035         return transfer->len;
1036 }
1037
1038 /**
1039  * zynqmp_qspi_suspend: Suspend method for the QSPI driver
1040  * @_dev:       Address of the platform_device structure
1041  *
1042  * This function stops the QSPI driver queue and disables the QSPI controller
1043  *
1044  * Return:      Always 0
1045  */
1046 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
1047 {
1048         struct platform_device *pdev = to_platform_device(dev);
1049         struct spi_master *master = platform_get_drvdata(pdev);
1050
1051         spi_master_suspend(master);
1052
1053         zynqmp_unprepare_transfer_hardware(master);
1054
1055         return 0;
1056 }
1057
1058 /**
1059  * zynqmp_qspi_resume:  Resume method for the QSPI driver
1060  * @dev:        Address of the platform_device structure
1061  *
1062  * The function starts the QSPI driver queue and initializes the QSPI
1063  * controller
1064  *
1065  * Return:      0 on success; error value otherwise
1066  */
1067 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
1068 {
1069         struct platform_device *pdev = to_platform_device(dev);
1070         struct spi_master *master = platform_get_drvdata(pdev);
1071         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1072         int ret = 0;
1073
1074         ret = clk_enable(xqspi->pclk);
1075         if (ret) {
1076                 dev_err(dev, "Cannot enable APB clock.\n");
1077                 return ret;
1078         }
1079
1080         ret = clk_enable(xqspi->refclk);
1081         if (ret) {
1082                 dev_err(dev, "Cannot enable device clock.\n");
1083                 clk_disable(xqspi->pclk);
1084                 return ret;
1085         }
1086
1087         spi_master_resume(master);
1088
1089         return 0;
1090 }
1091
1092 static SIMPLE_DEV_PM_OPS(zynqmp_qspi_dev_pm_ops, zynqmp_qspi_suspend,
1093                          zynqmp_qspi_resume);
1094
1095 /**
1096  * zynqmp_qspi_probe:   Probe method for the QSPI driver
1097  * @pdev:       Pointer to the platform_device structure
1098  *
1099  * This function initializes the driver data structures and the hardware.
1100  *
1101  * Return:      0 on success; error value otherwise
1102  */
1103 static int zynqmp_qspi_probe(struct platform_device *pdev)
1104 {
1105         int ret = 0;
1106         struct spi_master *master;
1107         struct zynqmp_qspi *xqspi;
1108         struct resource *res;
1109         struct device *dev = &pdev->dev;
1110         struct device_node *nc;
1111         u32 num_cs;
1112         u32 rx_bus_width;
1113
1114         master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1115         if (!master)
1116                 return -ENOMEM;
1117
1118         xqspi = spi_master_get_devdata(master);
1119         master->dev.of_node = pdev->dev.of_node;
1120         platform_set_drvdata(pdev, master);
1121
1122         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123         xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1124         if (IS_ERR(xqspi->regs)) {
1125                 ret = PTR_ERR(xqspi->regs);
1126                 goto remove_master;
1127         }
1128
1129         xqspi->dev = dev;
1130         xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1131         if (IS_ERR(xqspi->pclk)) {
1132                 dev_err(dev, "pclk clock not found.\n");
1133                 ret = PTR_ERR(xqspi->pclk);
1134                 goto remove_master;
1135         }
1136
1137         ret = clk_prepare_enable(xqspi->pclk);
1138         if (ret) {
1139                 dev_err(dev, "Unable to enable APB clock.\n");
1140                 goto remove_master;
1141         }
1142
1143         xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1144         if (IS_ERR(xqspi->refclk)) {
1145                 dev_err(dev, "ref_clk clock not found.\n");
1146                 ret = PTR_ERR(xqspi->refclk);
1147                 goto clk_dis_pclk;
1148         }
1149
1150         ret = clk_prepare_enable(xqspi->refclk);
1151         if (ret) {
1152                 dev_err(dev, "Unable to enable device clock.\n");
1153                 goto clk_dis_pclk;
1154         }
1155
1156         /* QSPI controller initializations */
1157         zynqmp_qspi_init_hw(xqspi);
1158
1159         xqspi->irq = platform_get_irq(pdev, 0);
1160         if (xqspi->irq <= 0) {
1161                 ret = -ENXIO;
1162                 dev_err(dev, "irq resource not found\n");
1163                 goto clk_dis_all;
1164         }
1165         ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1166                                0, pdev->name, master);
1167         if (ret != 0) {
1168                 ret = -ENXIO;
1169                 dev_err(dev, "request_irq failed\n");
1170                 goto clk_dis_all;
1171         }
1172
1173         xqspi->rx_bus_width = GQSPI_RX_BUS_WIDTH_SINGLE;
1174         for_each_available_child_of_node(pdev->dev.of_node, nc) {
1175                 ret = of_property_read_u32(nc, "spi-rx-bus-width",
1176                                         &rx_bus_width);
1177                 if (!ret) {
1178                         xqspi->rx_bus_width = rx_bus_width;
1179                         break;
1180                 }
1181         }
1182         if (ret)
1183                 dev_err(dev, "rx bus width not found\n");
1184
1185         ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
1186         if (ret < 0)
1187                 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1188         else
1189                 master->num_chipselect = num_cs;
1190
1191         master->setup = zynqmp_qspi_setup;
1192         master->set_cs = zynqmp_qspi_chipselect;
1193         master->transfer_one = zynqmp_qspi_start_transfer;
1194         master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1195         master->unprepare_transfer_hardware =
1196                                         zynqmp_unprepare_transfer_hardware;
1197         master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1198         master->bits_per_word_mask = SPI_BPW_MASK(8);
1199         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1200                             SPI_TX_DUAL | SPI_TX_QUAD;
1201         xqspi->speed_hz = master->max_speed_hz;
1202
1203         if (master->dev.parent == NULL)
1204                 master->dev.parent = &master->dev;
1205
1206         ret = spi_register_master(master);
1207         if (ret)
1208                 goto clk_dis_all;
1209
1210         dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1211
1212         return 0;
1213
1214 clk_dis_all:
1215         clk_disable_unprepare(xqspi->refclk);
1216 clk_dis_pclk:
1217         clk_disable_unprepare(xqspi->pclk);
1218 remove_master:
1219         spi_master_put(master);
1220
1221         return ret;
1222 }
1223
1224 /**
1225  * zynqmp_qspi_remove:  Remove method for the QSPI driver
1226  * @pdev:       Pointer to the platform_device structure
1227  *
1228  * This function is called if a device is physically removed from the system or
1229  * if the driver module is being unloaded. It frees all resources allocated to
1230  * the device.
1231  *
1232  * Return:      0 Always
1233  */
1234 static int zynqmp_qspi_remove(struct platform_device *pdev)
1235 {
1236         struct spi_master *master = platform_get_drvdata(pdev);
1237         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1238
1239         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1240         clk_disable_unprepare(xqspi->refclk);
1241         clk_disable_unprepare(xqspi->pclk);
1242
1243         spi_unregister_master(master);
1244
1245         return 0;
1246 }
1247
1248 static const struct of_device_id zynqmp_qspi_of_match[] = {
1249         { .compatible = "xlnx,zynqmp-qspi-1.0", },
1250         { /* End of table */ }
1251 };
1252
1253 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1254
1255 static struct platform_driver zynqmp_qspi_driver = {
1256         .probe = zynqmp_qspi_probe,
1257         .remove = zynqmp_qspi_remove,
1258         .driver = {
1259                 .name = "zynqmp-qspi",
1260                 .of_match_table = zynqmp_qspi_of_match,
1261                 .pm = &zynqmp_qspi_dev_pm_ops,
1262         },
1263 };
1264
1265 module_platform_driver(zynqmp_qspi_driver);
1266
1267 MODULE_AUTHOR("Xilinx, Inc.");
1268 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1269 MODULE_LICENSE("GPL");