arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU102 RevA";
  20         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <108>; /* down */
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &can1 {
  71         status = "okay";
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_can1_default>;
  74 };
  75
  76 &dcc {
  77         status = "okay";
  78 };
  79
  80 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  81 &fpd_dma_chan1 {
  82         status = "okay";
  83 };
  84
  85 &fpd_dma_chan2 {
  86         status = "okay";
  87 };
  88
  89 &fpd_dma_chan3 {
  90         status = "okay";
  91 };
  92
  93 &fpd_dma_chan4 {
  94         status = "okay";
  95 };
  96
  97 &fpd_dma_chan5 {
  98         status = "okay";
  99 };
 100
 101 &fpd_dma_chan6 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan7 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan8 {
 110         status = "okay";
 111 };
 112
 113 &gem3 {
 114         status = "okay";
 115         phy-handle = <&phy0>;
 116         phy-mode = "rgmii-id";
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gem3_default>;
 119         phy0: phy@21 {
 120                 reg = <21>;
 121                 ti,rx-internal-delay = <0x8>;
 122                 ti,tx-internal-delay = <0xa>;
 123                 ti,fifo-depth = <0x1>;
 124                 ti,rxctrl-strap-worka;
 125         };
 126 };
 127
 128 &gpio {
 129         status = "okay";
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_gpio_default>;
 132 };
 133
 134 &gpu {
 135         status = "okay";
 136 };
 137
 138 &i2c0 {
 139         status = "okay";
 140         clock-frequency = <400000>;
 141         pinctrl-names = "default", "gpio";
 142         pinctrl-0 = <&pinctrl_i2c0_default>;
 143         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 144         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 145         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 146
 147         tca6416_u97: gpio@20 {
 148                 compatible = "ti,tca6416";
 149                 reg = <0x20>;
 150                 gpio-controller;
 151                 #gpio-cells = <2>;
 152                 /*
 153                  * IRQ not connected
 154                  * Lines:
 155                  * 0 - PS_GTR_LAN_SEL0
 156                  * 1 - PS_GTR_LAN_SEL1
 157                  * 2 - PS_GTR_LAN_SEL2
 158                  * 3 - PS_GTR_LAN_SEL3
 159                  * 4 - PCI_CLK_DIR_SEL
 160                  * 5 - IIC_MUX_RESET_B
 161                  * 6 - GEM3_EXP_RESET_B
 162                  * 7, 10 - 17 - not connected
 163                  */
 164
 165                 gtr_sel0 {
 166                         gpio-hog;
 167                         gpios = <0 0>;
 168                         output-low; /* PCIE = 0, DP = 1 */
 169                         line-name = "sel0";
 170                 };
 171                 gtr_sel1 {
 172                         gpio-hog;
 173                         gpios = <1 0>;
 174                         output-high; /* PCIE = 0, DP = 1 */
 175                         line-name = "sel1";
 176                 };
 177                 gtr_sel2 {
 178                         gpio-hog;
 179                         gpios = <2 0>;
 180                         output-high; /* PCIE = 0, USB0 = 1 */
 181                         line-name = "sel2";
 182                 };
 183                 gtr_sel3 {
 184                         gpio-hog;
 185                         gpios = <3 0>;
 186                         output-high; /* PCIE = 0, SATA = 1 */
 187                         line-name = "sel3";
 188                 };
 189         };
 190
 191         tca6416_u61: gpio@21 {
 192                 compatible = "ti,tca6416";
 193                 reg = <0x21>;
 194                 gpio-controller;
 195                 #gpio-cells = <2>;
 196                 /*
 197                  * IRQ not connected
 198                  * Lines:
 199                  * 0 - VCCPSPLL_EN
 200                  * 1 - MGTRAVCC_EN
 201                  * 2 - MGTRAVTT_EN
 202                  * 3 - VCCPSDDRPLL_EN
 203                  * 4 - MIO26_PMU_INPUT_LS
 204                  * 5 - PL_PMBUS_ALERT
 205                  * 6 - PS_PMBUS_ALERT
 206                  * 7 - MAXIM_PMBUS_ALERT
 207                  * 10 - PL_DDR4_VTERM_EN
 208                  * 11 - PL_DDR4_VPP_2V5_EN
 209                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 210                  * 13 - PS_DIMM_SUSPEND_EN
 211                  * 14 - PS_DDR4_VTERM_EN
 212                  * 15 - PS_DDR4_VPP_2V5_EN
 213                  * 16 - 17 - not connected
 214                  */
 215         };
 216
 217         i2c-mux@75 { /* u60 */
 218                 compatible = "nxp,pca9544";
 219                 #address-cells = <1>;
 220                 #size-cells = <0>;
 221                 reg = <0x75>;
 222                 i2c@0 {
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         reg = <0>;
 226                         /* PS_PMBUS */
 227                         ina226@40 { /* u76 */
 228                                 compatible = "ti,ina226";
 229                                 reg = <0x40>;
 230                                 shunt-resistor = <5000>;
 231                         };
 232                         ina226@41 { /* u77 */
 233                                 compatible = "ti,ina226";
 234                                 reg = <0x41>;
 235                                 shunt-resistor = <5000>;
 236                         };
 237                         ina226@42 { /* u78 */
 238                                 compatible = "ti,ina226";
 239                                 reg = <0x42>;
 240                                 shunt-resistor = <5000>;
 241                         };
 242                         ina226@43 { /* u87 */
 243                                 compatible = "ti,ina226";
 244                                 reg = <0x43>;
 245                                 shunt-resistor = <5000>;
 246                         };
 247                         ina226@44 { /* u85 */
 248                                 compatible = "ti,ina226";
 249                                 reg = <0x44>;
 250                                 shunt-resistor = <5000>;
 251                         };
 252                         ina226@45 { /* u86 */
 253                                 compatible = "ti,ina226";
 254                                 reg = <0x45>;
 255                                 shunt-resistor = <5000>;
 256                         };
 257                         ina226@46 { /* u93 */
 258                                 compatible = "ti,ina226";
 259                                 reg = <0x46>;
 260                                 shunt-resistor = <5000>;
 261                         };
 262                         ina226@47 { /* u88 */
 263                                 compatible = "ti,ina226";
 264                                 reg = <0x47>;
 265                                 shunt-resistor = <5000>;
 266                         };
 267                         ina226@4a { /* u15 */
 268                                 compatible = "ti,ina226";
 269                                 reg = <0x4a>;
 270                                 shunt-resistor = <5000>;
 271                         };
 272                         ina226@4b { /* u92 */
 273                                 compatible = "ti,ina226";
 274                                 reg = <0x4b>;
 275                                 shunt-resistor = <5000>;
 276                         };
 277                 };
 278                 i2c@1 {
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         reg = <1>;
 282                         /* PL_PMBUS */
 283                         ina226@40 { /* u79 */
 284                                 compatible = "ti,ina226";
 285                                 reg = <0x40>;
 286                                 shunt-resistor = <2000>;
 287                         };
 288                         ina226@41 { /* u81 */
 289                                 compatible = "ti,ina226";
 290                                 reg = <0x41>;
 291                                 shunt-resistor = <5000>;
 292                         };
 293                         ina226@42 { /* u80 */
 294                                 compatible = "ti,ina226";
 295                                 reg = <0x42>;
 296                                 shunt-resistor = <5000>;
 297                         };
 298                         ina226@43 { /* u84 */
 299                                 compatible = "ti,ina226";
 300                                 reg = <0x43>;
 301                                 shunt-resistor = <5000>;
 302                         };
 303                         ina226@44 { /* u16 */
 304                                 compatible = "ti,ina226";
 305                                 reg = <0x44>;
 306                                 shunt-resistor = <5000>;
 307                         };
 308                         ina226@45 { /* u65 */
 309                                 compatible = "ti,ina226";
 310                                 reg = <0x45>;
 311                                 shunt-resistor = <5000>;
 312                         };
 313                         ina226@46 { /* u74 */
 314                                 compatible = "ti,ina226";
 315                                 reg = <0x46>;
 316                                 shunt-resistor = <5000>;
 317                         };
 318                         ina226@47 { /* u75 */
 319                                 compatible = "ti,ina226";
 320                                 reg = <0x47>;
 321                                 shunt-resistor = <5000>;
 322                         };
 323                 };
 324                 i2c@2 {
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         reg = <2>;
 328                         /* MAXIM_PMBUS - 00 */
 329                         max15301@a { /* u46 */
 330                                 compatible = "maxim,max15301";
 331                                 reg = <0xa>;
 332                         };
 333                         max15303@b { /* u4 */
 334                                 compatible = "maxim,max15303";
 335                                 reg = <0xb>;
 336                         };
 337                         max15303@10 { /* u13 */
 338                                 compatible = "maxim,max15303";
 339                                 reg = <0x10>;
 340                         };
 341                         max15301@13 { /* u47 */
 342                                 compatible = "maxim,max15301";
 343                                 reg = <0x13>;
 344                         };
 345                         max15303@14 { /* u7 */
 346                                 compatible = "maxim,max15303";
 347                                 reg = <0x14>;
 348                         };
 349                         max15303@15 { /* u6 */
 350                                 compatible = "maxim,max15303";
 351                                 reg = <0x15>;
 352                         };
 353                         max15303@16 { /* u10 */
 354                                 compatible = "maxim,max15303";
 355                                 reg = <0x16>;
 356                         };
 357                         max15303@17 { /* u9 */
 358                                 compatible = "maxim,max15303";
 359                                 reg = <0x17>;
 360                         };
 361                         max15301@18 { /* u63 */
 362                                 compatible = "maxim,max15301";
 363                                 reg = <0x18>;
 364                         };
 365                         max15303@1a { /* u49 */
 366                                 compatible = "maxim,max15303";
 367                                 reg = <0x1a>;
 368                         };
 369                         max15303@1d { /* u18 */
 370                                 compatible = "maxim,max15303";
 371                                 reg = <0x1d>;
 372                         };
 373                         max15303@20 { /* u8 */
 374                                 compatible = "maxim,max15303";
 375                                 status = "disabled"; /* unreachable */
 376                                 reg = <0x20>;
 377                         };
 378
 379 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
 380 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 381 */
 382                         max20751@72 { /* u95 FIXME - not detected */
 383                                 compatible = "maxim,max20751";
 384                                 reg = <0x72>;
 385                         };
 386                         max20751@73 { /* u96 FIXME - not detected */
 387                                 compatible = "maxim,max20751";
 388                                 reg = <0x73>;
 389                         };
 390                 };
 391                 /* Bus 3 is not connected */
 392         };
 393
 394         /* FIXME PMOD - j160 */
 395         /* FIXME MSP430F - u41 - not detected */
 396 };
 397
 398 &i2c1 {
 399         status = "okay";
 400         clock-frequency = <400000>;
 401         pinctrl-names = "default", "gpio";
 402         pinctrl-0 = <&pinctrl_i2c1_default>;
 403         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 404         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 405         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 406
 407         /* FIXME PL i2c via PCA9306 - u45 */
 408         /* FIXME MSP430 - u41 - not detected */
 409         i2c-mux@74 { /* u34 */
 410                 compatible = "nxp,pca9548";
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 reg = <0x74>;
 414                 i2c@0 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         reg = <0>;
 418                         /*
 419                          * IIC_EEPROM 1kB memory which uses 256B blocks
 420                          * where every block has different address.
 421                          *    0 - 256B address 0x54
 422                          * 256B - 512B address 0x55
 423                          * 512B - 768B address 0x56
 424                          * 768B - 1024B address 0x57
 425                          */
 426                         eeprom: eeprom@54 { /* u23 */
 427                                 compatible = "at,24c08";
 428                                 reg = <0x54>;
 429                         };
 430                 };
 431                 i2c@1 {
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         reg = <1>;
 435                         si5341: clock-generator@36 { /* SI5341 - u69 */
 436                                 compatible = "si5341";
 437                                 reg = <0x36>;
 438                         };
 439
 440                 };
 441                 i2c@2 {
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         reg = <2>;
 445                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 446                                 #clock-cells = <0>;
 447                                 compatible = "silabs,si570";
 448                                 reg = <0x5d>;
 449                                 temperature-stability = <50>;
 450                                 factory-fout = <300000000>;
 451                                 clock-frequency = <300000000>;
 452                         };
 453                 };
 454                 i2c@3 {
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         reg = <3>;
 458                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 459                                 #clock-cells = <0>;
 460                                 compatible = "silabs,si570";
 461                                 reg = <0x5d>;
 462                                 temperature-stability = <50>; /* copy from zc702 */
 463                                 factory-fout = <156250000>;
 464                                 clock-frequency = <148500000>;
 465                         };
 466                 };
 467                 i2c@4 {
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                         reg = <4>;
 471                         si5328: clock-generator@69 {/* SI5328 - u20 */
 472                                 compatible = "silabs,si5328";
 473                                 reg = <0x69>;
 474                                 /*
 475                                  * Chip has interrupt present connected to PL
 476                                  * interrupt-parent = <&>;
 477                                  * interrupts = <>;
 478                                  */
 479                         };
 480                 };
 481                 /* 5 - 7 unconnected */
 482         };
 483
 484         i2c-mux@75 {
 485                 compatible = "nxp,pca9548"; /* u135 */
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 reg = <0x75>;
 489
 490                 i2c@0 {
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         reg = <0>;
 494                         /* HPC0_IIC */
 495                 };
 496                 i2c@1 {
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         reg = <1>;
 500                         /* HPC1_IIC */
 501                 };
 502                 i2c@2 {
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         reg = <2>;
 506                         /* SYSMON */
 507                 };
 508                 i2c@3 {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         reg = <3>;
 512                         /* DDR4 SODIMM */
 513                         dev@19 { /* u-boot detection */
 514                                 compatible = "xxx";
 515                                 reg = <0x19>;
 516                         };
 517                         dev@30 { /* u-boot detection */
 518                                 compatible = "xxx";
 519                                 reg = <0x30>;
 520                         };
 521                         dev@35 { /* u-boot detection */
 522                                 compatible = "xxx";
 523                                 reg = <0x35>;
 524                         };
 525                         dev@36 { /* u-boot detection */
 526                                 compatible = "xxx";
 527                                 reg = <0x36>;
 528                         };
 529                         dev@51 { /* u-boot detection - maybe SPD */
 530                                 compatible = "xxx";
 531                                 reg = <0x51>;
 532                         };
 533                 };
 534                 i2c@4 {
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         reg = <4>;
 538                         /* SEP 3 */
 539                 };
 540                 i2c@5 {
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         reg = <5>;
 544                         /* SEP 2 */
 545                 };
 546                 i2c@6 {
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         reg = <6>;
 550                         /* SEP 1 */
 551                 };
 552                 i2c@7 {
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         reg = <7>;
 556                         /* SEP 0 */
 557                 };
 558         };
 559 };
 560
 561 &pinctrl0 {
 562         status = "okay";
 563         pinctrl_i2c0_default: i2c0-default {
 564                 mux {
 565                         groups = "i2c0_3_grp";
 566                         function = "i2c0";
 567                 };
 568
 569                 conf {
 570                         groups = "i2c0_3_grp";
 571                         bias-pull-up;
 572                         slew-rate = <SLEW_RATE_SLOW>;
 573                         io-standard = <IO_STANDARD_LVCMOS18>;
 574                 };
 575         };
 576
 577         pinctrl_i2c0_gpio: i2c0-gpio {
 578                 mux {
 579                         groups = "gpio0_14_grp", "gpio0_15_grp";
 580                         function = "gpio0";
 581                 };
 582
 583                 conf {
 584                         groups = "gpio0_14_grp", "gpio0_15_grp";
 585                         slew-rate = <SLEW_RATE_SLOW>;
 586                         io-standard = <IO_STANDARD_LVCMOS18>;
 587                 };
 588         };
 589
 590         pinctrl_i2c1_default: i2c1-default {
 591                 mux {
 592                         groups = "i2c1_4_grp";
 593                         function = "i2c1";
 594                 };
 595
 596                 conf {
 597                         groups = "i2c1_4_grp";
 598                         bias-pull-up;
 599                         slew-rate = <SLEW_RATE_SLOW>;
 600                         io-standard = <IO_STANDARD_LVCMOS18>;
 601                 };
 602         };
 603
 604         pinctrl_i2c1_gpio: i2c1-gpio {
 605                 mux {
 606                         groups = "gpio0_16_grp", "gpio0_17_grp";
 607                         function = "gpio0";
 608                 };
 609
 610                 conf {
 611                         groups = "gpio0_16_grp", "gpio0_17_grp";
 612                         slew-rate = <SLEW_RATE_SLOW>;
 613                         io-standard = <IO_STANDARD_LVCMOS18>;
 614                 };
 615         };
 616
 617         pinctrl_uart0_default: uart0-default {
 618                 mux {
 619                         groups = "uart0_4_grp";
 620                         function = "uart0";
 621                 };
 622
 623                 conf {
 624                         groups = "uart0_4_grp";
 625                         slew-rate = <SLEW_RATE_SLOW>;
 626                         io-standard = <IO_STANDARD_LVCMOS18>;
 627                 };
 628
 629                 conf-rx {
 630                         pins = "MIO18";
 631                         bias-high-impedance;
 632                 };
 633
 634                 conf-tx {
 635                         pins = "MIO19";
 636                         bias-disable;
 637                 };
 638         };
 639
 640         pinctrl_uart1_default: uart1-default {
 641                 mux {
 642                         groups = "uart1_5_grp";
 643                         function = "uart1";
 644                 };
 645
 646                 conf {
 647                         groups = "uart1_5_grp";
 648                         slew-rate = <SLEW_RATE_SLOW>;
 649                         io-standard = <IO_STANDARD_LVCMOS18>;
 650                 };
 651
 652                 conf-rx {
 653                         pins = "MIO21";
 654                         bias-high-impedance;
 655                 };
 656
 657                 conf-tx {
 658                         pins = "MIO20";
 659                         bias-disable;
 660                 };
 661         };
 662
 663         pinctrl_usb0_default: usb0-default {
 664                 mux {
 665                         groups = "usb0_0_grp";
 666                         function = "usb0";
 667                 };
 668
 669                 conf {
 670                         groups = "usb0_0_grp";
 671                         slew-rate = <SLEW_RATE_SLOW>;
 672                         io-standard = <IO_STANDARD_LVCMOS18>;
 673                 };
 674
 675                 conf-rx {
 676                         pins = "MIO52", "MIO53", "MIO55";
 677                         bias-high-impedance;
 678                 };
 679
 680                 conf-tx {
 681                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 682                                "MIO60", "MIO61", "MIO62", "MIO63";
 683                         bias-disable;
 684                 };
 685         };
 686
 687         pinctrl_gem3_default: gem3-default {
 688                 mux {
 689                         function = "ethernet3";
 690                         groups = "ethernet3_0_grp";
 691                 };
 692
 693                 conf {
 694                         groups = "ethernet3_0_grp";
 695                         slew-rate = <SLEW_RATE_SLOW>;
 696                         io-standard = <IO_STANDARD_LVCMOS18>;
 697                 };
 698
 699                 conf-rx {
 700                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 701                                                                         "MIO75";
 702                         bias-high-impedance;
 703                         low-power-disable;
 704                 };
 705
 706                 conf-tx {
 707                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 708                                                                         "MIO69";
 709                         bias-disable;
 710                         low-power-enable;
 711                 };
 712
 713                 mux-mdio {
 714                         function = "mdio3";
 715                         groups = "mdio3_0_grp";
 716                 };
 717
 718                 conf-mdio {
 719                         groups = "mdio3_0_grp";
 720                         slew-rate = <SLEW_RATE_SLOW>;
 721                         io-standard = <IO_STANDARD_LVCMOS18>;
 722                         bias-disable;
 723                 };
 724         };
 725
 726         pinctrl_can1_default: can1-default {
 727                 mux {
 728                         function = "can1";
 729                         groups = "can1_6_grp";
 730                 };
 731
 732                 conf {
 733                         groups = "can1_6_grp";
 734                         slew-rate = <SLEW_RATE_SLOW>;
 735                         io-standard = <IO_STANDARD_LVCMOS18>;
 736                 };
 737
 738                 conf-rx {
 739                         pins = "MIO25";
 740                         bias-high-impedance;
 741                 };
 742
 743                 conf-tx {
 744                         pins = "MIO24";
 745                         bias-disable;
 746                 };
 747         };
 748
 749         pinctrl_sdhci1_default: sdhci1-default {
 750                 mux {
 751                         groups = "sdio1_0_grp";
 752                         function = "sdio1";
 753                 };
 754
 755                 conf {
 756                         groups = "sdio1_0_grp";
 757                         slew-rate = <SLEW_RATE_SLOW>;
 758                         io-standard = <IO_STANDARD_LVCMOS18>;
 759                         bias-disable;
 760                 };
 761
 762                 mux-cd {
 763                         groups = "sdio1_cd_0_grp";
 764                         function = "sdio1_cd";
 765                 };
 766
 767                 conf-cd {
 768                         groups = "sdio1_cd_0_grp";
 769                         bias-high-impedance;
 770                         bias-pull-up;
 771                         slew-rate = <SLEW_RATE_SLOW>;
 772                         io-standard = <IO_STANDARD_LVCMOS18>;
 773                 };
 774
 775                 mux-wp {
 776                         groups = "sdio1_wp_0_grp";
 777                         function = "sdio1_wp";
 778                 };
 779
 780                 conf-wp {
 781                         groups = "sdio1_wp_0_grp";
 782                         bias-high-impedance;
 783                         bias-pull-up;
 784                         slew-rate = <SLEW_RATE_SLOW>;
 785                         io-standard = <IO_STANDARD_LVCMOS18>;
 786                 };
 787         };
 788
 789         pinctrl_gpio_default: gpio-default {
 790                 mux-sw {
 791                         function = "gpio0";
 792                         groups = "gpio0_22_grp", "gpio0_23_grp";
 793                 };
 794
 795                 conf-sw {
 796                         groups = "gpio0_22_grp", "gpio0_23_grp";
 797                         slew-rate = <SLEW_RATE_SLOW>;
 798                         io-standard = <IO_STANDARD_LVCMOS18>;
 799                 };
 800
 801                 mux-msp {
 802                         function = "gpio0";
 803                         groups = "gpio0_13_grp", "gpio0_38_grp";
 804                 };
 805
 806                 conf-msp {
 807                         groups = "gpio0_13_grp", "gpio0_38_grp";
 808                         slew-rate = <SLEW_RATE_SLOW>;
 809                         io-standard = <IO_STANDARD_LVCMOS18>;
 810                 };
 811
 812                 conf-pull-up {
 813                         pins = "MIO22", "MIO23";
 814                         bias-pull-up;
 815                 };
 816
 817                 conf-pull-none {
 818                         pins = "MIO13", "MIO38";
 819                         bias-disable;
 820                 };
 821         };
 822 };
 823
 824 &pcie {
 825         status = "okay";
 826 };
 827
 828 &qspi {
 829         status = "okay";
 830         is-dual = <1>;
 831         flash@0 {
 832                 compatible = "m25p80"; /* 32MB */
 833                 #address-cells = <1>;
 834                 #size-cells = <1>;
 835                 reg = <0x0>;
 836                 spi-tx-bus-width = <1>;
 837                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 838                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 839                 partition@qspi-fsbl-uboot { /* for testing purpose */
 840                         label = "qspi-fsbl-uboot";
 841                         reg = <0x0 0x100000>;
 842                 };
 843                 partition@qspi-linux { /* for testing purpose */
 844                         label = "qspi-linux";
 845                         reg = <0x100000 0x500000>;
 846                 };
 847                 partition@qspi-device-tree { /* for testing purpose */
 848                         label = "qspi-device-tree";
 849                         reg = <0x600000 0x20000>;
 850                 };
 851                 partition@qspi-rootfs { /* for testing purpose */
 852                         label = "qspi-rootfs";
 853                         reg = <0x620000 0x5E0000>;
 854                 };
 855         };
 856 };
 857
 858 &rtc {
 859         status = "okay";
 860 };
 861
 862 &sata {
 863         status = "okay";
 864         /* SATA OOB timing settings */
 865         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 866         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 867         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 868         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 869         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 870         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 871         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 872         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 873         phy-names = "sata-phy";
 874         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 875 };
 876
 877 /* SD1 with level shifter */
 878 &sdhci1 {
 879         status = "okay";
 880         pinctrl-names = "default";
 881         pinctrl-0 = <&pinctrl_sdhci1_default>;
 882         no-1-8-v;
 883         xlnx,mio_bank = <1>;
 884 };
 885
 886 &serdes {
 887         status = "okay";
 888 };
 889
 890 &uart0 {
 891         status = "okay";
 892         pinctrl-names = "default";
 893         pinctrl-0 = <&pinctrl_uart0_default>;
 894 };
 895
 896 &uart1 {
 897         status = "okay";
 898         pinctrl-names = "default";
 899         pinctrl-0 = <&pinctrl_uart1_default>;
 900 };
 901
 902 /* ULPI SMSC USB3320 */
 903 &usb0 {
 904         status = "okay";
 905         pinctrl-names = "default";
 906         pinctrl-0 = <&pinctrl_usb0_default>;
 907 };
 908
 909 &dwc3_0 {
 910         status = "okay";
 911         dr_mode = "host";
 912         snps,usb3_lpm_capable;
 913         phy-names = "usb3-phy";
 914         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 915         maximum-speed = "super-speed";
 916 };
 917
 918 &watchdog0 {
 919         status = "okay";
 920 };
 921
 922 &xilinx_ams {
 923         status = "okay";
 924 };
 925
 926 &ams_ps {
 927         status = "okay";
 928 };
 929
 930 &ams_pl {
 931         status = "okay";
 932 };
 933
 934 &zynqmp_dpsub {
 935         status = "okay";
 936         phy-names = "dp-phy0";
 937         phys = <&lane1 PHY_TYPE_DP 0 3 27000000>;
 938 };
 939
 940 &zynqmp_dp_snd_codec0 {
 941         status = "okay";
 942 };
 943
 944 &zynqmp_dp_snd_pcm0 {
 945         status = "okay";
 946 };
 947
 948 &zynqmp_dp_snd_pcm1 {
 949         status = "okay";
 950 };
 951
 952 &zynqmp_dp_snd_card0 {
 953         status = "okay";
 954 };
 955
 956 &xlnx_dpdma {
 957         status = "okay";
 958 };