arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU100 revC
   4  *
   5  * (C) Copyright 2016 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  * Nathalie Chan King Choy
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk-ccf.dtsi"
  15 #include <dt-bindings/input/input.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/gpio/gpio.h>
  18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  19 #include <dt-bindings/phy/phy.h>
  20
  21 / {
  22         model = "ZynqMP ZCU100 RevC";
  23         compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
  24
  25         aliases {
  26                 gpio0 = &gpio;
  27                 i2c0 = &i2c1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart1;
  30                 serial1 = &uart0;
  31                 serial2 = &dcc;
  32                 spi0 = &spi0;
  33                 spi1 = &spi1;
  34                 usb0 = &usb0;
  35                 usb1 = &usb1;
  36                 mmc0 = &sdhci0;
  37                 mmc1 = &sdhci1;
  38         };
  39
  40         chosen {
  41                 bootargs = "earlycon";
  42                 stdout-path = "serial0:115200n8";
  43         };
  44
  45         memory@0 {
  46                 device_type = "memory";
  47                 reg = <0x0 0x0 0x0 0x80000000>;
  48         };
  49
  50         gpio-keys {
  51                 compatible = "gpio-keys";
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 autorepeat;
  55                 sw4 {
  56                         label = "sw4";
  57                         gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
  58                         linux,code = <KEY_POWER>;
  59                         gpio-key,wakeup;
  60                         autorepeat;
  61                 };
  62         };
  63
  64         iio-hwmon {
  65                 compatible = "iio-hwmon";
  66                 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
  67                               <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
  68                               <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
  69                               <&xilinx_ams 9>, <&xilinx_ams 10>,
  70                               <&xilinx_ams 11>, <&xilinx_ams 12>;
  71         };
  72
  73         leds {
  74                 compatible = "gpio-leds";
  75                 ds2 {
  76                         label = "ds2";
  77                         gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
  78                         linux,default-trigger = "heartbeat";
  79                 };
  80
  81                 ds3 {
  82                         label = "ds3";
  83                         gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
  84                         linux,default-trigger = "phy0tx"; /* WLAN tx */
  85                         default-state = "off";
  86                 };
  87
  88                 ds4 {
  89                         label = "ds4";
  90                         gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
  91                         linux,default-trigger = "phy0rx"; /* WLAN rx */
  92                         default-state = "off";
  93                 };
  94
  95                 ds5 {
  96                         label = "ds5";
  97                         gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
  98                         linux,default-trigger = "bluetooth-power";
  99                 };
 100
 101                 vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
 102                         label = "vbus_det";
 103                         gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 104                         default-state = "on";
 105                 };
 106         };
 107
 108         ltc2954: ltc2954 { /* U7 */
 109                 compatible = "lltc,ltc2954", "lltc,ltc2952";
 110                 trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */
 111                 /* If there is HW watchdog on mezzanine this signal should be connected there */
 112                 watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */
 113                 kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */
 114         };
 115
 116         wmmcsdio_fixed: fixedregulator-mmcsdio {
 117                 compatible = "regulator-fixed";
 118                 regulator-name = "wmmcsdio_fixed";
 119                 regulator-min-microvolt = <3300000>;
 120                 regulator-max-microvolt = <3300000>;
 121                 regulator-always-on;
 122                 regulator-boot-on;
 123         };
 124
 125         sdio_pwrseq: sdio_pwrseq {
 126                 compatible = "mmc-pwrseq-simple";
 127                 reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
 128         };
 129 };
 130
 131 &dcc {
 132         status = "okay";
 133 };
 134
 135 &gpio {
 136         status = "okay";
 137         gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
 138                           "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
 139                           "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
 140                           "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
 141                           "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
 142                           "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
 143                           "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
 144                           "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
 145                           "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
 146                           "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
 147                           "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
 148                           "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
 149                           "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
 150                           "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
 151                           "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
 152                           "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
 153                           "", "",
 154                           "", "", "", "", "", "", "", "", "", "",
 155                           "", "", "", "", "", "", "", "", "", "",
 156                           "", "", "", "", "", "", "", "", "", "",
 157                           "", "", "", "", "", "", "", "", "", "",
 158                           "", "", "", "", "", "", "", "", "", "",
 159                           "", "", "", "", "", "", "", "", "", "",
 160                           "", "", "", "", "", "", "", "", "", "",
 161                           "", "", "", "", "", "", "", "", "", "",
 162                           "", "", "", "", "", "", "", "", "", "",
 163                           "", "", "", "";
 164 };
 165
 166 &gpu {
 167         status = "okay";
 168 };
 169
 170 &i2c1 {
 171         status = "okay";
 172         pinctrl-names = "default", "gpio";
 173         pinctrl-0 = <&pinctrl_i2c1_default>;
 174         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 175         scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
 176         sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 177         clock-frequency = <100000>;
 178         i2c-mux@75 { /* u11 */
 179                 compatible = "nxp,pca9548";
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 reg = <0x75>;
 183                 i2csw_0: i2c@0 {
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                         reg = <0>;
 187                         /*
 188                          * LSEXP_I2C0
 189                          */
 190                 };
 191                 i2csw_1: i2c@1 {
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                         reg = <1>;
 195                         /*
 196                          * LSEXP_I2C1
 197                          */
 198                 };
 199                 i2csw_2: i2c@2 {
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         reg = <2>;
 203                         /*
 204                          * HSEXP_I2C2
 205                          */
 206                 };
 207                 i2csw_3: i2c@3 {
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         reg = <3>;
 211                         /*
 212                          * HSEXP_I2C3
 213                          */
 214                 };
 215                 i2csw_4: i2c@4 {
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                         reg = <0x4>;
 219
 220                         pmic: pmic@5e { /* Custom TI PMIC u33 */
 221                                 compatible = "ti,tps65086";
 222                                 reg = <0x5e>;
 223                                 interrupt-parent = <&gpio>;
 224                                 interrupts = <77 GPIO_ACTIVE_LOW>;
 225                                 #gpio-cells = <2>;
 226                                 gpio-controller;
 227                         };
 228                 };
 229                 i2csw_5: i2c@5 {
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         reg = <5>;
 233                         /* PS_PMBUS */
 234                         ina226@40 { /* u35 */
 235                                 compatible = "ti,ina226";
 236                                 reg = <0x40>;
 237                                 shunt-resistor = <10000>;
 238                                 /* MIO31 is alert which should be routed to PMUFW */
 239                         };
 240                 };
 241                 i2csw_6: i2c@6 {
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         reg = <6>;
 245                         /*
 246                          * Not Connected
 247                          */
 248                 };
 249                 i2csw_7: i2c@7 {
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                         reg = <7>;
 253                         /*
 254                          * usb5744 (DNP) - U5
 255                          * 100kHz - this is default freq for us
 256                          */
 257                 };
 258         };
 259 };
 260
 261 &pinctrl0 {
 262         status = "okay";
 263         pinctrl_i2c1_default: i2c1-default {
 264                 mux {
 265                         groups = "i2c1_1_grp";
 266                         function = "i2c1";
 267                 };
 268
 269                 conf {
 270                         groups = "i2c1_1_grp";
 271                         bias-pull-up;
 272                         slew-rate = <SLEW_RATE_SLOW>;
 273                         io-standard = <IO_STANDARD_LVCMOS18>;
 274                 };
 275         };
 276
 277         pinctrl_i2c1_gpio: i2c1-gpio {
 278                 mux {
 279                         groups = "gpio0_4_grp", "gpio0_5_grp";
 280                         function = "gpio0";
 281                 };
 282
 283                 conf {
 284                         groups = "gpio0_4_grp", "gpio0_5_grp";
 285                         slew-rate = <SLEW_RATE_SLOW>;
 286                         io-standard = <IO_STANDARD_LVCMOS18>;
 287                 };
 288         };
 289
 290         pinctrl_sdhci0_default: sdhci0-default {
 291                 mux {
 292                         groups = "sdio0_3_grp";
 293                         function = "sdio0";
 294                 };
 295
 296                 conf {
 297                         groups = "sdio0_3_grp";
 298                         slew-rate = <SLEW_RATE_SLOW>;
 299                         io-standard = <IO_STANDARD_LVCMOS18>;
 300                         bias-disable;
 301                 };
 302
 303                 mux-cd {
 304                         groups = "sdio0_cd_0_grp";
 305                         function = "sdio0_cd";
 306                 };
 307
 308                 conf-cd {
 309                         groups = "sdio0_cd_0_grp";
 310                         bias-high-impedance;
 311                         bias-pull-up;
 312                         slew-rate = <SLEW_RATE_SLOW>;
 313                         io-standard = <IO_STANDARD_LVCMOS18>;
 314                 };
 315         };
 316
 317         pinctrl_sdhci1_default: sdhci1-default {
 318                 mux {
 319                         groups = "sdio1_2_grp";
 320                         function = "sdio1";
 321                 };
 322
 323                 conf {
 324                         groups = "sdio1_2_grp";
 325                         slew-rate = <SLEW_RATE_SLOW>;
 326                         io-standard = <IO_STANDARD_LVCMOS18>;
 327                         bias-disable;
 328                 };
 329         };
 330
 331         pinctrl_spi0_default: spi0-default {
 332                 mux {
 333                         groups = "spi0_3_grp";
 334                         function = "spi0";
 335                 };
 336
 337                 conf {
 338                         groups = "spi0_3_grp";
 339                         bias-disable;
 340                         slew-rate = <SLEW_RATE_SLOW>;
 341                         io-standard = <IO_STANDARD_LVCMOS18>;
 342                 };
 343
 344                 mux-cs {
 345                         groups = "spi0_ss_9_grp";
 346                         function = "spi0_ss";
 347                 };
 348
 349                 conf-cs {
 350                         groups = "spi0_ss_9_grp";
 351                         bias-disable;
 352                 };
 353
 354         };
 355
 356         pinctrl_spi1_default: spi1-default {
 357                 mux {
 358                         groups = "spi1_0_grp";
 359                         function = "spi1";
 360                 };
 361
 362                 conf {
 363                         groups = "spi1_0_grp";
 364                         bias-disable;
 365                         slew-rate = <SLEW_RATE_SLOW>;
 366                         io-standard = <IO_STANDARD_LVCMOS18>;
 367                 };
 368
 369                 mux-cs {
 370                         groups = "spi1_ss_0_grp";
 371                         function = "spi1_ss";
 372                 };
 373
 374                 conf-cs {
 375                         groups = "spi1_ss_0_grp";
 376                         bias-disable;
 377                 };
 378
 379         };
 380
 381         pinctrl_uart0_default: uart0-default {
 382                 mux {
 383                         groups = "uart0_0_grp";
 384                         function = "uart0";
 385                 };
 386
 387                 conf {
 388                         groups = "uart0_0_grp";
 389                         slew-rate = <SLEW_RATE_SLOW>;
 390                         io-standard = <IO_STANDARD_LVCMOS18>;
 391                 };
 392
 393                 conf-rx {
 394                         pins = "MIO3";
 395                         bias-high-impedance;
 396                 };
 397
 398                 conf-tx {
 399                         pins = "MIO2";
 400                         bias-disable;
 401                 };
 402         };
 403
 404         pinctrl_uart1_default: uart1-default {
 405                 mux {
 406                         groups = "uart1_0_grp";
 407                         function = "uart1";
 408                 };
 409
 410                 conf {
 411                         groups = "uart1_0_grp";
 412                         slew-rate = <SLEW_RATE_SLOW>;
 413                         io-standard = <IO_STANDARD_LVCMOS18>;
 414                 };
 415
 416                 conf-rx {
 417                         pins = "MIO1";
 418                         bias-high-impedance;
 419                 };
 420
 421                 conf-tx {
 422                         pins = "MIO0";
 423                         bias-disable;
 424                 };
 425         };
 426
 427         pinctrl_usb0_default: usb0-default {
 428                 mux {
 429                         groups = "usb0_0_grp";
 430                         function = "usb0";
 431                 };
 432
 433                 conf {
 434                         groups = "usb0_0_grp";
 435                         slew-rate = <SLEW_RATE_SLOW>;
 436                         io-standard = <IO_STANDARD_LVCMOS18>;
 437                 };
 438
 439                 conf-rx {
 440                         pins = "MIO52", "MIO53", "MIO55";
 441                         bias-high-impedance;
 442                 };
 443
 444                 conf-tx {
 445                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 446                                "MIO60", "MIO61", "MIO62", "MIO63";
 447                         bias-disable;
 448                 };
 449         };
 450
 451         pinctrl_usb1_default: usb1-default {
 452                 mux {
 453                         groups = "usb1_0_grp";
 454                         function = "usb1";
 455                 };
 456
 457                 conf {
 458                         groups = "usb1_0_grp";
 459                         slew-rate = <SLEW_RATE_SLOW>;
 460                         io-standard = <IO_STANDARD_LVCMOS18>;
 461                 };
 462
 463                 conf-rx {
 464                         pins = "MIO64", "MIO65", "MIO67";
 465                         bias-high-impedance;
 466                 };
 467
 468                 conf-tx {
 469                         pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
 470                                "MIO72", "MIO73", "MIO74", "MIO75";
 471                         bias-disable;
 472                 };
 473         };
 474 };
 475
 476 &rtc {
 477         status = "okay";
 478 };
 479
 480 /* SD0 only supports 3.3V, no level shifter */
 481 &sdhci0 {
 482         status = "okay";
 483         no-1-8-v;
 484         broken-cd; /* CD has to be enabled by default */
 485         disable-wp;
 486         pinctrl-names = "default";
 487         pinctrl-0 = <&pinctrl_sdhci0_default>;
 488         xlnx,mio_bank = <0>;
 489 };
 490
 491 &sdhci1 {
 492         status = "okay";
 493         bus-width = <0x4>;
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&pinctrl_sdhci1_default>;
 496         xlnx,mio_bank = <0>;
 497         non-removable;
 498         disable-wp;
 499         cap-power-off-card;
 500         mmc-pwrseq = <&sdio_pwrseq>;
 501         vqmmc-supply = <&wmmcsdio_fixed>;
 502         #address-cells = <1>;
 503         #size-cells = <0>;
 504         wlcore: wlcore@2 {
 505                 compatible = "ti,wl1831";
 506                 reg = <2>;
 507                 interrupt-parent = <&gpio>;
 508                 interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
 509         };
 510 };
 511
 512 &serdes {
 513         status = "okay";
 514 };
 515
 516 &spi0 { /* Low Speed connector */
 517         status = "okay";
 518         pinctrl-names = "default";
 519         pinctrl-0 = <&pinctrl_spi0_default>;
 520 };
 521
 522 &spi1 { /* High Speed connector */
 523         status = "okay";
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&pinctrl_spi1_default>;
 526 };
 527
 528 &uart0 {
 529         status = "okay";
 530         pinctrl-names = "default";
 531         pinctrl-0 = <&pinctrl_uart0_default>;
 532         bluetooth {
 533                 compatible = "ti,wl1831-st";
 534                 enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
 535         };
 536
 537 };
 538
 539 &uart1 {
 540         status = "okay";
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&pinctrl_uart1_default>;
 543
 544 };
 545
 546 /* ULPI SMSC USB3320 */
 547 &usb0 {
 548         status = "okay";
 549         pinctrl-names = "default";
 550         pinctrl-0 = <&pinctrl_usb0_default>;
 551 };
 552
 553 &dwc3_0 {
 554         status = "okay";
 555         dr_mode = "peripheral";
 556         phy-names = "usb3-phy";
 557         phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;
 558         maximum-speed = "super-speed";
 559 };
 560
 561 /* ULPI SMSC USB3320 */
 562 &usb1 {
 563         status = "okay";
 564         pinctrl-names = "default";
 565         pinctrl-0 = <&pinctrl_usb1_default>;
 566 };
 567
 568 &dwc3_1 {
 569         status = "okay";
 570         dr_mode = "host";
 571         phy-names = "usb3-phy";
 572         phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;
 573         maximum-speed = "super-speed";
 574 };
 575
 576 &watchdog0 {
 577         status = "okay";
 578 };
 579
 580 &zynqmp_dpsub {
 581         status = "okay";
 582         phy-names = "dp-phy0", "dp-phy1";
 583         phys = <&lane1 PHY_TYPE_DP 0 1 27000000>,
 584                <&lane0 PHY_TYPE_DP 1 1 27000000>;
 585 };
 586
 587 &zynqmp_dp_snd_pcm0 {
 588         status = "okay";
 589 };
 590
 591 &zynqmp_dp_snd_pcm1 {
 592         status = "okay";
 593 };
 594
 595 &zynqmp_dp_snd_card0 {
 596         status = "okay";
 597 };
 598
 599 &zynqmp_dp_snd_codec0 {
 600         status = "okay";
 601 };
 602
 603 &xlnx_dpdma {
 604         status = "okay";
 605 };
 606
 607 &xilinx_ams {
 608         status = "okay";
 609 };
 610
 611 &ams_ps {
 612         status = "okay";
 613 };