2 * JZ4780 BCH controller
4 * Copyright (c) 2015 Imagination Technologies
5 * Author: Alex Smith <alex.smith@imgtec.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
25 #include "jz4780_bch.h"
31 #define BCH_BHPAR0 0x14
32 #define BCH_BHERR0 0x84
33 #define BCH_BHINT 0x184
34 #define BCH_BHINTES 0x188
35 #define BCH_BHINTEC 0x18c
36 #define BCH_BHINTE 0x190
38 #define BCH_BHCR_BSEL_SHIFT 4
39 #define BCH_BHCR_BSEL_MASK (0x7f << BCH_BHCR_BSEL_SHIFT)
40 #define BCH_BHCR_ENCE BIT(2)
41 #define BCH_BHCR_INIT BIT(1)
42 #define BCH_BHCR_BCHE BIT(0)
44 #define BCH_BHCNT_PARITYSIZE_SHIFT 16
45 #define BCH_BHCNT_PARITYSIZE_MASK (0x7f << BCH_BHCNT_PARITYSIZE_SHIFT)
46 #define BCH_BHCNT_BLOCKSIZE_SHIFT 0
47 #define BCH_BHCNT_BLOCKSIZE_MASK (0x7ff << BCH_BHCNT_BLOCKSIZE_SHIFT)
49 #define BCH_BHERR_MASK_SHIFT 16
50 #define BCH_BHERR_MASK_MASK (0xffff << BCH_BHERR_MASK_SHIFT)
51 #define BCH_BHERR_INDEX_SHIFT 0
52 #define BCH_BHERR_INDEX_MASK (0x7ff << BCH_BHERR_INDEX_SHIFT)
54 #define BCH_BHINT_ERRC_SHIFT 24
55 #define BCH_BHINT_ERRC_MASK (0x7f << BCH_BHINT_ERRC_SHIFT)
56 #define BCH_BHINT_TERRC_SHIFT 16
57 #define BCH_BHINT_TERRC_MASK (0x7f << BCH_BHINT_TERRC_SHIFT)
58 #define BCH_BHINT_DECF BIT(3)
59 #define BCH_BHINT_ENCF BIT(2)
60 #define BCH_BHINT_UNCOR BIT(1)
61 #define BCH_BHINT_ERR BIT(0)
63 #define BCH_CLK_RATE (200 * 1000 * 1000)
65 /* Timeout for BCH calculation/correction. */
66 #define BCH_TIMEOUT_US 100000
75 static void jz4780_bch_init(struct jz4780_bch *bch,
76 struct jz4780_bch_params *params, bool encode)
80 /* Clear interrupt status. */
81 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
83 /* Set up BCH count register. */
84 reg = params->size << BCH_BHCNT_BLOCKSIZE_SHIFT;
85 reg |= params->bytes << BCH_BHCNT_PARITYSIZE_SHIFT;
86 writel(reg, bch->base + BCH_BHCNT);
88 /* Initialise and enable BCH. */
89 reg = BCH_BHCR_BCHE | BCH_BHCR_INIT;
90 reg |= params->strength << BCH_BHCR_BSEL_SHIFT;
93 writel(reg, bch->base + BCH_BHCR);
96 static void jz4780_bch_disable(struct jz4780_bch *bch)
98 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
99 writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR);
102 static void jz4780_bch_write_data(struct jz4780_bch *bch, const void *buf,
105 size_t size32 = size / sizeof(u32);
106 size_t size8 = size % sizeof(u32);
110 src32 = (const u32 *)buf;
112 writel(*src32++, bch->base + BCH_BHDR);
114 src8 = (const u8 *)src32;
116 writeb(*src8++, bch->base + BCH_BHDR);
119 static void jz4780_bch_read_parity(struct jz4780_bch *bch, void *buf,
122 size_t size32 = size / sizeof(u32);
123 size_t size8 = size % sizeof(u32);
130 *dest32++ = readl(bch->base + BCH_BHPAR0 + offset);
131 offset += sizeof(u32);
134 dest8 = (u8 *)dest32;
135 val = readl(bch->base + BCH_BHPAR0 + offset);
138 dest8[2] = (val >> 16) & 0xff;
141 dest8[1] = (val >> 8) & 0xff;
144 dest8[0] = val & 0xff;
149 static bool jz4780_bch_wait_complete(struct jz4780_bch *bch, unsigned int irq,
156 * While we could use interrupts here and sleep until the operation
157 * completes, the controller works fairly quickly (usually a few
158 * microseconds) and so the overhead of sleeping until we get an
159 * interrupt quite noticeably decreases performance.
161 ret = readl_poll_timeout(bch->base + BCH_BHINT, reg,
162 (reg & irq) == irq, 0, BCH_TIMEOUT_US);
169 writel(reg, bch->base + BCH_BHINT);
174 * jz4780_bch_calculate() - calculate ECC for a data buffer
176 * @params: BCH parameters.
177 * @buf: input buffer with raw data.
178 * @ecc_code: output buffer with ECC.
180 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for BCH
183 int jz4780_bch_calculate(struct jz4780_bch *bch, struct jz4780_bch_params *params,
184 const u8 *buf, u8 *ecc_code)
188 mutex_lock(&bch->lock);
189 jz4780_bch_init(bch, params, true);
190 jz4780_bch_write_data(bch, buf, params->size);
192 if (jz4780_bch_wait_complete(bch, BCH_BHINT_ENCF, NULL)) {
193 jz4780_bch_read_parity(bch, ecc_code, params->bytes);
195 dev_err(bch->dev, "timed out while calculating ECC\n");
199 jz4780_bch_disable(bch);
200 mutex_unlock(&bch->lock);
203 EXPORT_SYMBOL(jz4780_bch_calculate);
206 * jz4780_bch_correct() - detect and correct bit errors
208 * @params: BCH parameters.
209 * @buf: raw data read from the chip.
210 * @ecc_code: ECC read from the chip.
212 * Given the raw data and the ECC read from the NAND device, detects and
213 * corrects errors in the data.
215 * Return: the number of bit errors corrected, -EBADMSG if there are too many
216 * errors to correct or -ETIMEDOUT if we timed out waiting for the controller.
218 int jz4780_bch_correct(struct jz4780_bch *bch, struct jz4780_bch_params *params,
219 u8 *buf, u8 *ecc_code)
221 u32 reg, mask, index;
224 mutex_lock(&bch->lock);
226 jz4780_bch_init(bch, params, false);
227 jz4780_bch_write_data(bch, buf, params->size);
228 jz4780_bch_write_data(bch, ecc_code, params->bytes);
230 if (!jz4780_bch_wait_complete(bch, BCH_BHINT_DECF, ®)) {
231 dev_err(bch->dev, "timed out while correcting data\n");
236 if (reg & BCH_BHINT_UNCOR) {
237 dev_warn(bch->dev, "uncorrectable ECC error\n");
242 /* Correct any detected errors. */
243 if (reg & BCH_BHINT_ERR) {
244 count = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT;
245 ret = (reg & BCH_BHINT_TERRC_MASK) >> BCH_BHINT_TERRC_SHIFT;
247 for (i = 0; i < count; i++) {
248 reg = readl(bch->base + BCH_BHERR0 + (i * 4));
249 mask = (reg & BCH_BHERR_MASK_MASK) >>
250 BCH_BHERR_MASK_SHIFT;
251 index = (reg & BCH_BHERR_INDEX_MASK) >>
252 BCH_BHERR_INDEX_SHIFT;
253 buf[(index * 2) + 0] ^= mask;
254 buf[(index * 2) + 1] ^= mask >> 8;
261 jz4780_bch_disable(bch);
262 mutex_unlock(&bch->lock);
265 EXPORT_SYMBOL(jz4780_bch_correct);
268 * jz4780_bch_get() - get the BCH controller device
269 * @np: BCH device tree node.
271 * Gets the BCH controller device from the specified device tree node. The
272 * device must be released with jz4780_bch_release() when it is no longer being
275 * Return: a pointer to jz4780_bch, errors are encoded into the pointer.
276 * PTR_ERR(-EPROBE_DEFER) if the device hasn't been initialised yet.
278 static struct jz4780_bch *jz4780_bch_get(struct device_node *np)
280 struct platform_device *pdev;
281 struct jz4780_bch *bch;
283 pdev = of_find_device_by_node(np);
285 return ERR_PTR(-EPROBE_DEFER);
287 bch = platform_get_drvdata(pdev);
289 put_device(&pdev->dev);
290 return ERR_PTR(-EPROBE_DEFER);
293 clk_prepare_enable(bch->clk);
299 * of_jz4780_bch_get() - get the BCH controller from a DT node
300 * @of_node: the node that contains a bch-controller property.
302 * Get the bch-controller property from the given device tree
303 * node and pass it to jz4780_bch_get to do the work.
305 * Return: a pointer to jz4780_bch, errors are encoded into the pointer.
306 * PTR_ERR(-EPROBE_DEFER) if the device hasn't been initialised yet.
308 struct jz4780_bch *of_jz4780_bch_get(struct device_node *of_node)
310 struct jz4780_bch *bch = NULL;
311 struct device_node *np;
313 np = of_parse_phandle(of_node, "ingenic,bch-controller", 0);
316 bch = jz4780_bch_get(np);
321 EXPORT_SYMBOL(of_jz4780_bch_get);
324 * jz4780_bch_release() - release the BCH controller device
327 void jz4780_bch_release(struct jz4780_bch *bch)
329 clk_disable_unprepare(bch->clk);
330 put_device(bch->dev);
332 EXPORT_SYMBOL(jz4780_bch_release);
334 static int jz4780_bch_probe(struct platform_device *pdev)
336 struct device *dev = &pdev->dev;
337 struct jz4780_bch *bch;
338 struct resource *res;
340 bch = devm_kzalloc(dev, sizeof(*bch), GFP_KERNEL);
344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
345 bch->base = devm_ioremap_resource(dev, res);
346 if (IS_ERR(bch->base))
347 return PTR_ERR(bch->base);
349 jz4780_bch_disable(bch);
351 bch->clk = devm_clk_get(dev, NULL);
352 if (IS_ERR(bch->clk)) {
353 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(bch->clk));
354 return PTR_ERR(bch->clk);
357 clk_set_rate(bch->clk, BCH_CLK_RATE);
359 mutex_init(&bch->lock);
362 platform_set_drvdata(pdev, bch);
367 static const struct of_device_id jz4780_bch_dt_match[] = {
368 { .compatible = "ingenic,jz4780-bch" },
371 MODULE_DEVICE_TABLE(of, jz4780_bch_dt_match);
373 static struct platform_driver jz4780_bch_driver = {
374 .probe = jz4780_bch_probe,
376 .name = "jz4780-bch",
377 .of_match_table = of_match_ptr(jz4780_bch_dt_match),
380 module_platform_driver(jz4780_bch_driver);
382 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
383 MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
384 MODULE_DESCRIPTION("Ingenic JZ4780 BCH error correction driver");
385 MODULE_LICENSE("GPL v2");