drm: xilinx: dp: Add delay after Monitor wake up

Some monitors require delay to fully wake up. Otherwise, it may
result in some error such as training failure.

Delay of 4 msec was not specified in the spec, but found from
experimentation (ex, no failure for 20 times or more). Thus,
this setting is exposed as module parameter so that user can
change if needed.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_dp.c b/drivers/gpu/drm/xilinx/xilinx_drm_dp.c
index 7eb7515ecafa36a9754ebb5169d20a4001753dbd..efadb6569eb8c628a9a91756e19f9c6f29da0c7b 100644 (file)
--- a/drivers/gpu/drm/xilinx/xilinx_drm_dp.c
+++ b/drivers/gpu/drm/xilinx/xilinx_drm_dp.c
@@ -41,6 +41,12 @@ module_param_named(aux_timeout_ms, xilinx_drm_dp_aux_timeout_ms, uint, 0444);
 MODULE_PARM_DESC(aux_timeout_ms,
                 "DP aux timeout value in msec (default: 50)");
 
+static uint xilinx_drm_dp_power_on_delay_ms = 4;
+module_param_named(power_on_delay_ms, xilinx_drm_dp_power_on_delay_ms, uint,
+                  0644);
+MODULE_PARM_DESC(power_on_delay,
+                "Delay after power on request in msec (default: 4)");
+
 /* Link configuration registers */
 #define XILINX_DP_TX_LINK_BW_SET                       0x0
 #define XILINX_DP_TX_LANE_CNT_SET                      0x4
@@ -1416,7 +1422,8 @@ static void xilinx_drm_dp_dpms(struct drm_encoder *encoder, int dpms)
                                break;
                        usleep_range(300, 500);
                }
-
+               /* Some monitors take time to wake up properly */
+               msleep(xilinx_drm_dp_power_on_delay_ms);
                if (ret != 1)
                        dev_dbg(dp->dev, "DP aux failed\n");
                else