phy: zynqmp: Use the configured GT lane for tx_term_fix calibration

This is a small correction to
"phy: zynqmp: Change serdes calibraton logic to ICM_CFG1"
(sha1: c1c13c82fbff75d1e4fb19b8ebfc27ea75656c2d)

During the calibration process ICM_CFG register should be set to any
valid lane. The previous version was using hardcoded setting of PCIe
for lane 2 and 3. This breaks other devices on these lanes if they
don't configure the phy in Linux (i.e. expect the value to be configured
in FSBL).

Current version will use the ICM_CFG value for the first selected phy
instead of hardcoding lanes 2 and 3 to PCIe.

Signed-off-by: Edgar Lakis <ela@phaseone.com>
Acked-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c
index 908235dd11747d2aebed88a24beecbe448964bb3..37c54435bb15634e0b7df2c78ecba130583abd41 100644 (file)
--- a/drivers/phy/phy-zynqmp.c
+++ b/drivers/phy/phy-zynqmp.c
@@ -154,8 +154,6 @@
 #define PROT_BUS_WIDTH_20              0x1
 #define PROT_BUS_WIDTH_40              0x2
 
-#define TX_TERM_FIX_VAL                        0x11
-
 #define LANE_CLK_SHARE_MASK            0x8F
 
 #define SATA_CONTROL_OFFSET            0x0100
@@ -1008,7 +1006,7 @@ static int xpsgtr_phy_init(struct phy *phy)
                 * we need to configure any lane ICM_CFG to valid protocol. This
                 * will deassert the CMN_Resetn signal.
                 */
-               writel(TX_TERM_FIX_VAL, gtr_dev->serdes + ICM_CFG1);
+               xpsgtr_lane_setprotocol(gtr_phy);
 
                /* Clear Test Mode reset */
                reg = readl(gtr_dev->serdes + TM_CMN_RST);