dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revB-loopback.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
/*
- * dts file for Xilinx ZynqMP ZCU102
+ * dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015, Xilinx, Inc.
*
/ {
model = "ZynqMP ZCU102 RevA";
- compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
* the License, or (at your option) any later version.
*/
-#include "zynqmp-zcu102.dts"
+#include "zynqmp-zcu102-revA.dts"
/ {
model = "ZynqMP ZCU102 RevB";
+ compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
&gem3 {