bp->phc_index = ptp_clock_index(bp->ptp_clock);
}
-/*
- * Configure the receive DMA engine
+/* Configure the receive DMA engine
* - use the correct receive buffer size
* - set best burst length for DMA operations
* (if not supported by FIFO, it will fallback to default)
of_property_read_u32(pdev->dev.of_node, "tsu-clk", &bp->tsu_clk);
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
- if (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1)) > GEM_DBW32)
- dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
-#endif
-
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
if (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1)) > GEM_DBW32)
dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
netif_carrier_off(dev);
tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
- (unsigned long) bp);
+ (unsigned long)bp);
netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),