xilinx_drm_writel(vtc->base, VTC_CTL, reg | VTC_CTL_RU);
}
+/* enable vblank interrupt */
+void xilinx_vtc_vblank_enable(struct xilinx_vtc *vtc)
+{
+ xilinx_drm_writel(vtc->base, VTC_IER, VTC_IXR_G_VBLANK |
+ xilinx_drm_readl(vtc->base, VTC_IER));
+}
+EXPORT_SYMBOL_GPL(xilinx_vtc_vblank_enable);
+
/* enable interrupt */
static inline void xilinx_vtc_intr_enable(struct xilinx_vtc *vtc, u32 intr)
{
xilinx_drm_readl(vtc->base, VTC_IER));
}
+/* disable vblank interrupt */
+void xilinx_vtc_vblank_disable(struct xilinx_vtc *vtc)
+{
+ xilinx_drm_writel(vtc->base, VTC_IER, ~(VTC_IXR_G_VBLANK) &
+ xilinx_drm_readl(vtc->base, VTC_IER));
+}
+EXPORT_SYMBOL_GPL(xilinx_vtc_vblank_disable);
+
/* get interrupt */
-static inline u32 xilinx_vtc_intr_get(struct xilinx_vtc *vtc)
+u32 xilinx_vtc_intr_get(struct xilinx_vtc *vtc)
{
return xilinx_drm_readl(vtc->base, VTC_IER) &
xilinx_drm_readl(vtc->base, VTC_ISR) & VTC_IXR_ALLINTR_MASK;
}
+EXPORT_SYMBOL_GPL(xilinx_vtc_intr_get);
/* clear interrupt */
-static inline void xilinx_vtc_intr_clear(struct xilinx_vtc *vtc, u32 intr)
+void xilinx_vtc_intr_clear(struct xilinx_vtc *vtc, u32 intr)
{
xilinx_drm_writel(vtc->base, VTC_ISR, intr & VTC_IXR_ALLINTR_MASK);
}
+EXPORT_SYMBOL_GPL(xilinx_vtc_intr_clear);
/* interrupt handler */
static irqreturn_t xilinx_vtc_intr_handler(int irq, void *data)
struct xilinx_vtc *xilinx_vtc_probe(struct device *dev,
struct device_node *node);
+void xilinx_vtc_vblank_enable(struct xilinx_vtc *vtc);
+void xilinx_vtc_vblank_disable(struct xilinx_vtc *vtc);
+u32 xilinx_vtc_intr_get(struct xilinx_vtc *vtc);
+void xilinx_vtc_intr_clear(struct xilinx_vtc *vtc, u32 intr);
#endif /* _XILINX_VTC_H_ */