#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
+#define XAE_EMMC_LINKSPD_2500 0x80000000 /* Link Speed mask for 2500 Mbit */
/* Bit masks for Axi Ethernet PHYC register */
#define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
* enum axienet_ip_type - AXIENET IP/MAC type.
*
* @XAXIENET_1G: IP is 1G MAC
+ * @XAXIENET_2_5G: IP type is 2.5G MAC.
* @XAXIENET_LEGACY_10G: IP type is legacy 10G MAC.
* @XAXIENET_10G_25G: IP type is 10G/25G MAC(XXV MAC).
*
*/
enum axienet_ip_type {
XAXIENET_1G = 0,
+ XAXIENET_2_5G,
XAXIENET_LEGACY_10G,
XAXIENET_10G_25G,
};
if (!is_valid_ether_addr(ndev->dev_addr))
eth_random_addr(ndev->dev_addr);
- if (lp->axienet_config->mactype != XAXIENET_1G)
+ if (lp->axienet_config->mactype != XAXIENET_1G &&
+ lp->axienet_config->mactype != XAXIENET_2_5G)
return;
/* Set up unicast MAC address filter set its mac address */
emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
switch (phy->speed) {
+ case SPEED_2500:
+ emmc_reg |= XAE_EMMC_LINKSPD_2500;
case SPEED_1000:
emmc_reg |= XAE_EMMC_LINKSPD_1000;
break;
buf[3] = (cur_p->ptp_tx_ts_tag >> 8) & 0xFF;
}
- if (lp->axienet_config->mactype == XAXIENET_1G) {
+ if (lp->axienet_config->mactype == XAXIENET_1G ||
+ lp->axienet_config->mactype == XAXIENET_2_5G) {
memcpy(&val, buf, AXIENET_TS_HEADER_LEN);
swab64s(&val);
memcpy(buf, &val, AXIENET_TS_HEADER_LEN);
u64 time64;
struct skb_shared_hwtstamps *shhwtstamps;
- if (lp->axienet_config->mactype == XAXIENET_1G) {
+ if (lp->axienet_config->mactype == XAXIENET_1G ||
+ lp->axienet_config->mactype == XAXIENET_2_5G) {
/* The first 8 bytes will be the timestamp */
memcpy(&sec, &skb->data[0], 4);
memcpy(&nsec, &skb->data[4], 4);
if (ret < 0)
return ret;
- if (lp->phy_node && (lp->axienet_config->mactype == XAXIENET_1G)) {
+ if (lp->phy_node && ((lp->axienet_config->mactype == XAXIENET_1G) ||
+ (lp->axienet_config->mactype == XAXIENET_2_5G))) {
lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
axienet_adjust_link, lp->phy_flags,
lp->phy_interface);
.tx_ptplen = XAE_TX_PTP_LEN,
};
+static const struct axienet_config axienet_2_5g_config = {
+ .mactype = XAXIENET_2_5G,
+ .setoptions = axienet_setoptions,
+ .tx_ptplen = XAE_TX_PTP_LEN,
+};
+
static const struct axienet_config axienet_10g_config = {
.mactype = XAXIENET_LEGACY_10G,
.setoptions = axienet_setoptions,
{ .compatible = "xlnx,axi-ethernet-1.00.a", .data = &axienet_1g_config},
{ .compatible = "xlnx,axi-ethernet-1.01.a", .data = &axienet_1g_config},
{ .compatible = "xlnx,axi-ethernet-2.01.a", .data = &axienet_1g_config},
+ { .compatible = "xlnx,axi-2_5-gig-ethernet-1.0",
+ .data = &axienet_2_5g_config},
{ .compatible = "xlnx,ten-gig-eth-mac", .data = &axienet_10g_config},
{ .compatible = "xlnx,xxv-ethernet-1.0",
.data = &axienet_10g25g_config},