devicetree: bindings: Added documentation for xilinx axi Uartlite

This patch adds device-tree bindings for xilinx axi uartlite core.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/serial/uartlite.c b/Documentation/devicetree/bindings/serial/uartlite.c
new file mode 100644 (file)
index 0000000..df8aba0
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/uartlite.c
@@ -0,0 +1,24 @@
+Xilinx Axi Uartlite controller Device Tree Bindings
+---------------------------------------------------------
+
+Required properties:
+- compatible           : Can be either of
+                               "xlnx,xps-uartlite-1.00.a"
+                               "xlnx,opb-uartlite-1.00.b"
+- reg                  : Physical base address and size of the Axi Uartlite
+                         registers map.
+- interrupts           : Property with a value describing the interrupt
+                         number.
+- interrupt-parent     : Must be core interrupt controller.
+
+Optional properties:
+- port-number          : Set Uart port number
+
+Example:
+serial@800C0000 {
+       compatible = "xlnx,xps-uartlite-1.00.a";
+       reg = <0x0 0x800c0000 0x10000>;
+       interrupt-parent = <&gic>;
+       interrupts = <0x0 0x6e 0x1>;
+       port-number = <0>;
+};