devicetree: Add GUCTL1 flags for USB dwc3 controller

This patch updates the device tree binding properties for programming
GUCTL1 register bit 9 & 10 for adding HW workarounds in dwc3 controller.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 92a27316336c4c337a64e05b2dc985a6ea11579a..7058daee6fac8babb8934e02a076b28f948d7765 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -973,6 +973,8 @@
                                interrupts = <0 65 4>, <0 69 4>;
                                snps,quirk-frame-length-adjustment = <0x20>;
                                snps,refclk_fladj;
+                               snps,enable_guctl1_resume_quirk;
+                               snps,enable_guctl1_ipd_quirk;
                                /* dma-coherent; */
                        };
                };
@@ -999,6 +1001,8 @@
                                interrupts = <0 70 4>, <0 74 4>;
                                snps,quirk-frame-length-adjustment = <0x20>;
                                snps,refclk_fladj;
+                               snps,enable_guctl1_resume_quirk;
+                               snps,enable_guctl1_ipd_quirk;
                                /* dma-coherent; */
                        };
                };