arm64: zynqmp: Add dtses for zc1751 dc3/dc4 configurations

Add missing dtses for dc cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 4fe8e2d42e1ee901b53e9caed11b982a728b14e9..b42c4a74186d88fbebc9dedb64ed4e33472e1198 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,6 +1,8 @@
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revB.dtb

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644 (file)
index 0000000..3da9bd2
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,224 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+       model = "ZynqMP zc1751-xm017-dc3 RevA";
+       compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+       aliases {
+               ethernet0 = &gem0;
+               gpio0 = &gpio;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               mmc0 = &sdhci1;
+               rtc0 = &rtc;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               usb0 = &usb0;
+               usb1 = &usb1;
+       };
+
+       chosen {
+               bootargs = "earlycon";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+       };
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+       xlnx,overfetch; /* for testing purpose */
+       xlnx,ratectrl = <0>; /* for testing purpose */
+       xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+       status = "okay";
+       xlnx,ratectrl = <100>; /* for testing purpose */
+       xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+       status = "okay";
+};
+
+&fpd_dma_chan4 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+       status = "okay";
+};
+
+&fpd_dma_chan6 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+       status = "okay";
+};
+
+&fpd_dma_chan8 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&gem0 {
+       status = "okay";
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       phy0: phy@0 { /* VSC8211 */
+               reg = <0>;
+       };
+};
+
+&gpio {
+       status = "okay";
+};
+
+/* just eeprom here */
+&i2c0 {
+       status = "okay";
+       clock-frequency = <400000>;
+
+       tca6416_u26: gpio@20 {
+               compatible = "ti,tca6416";
+               reg = <0x20>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               /* IRQ not connected */
+       };
+
+       rtc@68 {
+               compatible = "dallas,ds1339";
+               reg = <0x68>;
+       };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+&i2c1 {
+       status = "okay";
+       clock-frequency = <400000>;
+};
+
+/* MT29F64G08AECDBJ4-6 */
+&nand0 {
+       status = "okay";
+       arasan,has-mdma;
+       num-cs = <2>;
+
+       partition@0 {   /* for testing purpose */
+               label = "nand-fsbl-uboot";
+               reg = <0x0 0x0 0x400000>;
+       };
+       partition@1 {   /* for testing purpose */
+               label = "nand-linux";
+               reg = <0x0 0x400000 0x1400000>;
+       };
+       partition@2 {   /* for testing purpose */
+               label = "nand-device-tree";
+               reg = <0x0 0x1800000 0x400000>;
+       };
+       partition@3 {   /* for testing purpose */
+               label = "nand-rootfs";
+               reg = <0x0 0x1C00000 0x1400000>;
+       };
+       partition@4 {   /* for testing purpose */
+               label = "nand-bitstream";
+               reg = <0x0 0x3000000 0x400000>;
+       };
+       partition@5 {   /* for testing purpose */
+               label = "nand-misc";
+               reg = <0x0 0x3400000 0xFCC00000>;
+       };
+
+       partition@6 {   /* for testing purpose */
+               label = "nand1-fsbl-uboot";
+               reg = <0x1 0x0 0x400000>;
+       };
+       partition@7 {   /* for testing purpose */
+               label = "nand1-linux";
+               reg = <0x1 0x400000 0x1400000>;
+       };
+       partition@8 {   /* for testing purpose */
+               label = "nand1-device-tree";
+               reg = <0x1 0x1800000 0x400000>;
+       };
+       partition@9 {   /* for testing purpose */
+               label = "nand1-rootfs";
+               reg = <0x1 0x1C00000 0x1400000>;
+       };
+       partition@10 {  /* for testing purpose */
+               label = "nand1-bitstream";
+               reg = <0x1 0x3000000 0x400000>;
+       };
+       partition@11 {  /* for testing purpose */
+               label = "nand1-misc";
+               reg = <0x1 0x3400000 0xFCC00000>;
+       };
+};
+
+&rtc {
+       status = "okay";
+};
+
+&sata {
+       status = "okay";
+       /* SATA phy OOB timing settings */
+       ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+       ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+       ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+       ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+       ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+       ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+       ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+       ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&sdhci1 { /* emmc with some settings */
+       status = "okay";
+};
+
+/* main */
+&uart0 {
+       status = "okay";
+};
+
+/* DB9 */
+&uart1 {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+       dr_mode = "host";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+       status = "okay";
+       dr_mode = "host";
+};

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644 (file)
index 0000000..ab2e2f2
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,208 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+       model = "ZynqMP zc1751-xm018-dc4";
+       compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+       aliases {
+               can0 = &can0;
+               can1 = &can1;
+               ethernet0 = &gem0;
+               ethernet1 = &gem1;
+               ethernet2 = &gem2;
+               ethernet3 = &gem3;
+               gpio0 = &gpio;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               rtc0 = &rtc;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               spi0 = &qspi;
+       };
+
+       chosen {
+               bootargs = "earlycon";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+       };
+};
+
+&can0 {
+       status = "okay";
+};
+
+&can1 {
+       status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+       xlnx,overfetch; /* for testing purpose */
+       xlnx,ratectrl = <0>; /* for testing purpose */
+       xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+       status = "okay";
+       xlnx,ratectrl = <100>; /* for testing purpose */
+       xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+       status = "okay";
+};
+
+&fpd_dma_chan4 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+       status = "okay";
+};
+
+&fpd_dma_chan6 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+       status = "okay";
+};
+
+&fpd_dma_chan8 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&lpd_dma_chan1 {
+       status = "okay";
+};
+
+&lpd_dma_chan2 {
+       status = "okay";
+};
+
+&lpd_dma_chan3 {
+       status = "okay";
+};
+
+&lpd_dma_chan4 {
+       status = "okay";
+};
+
+&lpd_dma_chan5 {
+       status = "okay";
+};
+
+&lpd_dma_chan6 {
+       status = "okay";
+};
+
+&lpd_dma_chan7 {
+       status = "okay";
+};
+
+&lpd_dma_chan8 {
+       status = "okay";
+};
+
+&xlnx_dp {
+       status = "okay";
+};
+
+&xlnx_dpdma {
+       status = "okay";
+};
+
+&gem0 {
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethernet_phy0>;
+       ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+               reg = <0>;
+       };
+       ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+               reg = <7>;
+       };
+       ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+               reg = <3>;
+       };
+       ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+               reg = <8>;
+       };
+};
+
+&gem1 {
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethernet_phy7>;
+};
+
+&gem2 {
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethernet_phy3>;
+};
+
+&gem3 {
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethernet_phy8>;
+};
+
+&gpio {
+       status = "okay";
+};
+
+&gpu {
+       status = "okay";
+};
+
+&i2c0 {
+       clock-frequency = <400000>;
+       status = "okay";
+};
+
+&i2c1 {
+       clock-frequency = <400000>;
+       status = "okay";
+};
+
+&rtc {
+       status = "okay";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&watchdog0 {
+       status = "okay";
+};