drivers/mmc/host/sdhci-of-arasan.c

   1 /*
   2  * Arasan Secure Digital Host Controller Interface.
   3  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
   4  * Copyright (c) 2012 Wind River Systems, Inc.
   5  * Copyright (C) 2013 Pengutronix e.K.
   6  * Copyright (C) 2013 Xilinx Inc.
   7  *
   8  * Based on sdhci-of-esdhc.c
   9  *
  10  * Copyright (c) 2007 Freescale Semiconductor, Inc.
  11  * Copyright (c) 2009 MontaVista Software, Inc.
  12  *
  13  * Authors: Xiaobo Xie <X.Xie@freescale.com>
  14  *          Anton Vorontsov <avorontsov@ru.mvista.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or (at
  19  * your option) any later version.
  20  */
  21
  22 #include <linux/clk-provider.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/module.h>
  25 #include <linux/delay.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/phy/phy.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/soc/xilinx/zynqmp/tap_delays.h>
  31 #include <linux/soc/xilinx/zynqmp/fw.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/regmap.h>
  34 #include "sdhci-pltfm.h"
  35 #include <linux/of.h>
  36 #include <linux/slab.h>
  37
  38 #define SDHCI_ARASAN_CLK_CTRL_OFFSET    0x2c
  39 #define SDHCI_ARASAN_VENDOR_REGISTER    0x78
  40
  41 #define VENDOR_ENHANCED_STROBE          BIT(0)
  42 #define CLK_CTRL_TIMEOUT_SHIFT          16
  43 #define CLK_CTRL_TIMEOUT_MASK           (0xf << CLK_CTRL_TIMEOUT_SHIFT)
  44 #define CLK_CTRL_TIMEOUT_MIN_EXP        13
  45 #define SD_CLK_25_MHZ                           25000000
  46 #define SD_CLK_19_MHZ                           19000000
  47 #define MAX_TUNING_LOOP 40
  48
  49 #define PHY_CLK_TOO_SLOW_HZ             400000
  50
  51 /*
  52  * On some SoCs the syscon area has a feature where the upper 16-bits of
  53  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
  54  * atomic updates of the register without locking.  This macro is used on SoCs
  55  * that have that feature.
  56  */
  57 #define HIWORD_UPDATE(val, mask, shift) \
  58                 ((val) << (shift) | (mask) << ((shift) + 16))
  59
  60 /**
  61  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
  62  *
  63  * @reg:        Offset within the syscon of the register containing this field
  64  * @width:      Number of bits for this field
  65  * @shift:      Bit offset within @reg of this field (or -1 if not avail)
  66  */
  67 struct sdhci_arasan_soc_ctl_field {
  68         u32 reg;
  69         u16 width;
  70         s16 shift;
  71 };
  72
  73 /**
  74  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
  75  *
  76  * It's up to the licensee of the Arsan IP block to make these available
  77  * somewhere if needed.  Presumably these will be scattered somewhere that's
  78  * accessible via the syscon API.
  79  *
  80  * @baseclkfreq:        Where to find corecfg_baseclkfreq
  81  * @clockmultiplier:    Where to find corecfg_clockmultiplier
  82  * @hiword_update:      If true, use HIWORD_UPDATE to access the syscon
  83  */
  84 struct sdhci_arasan_soc_ctl_map {
  85         struct sdhci_arasan_soc_ctl_field       baseclkfreq;
  86         struct sdhci_arasan_soc_ctl_field       clockmultiplier;
  87         bool                                    hiword_update;
  88 };
  89
  90 /**
  91  * struct sdhci_arasan_data
  92  * @host:               Pointer to the main SDHCI host structure.
  93  * @clk_ahb:            Pointer to the AHB clock
  94  * @phy:                Pointer to the generic phy
  95  * @is_phy_on:          True if the PHY is on; false if not.
  96  * @sdcardclk_hw:       Struct for the clock we might provide to a PHY.
  97  * @sdcardclk:          Pointer to normal 'struct clock' for sdcardclk_hw.
  98  * @soc_ctl_base:       Pointer to regmap for syscon for soc_ctl registers.
  99  * @soc_ctl_map:        Map to get offsets into soc_ctl registers.
 100  */
 101 struct sdhci_arasan_data {
 102         struct sdhci_host *host;
 103         struct clk      *clk_ahb;
 104         struct phy      *phy;
 105         u32 mio_bank;
 106         u32 device_id;
 107         bool            is_phy_on;
 108
 109         struct clk_hw   sdcardclk_hw;
 110         struct clk      *sdcardclk;
 111
 112         struct regmap   *soc_ctl_base;
 113         struct pinctrl *pinctrl;
 114         struct pinctrl_state *pins_default;
 115         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
 116         unsigned int    quirks; /* Arasan deviations from spec */
 117
 118 /* Controller does not have CD wired and will not function normally without */
 119 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
 120 };
 121
 122 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
 123         .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
 124         .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
 125         .hiword_update = true,
 126 };
 127
 128 /**
 129  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
 130  *
 131  * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
 132  * Note that if a field is specified as not available (shift < 0) then
 133  * this function will silently return an error code.  It will be noisy
 134  * and print errors for any other (unexpected) errors.
 135  *
 136  * @host:       The sdhci_host
 137  * @fld:        The field to write to
 138  * @val:        The value to write
 139  */
 140 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
 141                                    const struct sdhci_arasan_soc_ctl_field *fld,
 142                                    u32 val)
 143 {
 144         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 145         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 146         struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
 147         u32 reg = fld->reg;
 148         u16 width = fld->width;
 149         s16 shift = fld->shift;
 150         int ret;
 151
 152         /*
 153          * Silently return errors for shift < 0 so caller doesn't have
 154          * to check for fields which are optional.  For fields that
 155          * are required then caller needs to do something special
 156          * anyway.
 157          */
 158         if (shift < 0)
 159                 return -EINVAL;
 160
 161         if (sdhci_arasan->soc_ctl_map->hiword_update)
 162                 ret = regmap_write(soc_ctl_base, reg,
 163                                    HIWORD_UPDATE(val, GENMASK(width, 0),
 164                                                  shift));
 165         else
 166                 ret = regmap_update_bits(soc_ctl_base, reg,
 167                                          GENMASK(shift + width, shift),
 168                                          val << shift);
 169
 170         /* Yell about (unexpected) regmap errors */
 171         if (ret)
 172                 pr_warn("%s: Regmap write fail: %d\n",
 173                          mmc_hostname(host->mmc), ret);
 174
 175         return ret;
 176 }
 177
 178 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
 179 {
 180         u32 div;
 181         unsigned long freq;
 182         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 183
 184         div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
 185         div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
 186
 187         freq = clk_get_rate(pltfm_host->clk);
 188         freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
 189
 190         return freq;
 191 }
 192
 193 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
 194 {
 195         u16 clk;
 196         unsigned long timeout;
 197
 198         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 199         clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
 200         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 201
 202         /* Issue DLL Reset */
 203         zynqmp_dll_reset(deviceid);
 204
 205         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 206         clk |= SDHCI_CLOCK_INT_EN;
 207         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 208
 209         /* Wait max 20 ms */
 210         timeout = 20;
 211         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 212                                 & SDHCI_CLOCK_INT_STABLE)) {
 213                 if (timeout == 0) {
 214                         dev_err(mmc_dev(host->mmc),
 215                                 ": Internal clock never stabilised.\n");
 216                         return;
 217                 }
 218                 timeout--;
 219                 mdelay(1);
 220         }
 221
 222         clk |= SDHCI_CLOCK_CARD_EN;
 223         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 224 }
 225
 226 static int arasan_zynqmp_execute_tuning(struct sdhci_host *host, u32 opcode)
 227 {
 228         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 229         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 230         struct mmc_host *mmc = host->mmc;
 231         u16 ctrl;
 232         int tuning_loop_counter = MAX_TUNING_LOOP;
 233         int err = 0;
 234         unsigned long flags;
 235         unsigned int tuning_count = 0;
 236
 237         spin_lock_irqsave(&host->lock, flags);
 238
 239         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
 240                 tuning_count = host->tuning_count;
 241
 242         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 243         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 244         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
 245                 ctrl |= SDHCI_CTRL_TUNED_CLK;
 246         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 247
 248         mdelay(1);
 249
 250         arasan_zynqmp_dll_reset(host, sdhci_arasan->device_id);
 251
 252         /*
 253          * As per the Host Controller spec v3.00, tuning command
 254          * generates Buffer Read Ready interrupt, so enable that.
 255          *
 256          * Note: The spec clearly says that when tuning sequence
 257          * is being performed, the controller does not generate
 258          * interrupts other than Buffer Read Ready interrupt. But
 259          * to make sure we don't hit a controller bug, we _only_
 260          * enable Buffer Read Ready interrupt here.
 261          */
 262         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 263         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 264
 265         /*
 266          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
 267          * of loops reaches 40 times or a timeout of 150ms occurs.
 268          */
 269         do {
 270                 struct mmc_command cmd = {0};
 271                 struct mmc_request mrq = {NULL};
 272
 273                 cmd.opcode = opcode;
 274                 cmd.arg = 0;
 275                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 276                 cmd.retries = 0;
 277                 cmd.data = NULL;
 278                 cmd.mrq = &mrq;
 279                 cmd.error = 0;
 280
 281                 if (tuning_loop_counter-- == 0)
 282                         break;
 283
 284                 mrq.cmd = &cmd;
 285
 286                 /*
 287                  * In response to CMD19, the card sends 64 bytes of tuning
 288                  * block to the Host Controller. So we set the block size
 289                  * to 64 here.
 290                  */
 291                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
 292                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 293                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
 294                                              SDHCI_BLOCK_SIZE);
 295                         } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
 296                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
 297                                              SDHCI_BLOCK_SIZE);
 298                         }
 299                 } else {
 300                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
 301                                      SDHCI_BLOCK_SIZE);
 302                 }
 303
 304                 /*
 305                  * The tuning block is sent by the card to the host controller.
 306                  * So we set the TRNS_READ bit in the Transfer Mode register.
 307                  * This also takes care of setting DMA Enable and Multi Block
 308                  * Select in the same register to 0.
 309                  */
 310                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 311
 312                 sdhci_send_command(host, &cmd);
 313
 314                 host->cmd = NULL;
 315
 316                 spin_unlock_irqrestore(&host->lock, flags);
 317                 /* Wait for Buffer Read Ready interrupt */
 318                 wait_event_interruptible_timeout(host->buf_ready_int,
 319                                         (host->tuning_done == 1),
 320                                         msecs_to_jiffies(50));
 321                 spin_lock_irqsave(&host->lock, flags);
 322
 323                 if (!host->tuning_done) {
 324                         dev_warn(mmc_dev(host->mmc),
 325                                  ": Timeout for Buffer Read Ready interrupt, back to fixed sampling clock\n");
 326                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 327                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 328                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
 329                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 330
 331                         err = -EIO;
 332                         goto out;
 333                 }
 334
 335                 host->tuning_done = 0;
 336
 337                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 338
 339                 /* eMMC spec does not require a delay between tuning cycles */
 340                 if (opcode == MMC_SEND_TUNING_BLOCK)
 341                         mdelay(1);
 342         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 343
 344         /*
 345          * The Host Driver has exhausted the maximum number of loops allowed,
 346          * so use fixed sampling frequency.
 347          */
 348         if (tuning_loop_counter < 0) {
 349                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 350                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 351         }
 352         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 353                 dev_warn(mmc_dev(host->mmc),
 354                          ": Tuning failed, back to fixed sampling clock\n");
 355                 err = -EIO;
 356         } else {
 357                 arasan_zynqmp_dll_reset(host, sdhci_arasan->device_id);
 358         }
 359
 360 out:
 361         /*
 362          * In case tuning fails, host controllers which support
 363          * re-tuning can try tuning again at a later time, when the
 364          * re-tuning timer expires.  So for these controllers, we
 365          * return 0. Since there might be other controllers who do not
 366          * have this capability, we return error for them.
 367          */
 368         if (tuning_count)
 369                 err = 0;
 370
 371         host->mmc->retune_period = err ? 0 : tuning_count;
 372
 373         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 374         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 375         spin_unlock_irqrestore(&host->lock, flags);
 376
 377         return err;
 378 }
 379
 380 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
 381 {
 382         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 383         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 384         bool ctrl_phy = false;
 385
 386         if (!IS_ERR(sdhci_arasan->phy)) {
 387                 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
 388                         /*
 389                          * If PHY off, set clock to max speed and power PHY on.
 390                          *
 391                          * Although PHY docs apparently suggest power cycling
 392                          * when changing the clock the PHY doesn't like to be
 393                          * powered on while at low speeds like those used in ID
 394                          * mode.  Even worse is powering the PHY on while the
 395                          * clock is off.
 396                          *
 397                          * To workaround the PHY limitations, the best we can
 398                          * do is to power it on at a faster speed and then slam
 399                          * through low speeds without power cycling.
 400                          */
 401                         sdhci_set_clock(host, host->max_clk);
 402                         spin_unlock_irq(&host->lock);
 403                         phy_power_on(sdhci_arasan->phy);
 404                         spin_lock_irq(&host->lock);
 405                         sdhci_arasan->is_phy_on = true;
 406
 407                         /*
 408                          * We'll now fall through to the below case with
 409                          * ctrl_phy = false (so we won't turn off/on).  The
 410                          * sdhci_set_clock() will set the real clock.
 411                          */
 412                 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
 413                         /*
 414                          * At higher clock speeds the PHY is fine being power
 415                          * cycled and docs say you _should_ power cycle when
 416                          * changing clock speeds.
 417                          */
 418                         ctrl_phy = true;
 419                 }
 420         }
 421
 422         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN) &&
 423                 (host->version >= SDHCI_SPEC_300)) {
 424                 if (clock == SD_CLK_25_MHZ)
 425                         clock = SD_CLK_19_MHZ;
 426                 if ((host->timing != MMC_TIMING_LEGACY) &&
 427                         (host->timing != MMC_TIMING_UHS_SDR12))
 428                         arasan_zynqmp_set_tap_delay(sdhci_arasan->device_id,
 429                                                     host->timing,
 430                                                     sdhci_arasan->mio_bank);
 431         }
 432
 433         if (ctrl_phy && sdhci_arasan->is_phy_on) {
 434                 spin_unlock_irq(&host->lock);
 435                 phy_power_off(sdhci_arasan->phy);
 436                 spin_lock_irq(&host->lock);
 437                 sdhci_arasan->is_phy_on = false;
 438         }
 439
 440         sdhci_set_clock(host, clock);
 441
 442         if (ctrl_phy) {
 443                 spin_unlock_irq(&host->lock);
 444                 phy_power_on(sdhci_arasan->phy);
 445                 spin_lock_irq(&host->lock);
 446                 sdhci_arasan->is_phy_on = true;
 447         }
 448 }
 449
 450 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
 451                                         struct mmc_ios *ios)
 452 {
 453         u32 vendor;
 454         struct sdhci_host *host = mmc_priv(mmc);
 455
 456         vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
 457         if (ios->enhanced_strobe)
 458                 vendor |= VENDOR_ENHANCED_STROBE;
 459         else
 460                 vendor &= ~VENDOR_ENHANCED_STROBE;
 461
 462         writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
 463 }
 464
 465 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
 466 {
 467         u8 ctrl;
 468         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 469         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 470
 471         sdhci_reset(host, mask);
 472
 473         if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
 474                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 475                 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
 476                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 477         }
 478 }
 479
 480 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
 481                                        struct mmc_ios *ios)
 482 {
 483         switch (ios->signal_voltage) {
 484         case MMC_SIGNAL_VOLTAGE_180:
 485                 /*
 486                  * Plese don't switch to 1V8 as arasan,5.1 doesn't
 487                  * actually refer to this setting to indicate the
 488                  * signal voltage and the state machine will be broken
 489                  * actually if we force to enable 1V8. That's something
 490                  * like broken quirk but we could work around here.
 491                  */
 492                 return 0;
 493         case MMC_SIGNAL_VOLTAGE_330:
 494         case MMC_SIGNAL_VOLTAGE_120:
 495                 /* We don't support 3V3 and 1V2 */
 496                 break;
 497         }
 498
 499         return -EINVAL;
 500 }
 501
 502 static struct sdhci_ops sdhci_arasan_ops = {
 503         .set_clock = sdhci_arasan_set_clock,
 504         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 505         .get_timeout_clock = sdhci_arasan_get_timeout_clock,
 506         .set_bus_width = sdhci_set_bus_width,
 507         .reset = sdhci_arasan_reset,
 508         .set_uhs_signaling = sdhci_set_uhs_signaling,
 509 };
 510
 511 static struct sdhci_pltfm_data sdhci_arasan_pdata = {
 512         .ops = &sdhci_arasan_ops,
 513         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 514         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 515                         SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
 516 };
 517
 518 #ifdef CONFIG_PM_SLEEP
 519 /**
 520  * sdhci_arasan_suspend - Suspend method for the driver
 521  * @dev:        Address of the device structure
 522  * Returns 0 on success and error value on error
 523  *
 524  * Put the device in a low power state.
 525  */
 526 static int sdhci_arasan_suspend(struct device *dev)
 527 {
 528         struct platform_device *pdev = to_platform_device(dev);
 529         struct sdhci_host *host = platform_get_drvdata(pdev);
 530         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 531         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 532         int ret;
 533
 534         ret = sdhci_suspend_host(host);
 535         if (ret)
 536                 return ret;
 537
 538         if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
 539                 ret = phy_power_off(sdhci_arasan->phy);
 540                 if (ret) {
 541                         dev_err(dev, "Cannot power off phy.\n");
 542                         sdhci_resume_host(host);
 543                         return ret;
 544                 }
 545                 sdhci_arasan->is_phy_on = false;
 546         }
 547
 548         clk_disable(pltfm_host->clk);
 549         clk_disable(sdhci_arasan->clk_ahb);
 550
 551         return 0;
 552 }
 553
 554 /**
 555  * sdhci_arasan_resume - Resume method for the driver
 556  * @dev:        Address of the device structure
 557  * Returns 0 on success and error value on error
 558  *
 559  * Resume operation after suspend
 560  */
 561 static int sdhci_arasan_resume(struct device *dev)
 562 {
 563         struct platform_device *pdev = to_platform_device(dev);
 564         struct sdhci_host *host = platform_get_drvdata(pdev);
 565         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 566         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 567         int ret;
 568
 569         ret = clk_enable(sdhci_arasan->clk_ahb);
 570         if (ret) {
 571                 dev_err(dev, "Cannot enable AHB clock.\n");
 572                 return ret;
 573         }
 574
 575         ret = clk_enable(pltfm_host->clk);
 576         if (ret) {
 577                 dev_err(dev, "Cannot enable SD clock.\n");
 578                 return ret;
 579         }
 580
 581         if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
 582                 ret = phy_power_on(sdhci_arasan->phy);
 583                 if (ret) {
 584                         dev_err(dev, "Cannot power on phy.\n");
 585                         return ret;
 586                 }
 587                 sdhci_arasan->is_phy_on = true;
 588         }
 589
 590         return sdhci_resume_host(host);
 591 }
 592 #endif /* ! CONFIG_PM_SLEEP */
 593
 594 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
 595                          sdhci_arasan_resume);
 596
 597 static const struct of_device_id sdhci_arasan_of_match[] = {
 598         /* SoC-specific compatible strings w/ soc_ctl_map */
 599         {
 600                 .compatible = "rockchip,rk3399-sdhci-5.1",
 601                 .data = &rk3399_soc_ctl_map,
 602         },
 603
 604         /* Generic compatible below here */
 605         { .compatible = "arasan,sdhci-8.9a" },
 606         { .compatible = "arasan,sdhci-5.1" },
 607         { .compatible = "arasan,sdhci-4.9a" },
 608         { .compatible = "xlnx,zynqmp-8.9a" },
 609
 610         { /* sentinel */ }
 611 };
 612 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
 613
 614 /**
 615  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
 616  *
 617  * Return the current actual rate of the SD card clock.  This can be used
 618  * to communicate with out PHY.
 619  *
 620  * @hw:                 Pointer to the hardware clock structure.
 621  * @parent_rate         The parent rate (should be rate of clk_xin).
 622  * Returns the card clock rate.
 623  */
 624 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
 625                                                       unsigned long parent_rate)
 626
 627 {
 628         struct sdhci_arasan_data *sdhci_arasan =
 629                 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
 630         struct sdhci_host *host = sdhci_arasan->host;
 631
 632         return host->mmc->actual_clock;
 633 }
 634
 635 static const struct clk_ops arasan_sdcardclk_ops = {
 636         .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
 637 };
 638
 639 /**
 640  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
 641  *
 642  * The corecfg_clockmultiplier is supposed to contain clock multiplier
 643  * value of programmable clock generator.
 644  *
 645  * NOTES:
 646  * - Many existing devices don't seem to do this and work fine.  To keep
 647  *   compatibility for old hardware where the device tree doesn't provide a
 648  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
 649  *   for this platform.
 650  * - The value of corecfg_clockmultiplier should sync with that of corresponding
 651  *   value reading from sdhci_capability_register. So this function is called
 652  *   once at probe time and never called again.
 653  *
 654  * @host:               The sdhci_host
 655  */
 656 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
 657                                                 u32 value)
 658 {
 659         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 660         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 661         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
 662                 sdhci_arasan->soc_ctl_map;
 663
 664         /* Having a map is optional */
 665         if (!soc_ctl_map)
 666                 return;
 667
 668         /* If we have a map, we expect to have a syscon */
 669         if (!sdhci_arasan->soc_ctl_base) {
 670                 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
 671                         mmc_hostname(host->mmc));
 672                 return;
 673         }
 674
 675         sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
 676 }
 677
 678 /**
 679  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
 680  *
 681  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
 682  * function can be used to make that happen.
 683  *
 684  * NOTES:
 685  * - Many existing devices don't seem to do this and work fine.  To keep
 686  *   compatibility for old hardware where the device tree doesn't provide a
 687  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
 688  *   for this platform.
 689  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
 690  *   to achieve lower clock rates.  That means that this function is called once
 691  *   at probe time and never called again.
 692  *
 693  * @host:               The sdhci_host
 694  */
 695 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
 696 {
 697         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 698         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 699         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
 700                 sdhci_arasan->soc_ctl_map;
 701         u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
 702
 703         /* Having a map is optional */
 704         if (!soc_ctl_map)
 705                 return;
 706
 707         /* If we have a map, we expect to have a syscon */
 708         if (!sdhci_arasan->soc_ctl_base) {
 709                 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
 710                         mmc_hostname(host->mmc));
 711                 return;
 712         }
 713
 714         sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
 715 }
 716
 717 /**
 718  * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
 719  *
 720  * Some PHY devices need to know what the actual card clock is.  In order for
 721  * them to find out, we'll provide a clock through the common clock framework
 722  * for them to query.
 723  *
 724  * Note: without seriously re-architecting SDHCI's clock code and testing on
 725  * all platforms, there's no way to create a totally beautiful clock here
 726  * with all clock ops implemented.  Instead, we'll just create a clock that can
 727  * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
 728  * framework that we're doing things behind its back.  This should be sufficient
 729  * to create nice clean device tree bindings and later (if needed) we can try
 730  * re-architecting SDHCI if we see some benefit to it.
 731  *
 732  * @sdhci_arasan:       Our private data structure.
 733  * @clk_xin:            Pointer to the functional clock
 734  * @dev:                Pointer to our struct device.
 735  * Returns 0 on success and error value on error
 736  */
 737 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
 738                                        struct clk *clk_xin,
 739                                        struct device *dev)
 740 {
 741         struct device_node *np = dev->of_node;
 742         struct clk_init_data sdcardclk_init;
 743         const char *parent_clk_name;
 744         int ret;
 745
 746         /* Providing a clock to the PHY is optional; no error if missing */
 747         if (!of_find_property(np, "#clock-cells", NULL))
 748                 return 0;
 749
 750         ret = of_property_read_string_index(np, "clock-output-names", 0,
 751                                             &sdcardclk_init.name);
 752         if (ret) {
 753                 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
 754                 return ret;
 755         }
 756
 757         parent_clk_name = __clk_get_name(clk_xin);
 758         sdcardclk_init.parent_names = &parent_clk_name;
 759         sdcardclk_init.num_parents = 1;
 760         sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
 761         sdcardclk_init.ops = &arasan_sdcardclk_ops;
 762
 763         sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
 764         sdhci_arasan->sdcardclk =
 765                 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
 766         sdhci_arasan->sdcardclk_hw.init = NULL;
 767
 768         ret = of_clk_add_provider(np, of_clk_src_simple_get,
 769                                   sdhci_arasan->sdcardclk);
 770         if (ret)
 771                 dev_err(dev, "Failed to add clock provider\n");
 772
 773         return ret;
 774 }
 775
 776 /**
 777  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
 778  *
 779  * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
 780  * returned success.
 781  *
 782  * @dev:                Pointer to our struct device.
 783  */
 784 static void sdhci_arasan_unregister_sdclk(struct device *dev)
 785 {
 786         struct device_node *np = dev->of_node;
 787
 788         if (!of_find_property(np, "#clock-cells", NULL))
 789                 return;
 790
 791         of_clk_del_provider(dev->of_node);
 792 }
 793
 794 static int sdhci_arasan_probe(struct platform_device *pdev)
 795 {
 796         int ret;
 797         const struct of_device_id *match;
 798         struct device_node *node;
 799         struct clk *clk_xin;
 800         struct sdhci_host *host;
 801         struct sdhci_pltfm_host *pltfm_host;
 802         struct sdhci_arasan_data *sdhci_arasan;
 803         struct device_node *np = pdev->dev.of_node;
 804         unsigned int host_quirks2 = 0;
 805
 806         if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a")) {
 807                 char *soc_rev;
 808
 809                 /* read Silicon version using nvmem driver */
 810                 soc_rev = zynqmp_nvmem_get_silicon_version(&pdev->dev,
 811                                                            "soc_revision");
 812                 if (PTR_ERR(soc_rev) == -EPROBE_DEFER)
 813                         /* Do a deferred probe */
 814                         return -EPROBE_DEFER;
 815                 else if (IS_ERR(soc_rev))
 816                         dev_dbg(&pdev->dev, "Error getting silicon version\n");
 817
 818                 /* Set host quirk if the silicon version is v1.0 */
 819                 if (!IS_ERR(soc_rev) && (*soc_rev == ZYNQMP_SILICON_V1))
 820                         host_quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
 821
 822                 /* Clean soc_rev if got a valid pointer from nvmem driver
 823                  * else we may end up in kernel panic
 824                  */
 825                 if (!IS_ERR(soc_rev))
 826                         kfree(soc_rev);
 827         }
 828
 829         host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
 830                                 sizeof(*sdhci_arasan));
 831         if (IS_ERR(host))
 832                 return PTR_ERR(host);
 833
 834         pltfm_host = sdhci_priv(host);
 835         sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 836         sdhci_arasan->host = host;
 837
 838         match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
 839         sdhci_arasan->soc_ctl_map = match->data;
 840
 841         host->quirks2 |= host_quirks2;
 842
 843         node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
 844         if (node) {
 845                 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
 846                 of_node_put(node);
 847
 848                 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
 849                         ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
 850                         if (ret != -EPROBE_DEFER)
 851                                 dev_err(&pdev->dev, "Can't get syscon: %d\n",
 852                                         ret);
 853                         goto err_pltfm_free;
 854                 }
 855         }
 856
 857         sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
 858         if (IS_ERR(sdhci_arasan->clk_ahb)) {
 859                 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
 860                 ret = PTR_ERR(sdhci_arasan->clk_ahb);
 861                 goto err_pltfm_free;
 862         }
 863
 864         clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
 865         if (IS_ERR(clk_xin)) {
 866                 dev_err(&pdev->dev, "clk_xin clock not found.\n");
 867                 ret = PTR_ERR(clk_xin);
 868                 goto err_pltfm_free;
 869         }
 870
 871         ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
 872         if (ret) {
 873                 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
 874                 goto err_pltfm_free;
 875         }
 876
 877         ret = clk_prepare_enable(clk_xin);
 878         if (ret) {
 879                 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
 880                 goto clk_dis_ahb;
 881         }
 882
 883         sdhci_get_of_property(pdev);
 884
 885         if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
 886                 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
 887
 888         pltfm_host->clk = clk_xin;
 889
 890         if (of_device_is_compatible(pdev->dev.of_node,
 891                                     "rockchip,rk3399-sdhci-5.1"))
 892                 sdhci_arasan_update_clockmultiplier(host, 0x0);
 893
 894         sdhci_arasan_update_baseclkfreq(host);
 895
 896         ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
 897         if (ret)
 898                 goto clk_disable_all;
 899
 900         ret = mmc_of_parse(host->mmc);
 901         if (ret) {
 902                 dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
 903                 goto unreg_clk;
 904         }
 905
 906         if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a") ||
 907                 of_device_is_compatible(pdev->dev.of_node,
 908                                         "arasan,sdhci-8.9a")) {
 909                 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 910                 host->quirks2 |= SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN;
 911                 if (of_device_is_compatible(pdev->dev.of_node,
 912                                             "xlnx,zynqmp-8.9a")) {
 913                         ret = of_property_read_u32(pdev->dev.of_node,
 914                                                    "xlnx,mio_bank",
 915                                                    &sdhci_arasan->mio_bank);
 916                         if (ret < 0) {
 917                                 dev_err(&pdev->dev,
 918                                         "\"xlnx,mio_bank \" property is missing.\n");
 919                                 goto clk_disable_all;
 920                         }
 921                         ret = of_property_read_u32(pdev->dev.of_node,
 922                                                    "xlnx,device_id",
 923                                                    &sdhci_arasan->device_id);
 924                         if (ret < 0) {
 925                                 dev_err(&pdev->dev,
 926                                         "\"xlnx,device_id \" property is missing.\n");
 927                                 goto clk_disable_all;
 928                         }
 929                         sdhci_arasan_ops.platform_execute_tuning =
 930                                 arasan_zynqmp_execute_tuning;
 931                 }
 932         }
 933
 934         sdhci_arasan->pinctrl = devm_pinctrl_get(&pdev->dev);
 935         if (!IS_ERR(sdhci_arasan->pinctrl)) {
 936                 sdhci_arasan->pins_default = pinctrl_lookup_state(
 937                                                         sdhci_arasan->pinctrl,
 938                                                         PINCTRL_STATE_DEFAULT);
 939                 if (IS_ERR(sdhci_arasan->pins_default)) {
 940                         dev_err(&pdev->dev, "Missing default pinctrl config\n");
 941                         return IS_ERR(sdhci_arasan->pins_default);
 942                 }
 943
 944                 pinctrl_select_state(sdhci_arasan->pinctrl,
 945                                      sdhci_arasan->pins_default);
 946         }
 947
 948         sdhci_arasan->phy = ERR_PTR(-ENODEV);
 949         if (of_device_is_compatible(pdev->dev.of_node,
 950                                     "arasan,sdhci-5.1")) {
 951                 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
 952                                                  "phy_arasan");
 953                 if (IS_ERR(sdhci_arasan->phy)) {
 954                         ret = PTR_ERR(sdhci_arasan->phy);
 955                         dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
 956                         goto unreg_clk;
 957                 }
 958
 959                 ret = phy_init(sdhci_arasan->phy);
 960                 if (ret < 0) {
 961                         dev_err(&pdev->dev, "phy_init err.\n");
 962                         goto unreg_clk;
 963                 }
 964
 965                 host->mmc_host_ops.hs400_enhanced_strobe =
 966                                         sdhci_arasan_hs400_enhanced_strobe;
 967                 host->mmc_host_ops.start_signal_voltage_switch =
 968                                         sdhci_arasan_voltage_switch;
 969         }
 970
 971         ret = sdhci_add_host(host);
 972         if (ret)
 973                 goto err_add_host;
 974
 975         return 0;
 976
 977 err_add_host:
 978         if (!IS_ERR(sdhci_arasan->phy))
 979                 phy_exit(sdhci_arasan->phy);
 980 unreg_clk:
 981         sdhci_arasan_unregister_sdclk(&pdev->dev);
 982 clk_disable_all:
 983         clk_disable_unprepare(clk_xin);
 984 clk_dis_ahb:
 985         clk_disable_unprepare(sdhci_arasan->clk_ahb);
 986 err_pltfm_free:
 987         sdhci_pltfm_free(pdev);
 988         return ret;
 989 }
 990
 991 static int sdhci_arasan_remove(struct platform_device *pdev)
 992 {
 993         int ret;
 994         struct sdhci_host *host = platform_get_drvdata(pdev);
 995         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 996         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 997         struct clk *clk_ahb = sdhci_arasan->clk_ahb;
 998
 999         if (!IS_ERR(sdhci_arasan->phy)) {
1000                 if (sdhci_arasan->is_phy_on)
1001                         phy_power_off(sdhci_arasan->phy);
1002                 phy_exit(sdhci_arasan->phy);
1003         }
1004
1005         sdhci_arasan_unregister_sdclk(&pdev->dev);
1006
1007         ret = sdhci_pltfm_unregister(pdev);
1008
1009         clk_disable_unprepare(clk_ahb);
1010
1011         return ret;
1012 }
1013
1014 static struct platform_driver sdhci_arasan_driver = {
1015         .driver = {
1016                 .name = "sdhci-arasan",
1017                 .of_match_table = sdhci_arasan_of_match,
1018                 .pm = &sdhci_arasan_dev_pm_ops,
1019         },
1020         .probe = sdhci_arasan_probe,
1021         .remove = sdhci_arasan_remove,
1022 };
1023
1024 module_platform_driver(sdhci_arasan_driver);
1025
1026 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1027 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1028 MODULE_LICENSE("GPL");