drivers/spi/spi-zynqmp-gqspi.c

   1 /*
   2  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
   3  * (master mode only)
   4  *
   5  * Copyright (C) 2009 - 2015 Xilinx, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_address.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/soc/xilinx/zynqmp/firmware.h>
  28
  29 /* Generic QSPI register offsets */
  30 #define GQSPI_CONFIG_OFST               0x00000100
  31 #define GQSPI_ISR_OFST                  0x00000104
  32 #define GQSPI_IDR_OFST                  0x0000010C
  33 #define GQSPI_IER_OFST                  0x00000108
  34 #define GQSPI_IMASK_OFST                0x00000110
  35 #define GQSPI_EN_OFST                   0x00000114
  36 #define GQSPI_TXD_OFST                  0x0000011C
  37 #define GQSPI_RXD_OFST                  0x00000120
  38 #define GQSPI_TX_THRESHOLD_OFST         0x00000128
  39 #define GQSPI_RX_THRESHOLD_OFST         0x0000012C
  40 #define GQSPI_LPBK_DLY_ADJ_OFST         0x00000138
  41 #define GQSPI_GEN_FIFO_OFST             0x00000140
  42 #define GQSPI_SEL_OFST                  0x00000144
  43 #define GQSPI_GF_THRESHOLD_OFST         0x00000150
  44 #define GQSPI_FIFO_CTRL_OFST            0x0000014C
  45 #define GQSPI_QSPIDMA_DST_CTRL_OFST     0x0000080C
  46 #define GQSPI_QSPIDMA_DST_SIZE_OFST     0x00000804
  47 #define GQSPI_QSPIDMA_DST_STS_OFST      0x00000808
  48 #define GQSPI_QSPIDMA_DST_I_STS_OFST    0x00000814
  49 #define GQSPI_QSPIDMA_DST_I_EN_OFST     0x00000818
  50 #define GQSPI_QSPIDMA_DST_I_DIS_OFST    0x0000081C
  51 #define GQSPI_QSPIDMA_DST_I_MASK_OFST   0x00000820
  52 #define GQSPI_QSPIDMA_DST_ADDR_OFST     0x00000800
  53 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
  54 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
  55 #define IOU_TAPDLY_BYPASS_OFST          0xFF180390
  56
  57 /* GQSPI register bit masks */
  58 #define GQSPI_SEL_MASK                          0x00000001
  59 #define GQSPI_EN_MASK                           0x00000001
  60 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK        0x00000020
  61 #define GQSPI_ISR_WR_TO_CLR_MASK                0x00000002
  62 #define GQSPI_IDR_ALL_MASK                      0x00000FBE
  63 #define GQSPI_CFG_MODE_EN_MASK                  0xC0000000
  64 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK      0x20000000
  65 #define GQSPI_CFG_ENDIAN_MASK                   0x04000000
  66 #define GQSPI_CFG_EN_POLL_TO_MASK               0x00100000
  67 #define GQSPI_CFG_WP_HOLD_MASK                  0x00080000
  68 #define GQSPI_CFG_BAUD_RATE_DIV_MASK            0x00000038
  69 #define GQSPI_CFG_CLK_PHA_MASK                  0x00000004
  70 #define GQSPI_CFG_CLK_POL_MASK                  0x00000002
  71 #define GQSPI_CFG_START_GEN_FIFO_MASK           0x10000000
  72 #define GQSPI_GENFIFO_IMM_DATA_MASK             0x000000FF
  73 #define GQSPI_GENFIFO_DATA_XFER                 0x00000100
  74 #define GQSPI_GENFIFO_EXP                       0x00000200
  75 #define GQSPI_GENFIFO_MODE_SPI                  0x00000400
  76 #define GQSPI_GENFIFO_MODE_DUALSPI              0x00000800
  77 #define GQSPI_GENFIFO_MODE_QUADSPI              0x00000C00
  78 #define GQSPI_GENFIFO_MODE_MASK                 0x00000C00
  79 #define GQSPI_GENFIFO_CS_LOWER                  0x00001000
  80 #define GQSPI_GENFIFO_CS_UPPER                  0x00002000
  81 #define GQSPI_GENFIFO_BUS_LOWER                 0x00004000
  82 #define GQSPI_GENFIFO_BUS_UPPER                 0x00008000
  83 #define GQSPI_GENFIFO_BUS_BOTH                  0x0000C000
  84 #define GQSPI_GENFIFO_BUS_MASK                  0x0000C000
  85 #define GQSPI_GENFIFO_TX                        0x00010000
  86 #define GQSPI_GENFIFO_RX                        0x00020000
  87 #define GQSPI_GENFIFO_STRIPE                    0x00040000
  88 #define GQSPI_GENFIFO_POLL                      0x00080000
  89 #define GQSPI_GENFIFO_EXP_START                 0x00000100
  90 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK        0x00000004
  91 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK        0x00000002
  92 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK       0x00000001
  93 #define GQSPI_ISR_RXEMPTY_MASK                  0x00000800
  94 #define GQSPI_ISR_GENFIFOFULL_MASK              0x00000400
  95 #define GQSPI_ISR_GENFIFONOT_FULL_MASK          0x00000200
  96 #define GQSPI_ISR_TXEMPTY_MASK                  0x00000100
  97 #define GQSPI_ISR_GENFIFOEMPTY_MASK             0x00000080
  98 #define GQSPI_ISR_RXFULL_MASK                   0x00000020
  99 #define GQSPI_ISR_RXNEMPTY_MASK                 0x00000010
 100 #define GQSPI_ISR_TXFULL_MASK                   0x00000008
 101 #define GQSPI_ISR_TXNOT_FULL_MASK               0x00000004
 102 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK         0x00000002
 103 #define GQSPI_IER_TXNOT_FULL_MASK               0x00000004
 104 #define GQSPI_IER_RXEMPTY_MASK                  0x00000800
 105 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK         0x00000002
 106 #define GQSPI_IER_RXNEMPTY_MASK                 0x00000010
 107 #define GQSPI_IER_GENFIFOEMPTY_MASK             0x00000080
 108 #define GQSPI_IER_TXEMPTY_MASK                  0x00000100
 109 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK         0x000000FE
 110 #define GQSPI_QSPIDMA_DST_STS_WTC               0x0000E000
 111 #define GQSPI_CFG_MODE_EN_DMA_MASK              0x80000000
 112 #define GQSPI_ISR_IDR_MASK                      0x00000994
 113 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK        0x00000002
 114 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK       0x00000002
 115 #define GQSPI_IRQ_MASK                          0x00000980
 116
 117 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT           3
 118 #define GQSPI_GENFIFO_CS_SETUP                  0x4
 119 #define GQSPI_GENFIFO_CS_HOLD                   0x3
 120 #define GQSPI_TXD_DEPTH                         64
 121 #define GQSPI_RX_FIFO_THRESHOLD                 32
 122 #define GQSPI_RX_FIFO_FILL      (GQSPI_RX_FIFO_THRESHOLD * 4)
 123 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL       32
 124 #define GQSPI_TX_FIFO_FILL      (GQSPI_TXD_DEPTH -\
 125                                 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
 126 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL      0X10
 127 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL        0x803FFA00
 128 #define GQSPI_SELECT_FLASH_CS_LOWER             0x1
 129 #define GQSPI_SELECT_FLASH_CS_UPPER             0x2
 130 #define GQSPI_SELECT_FLASH_CS_BOTH              0x3
 131 #define GQSPI_SELECT_FLASH_BUS_LOWER            0x1
 132 #define GQSPI_SELECT_FLASH_BUS_UPPER            0x2
 133 #define GQSPI_SELECT_FLASH_BUS_BOTH             0x3
 134 #define GQSPI_BAUD_DIV_MAX      7       /* Baud rate divisor maximum */
 135 #define GQSPI_BAUD_DIV_SHIFT    2       /* Baud rate divisor shift */
 136 #define GQSPI_SELECT_MODE_SPI           0x1
 137 #define GQSPI_SELECT_MODE_DUALSPI       0x2
 138 #define GQSPI_SELECT_MODE_QUADSPI       0x4
 139 #define GQSPI_DMA_UNALIGN               0x3
 140 #define GQSPI_DEFAULT_NUM_CS    1       /* Default number of chip selects */
 141 #define GQSPI_RX_BUS_WIDTH_QUAD         0x4
 142 #define GQSPI_RX_BUS_WIDTH_DUAL         0x2
 143 #define GQSPI_RX_BUS_WIDTH_SINGLE       0x1
 144 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
 145 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
 146 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
 147 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
 148 #define GQSPI_USE_DATA_DLY              0x1
 149 #define GQSPI_USE_DATA_DLY_SHIFT        31
 150 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
 151 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
 152 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
 153 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
 154
 155 #define GQSPI_FREQ_40MHZ        40000000
 156 #define GQSPI_FREQ_100MHZ       100000000
 157 #define GQSPI_FREQ_150MHZ       150000000
 158 #define IOU_TAPDLY_BYPASS_MASK  0x7
 159
 160 #define SPI_AUTOSUSPEND_TIMEOUT         3000
 161 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
 162
 163 /**
 164  * struct zynqmp_qspi - Defines qspi driver instance
 165  * @regs:               Virtual address of the QSPI controller registers
 166  * @refclk:             Pointer to the peripheral clock
 167  * @pclk:               Pointer to the APB clock
 168  * @irq:                IRQ number
 169  * @dev:                Pointer to struct device
 170  * @txbuf:              Pointer to the TX buffer
 171  * @rxbuf:              Pointer to the RX buffer
 172  * @bytes_to_transfer:  Number of bytes left to transfer
 173  * @bytes_to_receive:   Number of bytes left to receive
 174  * @genfifocs:          Used for chip select
 175  * @genfifobus:         Used to select the upper or lower bus
 176  * @dma_rx_bytes:       Remaining bytes to receive by DMA mode
 177  * @dma_addr:           DMA address after mapping the kernel buffer
 178  * @rx_bus_width:       Used to represent number of data wires
 179  * @genfifoentry:       Used for storing the genfifoentry instruction.
 180  * @isinstr:            To determine whether the transfer is instruction
 181  * @mode:               Defines the mode in which QSPI is operating
 182  * @speed_hz:           Current SPI bus clock speed in hz
 183  * @io_mode:            Defines the operating mode, either IO or dma
 184  */
 185 struct zynqmp_qspi {
 186         void __iomem *regs;
 187         struct clk *refclk;
 188         struct clk *pclk;
 189         int irq;
 190         struct device *dev;
 191         const void *txbuf;
 192         void *rxbuf;
 193         int bytes_to_transfer;
 194         int bytes_to_receive;
 195         u32 genfifocs;
 196         u32 genfifobus;
 197         u32 dma_rx_bytes;
 198         dma_addr_t dma_addr;
 199         u32 rx_bus_width;
 200         u32 genfifoentry;
 201         bool isinstr;
 202         enum mode_type mode;
 203         u32 speed_hz;
 204         bool io_mode;
 205 };
 206
 207 /**
 208  * zynqmp_gqspi_read -  For GQSPI controller read operation
 209  * @xqspi:      Pointer to the zynqmp_qspi structure
 210  * @offset:     Offset from where to read
 211  *
 212  * Return: Value read from the qspi register
 213  */
 214 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
 215 {
 216         return readl_relaxed(xqspi->regs + offset);
 217 }
 218
 219 /**
 220  * zynqmp_gqspi_write - For GQSPI controller write operation
 221  * @xqspi:      Pointer to the zynqmp_qspi structure
 222  * @offset:     Offset where to write
 223  * @val:        Value to be written
 224  */
 225 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
 226                                       u32 val)
 227 {
 228         writel_relaxed(val, (xqspi->regs + offset));
 229 }
 230
 231 /**
 232  * zynqmp_gqspi_selectslave -   For selection of slave device
 233  * @instanceptr:        Pointer to the zynqmp_qspi structure
 234  * @slavecs:    For chip select
 235  * @slavebus:   To check which bus is selected- upper or lower
 236  */
 237 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
 238                                      u8 slavecs, u8 slavebus)
 239 {
 240         /*
 241          * Bus and CS lines selected here will be updated in the instance and
 242          * used for subsequent GENFIFO entries during transfer.
 243          */
 244
 245         /* Choose slave select line */
 246         switch (slavecs) {
 247         case GQSPI_SELECT_FLASH_CS_BOTH:
 248                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
 249                         GQSPI_GENFIFO_CS_UPPER;
 250                 break;
 251         case GQSPI_SELECT_FLASH_CS_UPPER:
 252                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
 253                 break;
 254         case GQSPI_SELECT_FLASH_CS_LOWER:
 255                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 256                 break;
 257         default:
 258                 dev_warn(instanceptr->dev, "Invalid slave select\n");
 259         }
 260
 261         /* Choose the bus */
 262         switch (slavebus) {
 263         case GQSPI_SELECT_FLASH_BUS_BOTH:
 264                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
 265                         GQSPI_GENFIFO_BUS_UPPER;
 266                 break;
 267         case GQSPI_SELECT_FLASH_BUS_UPPER:
 268                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
 269                 break;
 270         case GQSPI_SELECT_FLASH_BUS_LOWER:
 271                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 272                 break;
 273         default:
 274                 dev_warn(instanceptr->dev, "Invalid slave bus\n");
 275         }
 276 }
 277
 278 /**
 279  * zynqmp_qspi_set_tapdelay -   To configure qspi tap delays
 280  * @xqspi:              Pointer to the zynqmp_qspi structure
 281  * @baudrateval:        Buadrate to configure
 282  */
 283 static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
 284 {
 285         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 286         u32 reqhz = 0;
 287
 288         clk_rate = clk_get_rate(xqspi->refclk);
 289         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 290
 291         if (reqhz < GQSPI_FREQ_40MHZ) {
 292                 zynqmp_pm_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 293                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 294                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 295         } else if (reqhz < GQSPI_FREQ_100MHZ) {
 296                 zynqmp_pm_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 297                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 298                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 299                 lpbkdlyadj = zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST);
 300                 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 301                 datadlyadj = zynqmp_gqspi_read(xqspi, GQSPI_DATA_DLY_ADJ_OFST);
 302                 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 303                                 | (GQSPI_DATA_DLY_ADJ_VALUE <<
 304                                         GQSPI_DATA_DLY_ADJ_SHIFT));
 305         } else if (reqhz < GQSPI_FREQ_150MHZ) {
 306                 lpbkdlyadj = zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST);
 307                 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK) |
 308                                 GQSPI_LPBK_DLY_ADJ_DLY_0);
 309         }
 310
 311         zynqmp_pm_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
 312                         tapdlybypass);
 313         zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);
 314         zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);
 315 }
 316
 317 /**
 318  * zynqmp_qspi_init_hw -        Initialize the hardware
 319  * @xqspi:      Pointer to the zynqmp_qspi structure
 320  *
 321  * The default settings of the QSPI controller's configurable parameters on
 322  * reset are
 323  *      - Master mode
 324  *      - TX threshold set to 1
 325  *      - RX threshold set to 1
 326  *      - Flash memory interface mode enabled
 327  * This function performs the following actions
 328  *      - Disable and clear all the interrupts
 329  *      - Enable manual slave select
 330  *      - Enable manual start
 331  *      - Deselect all the chip select lines
 332  *      - Set the little endian mode of TX FIFO and
 333  *      - Enable the QSPI controller
 334  */
 335 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 336 {
 337         u32 config_reg;
 338
 339         /* Select the GQSPI mode */
 340         zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
 341         /* Clear and disable interrupts */
 342         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
 343                            zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
 344                            GQSPI_ISR_WR_TO_CLR_MASK);
 345         /* Clear the DMA STS */
 346         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 347                            zynqmp_gqspi_read(xqspi,
 348                                              GQSPI_QSPIDMA_DST_I_STS_OFST));
 349         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
 350                            zynqmp_gqspi_read(xqspi,
 351                                              GQSPI_QSPIDMA_DST_STS_OFST) |
 352                                              GQSPI_QSPIDMA_DST_STS_WTC);
 353         zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
 354         zynqmp_gqspi_write(xqspi,
 355                            GQSPI_QSPIDMA_DST_I_DIS_OFST,
 356                            GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
 357         /* Disable the GQSPI */
 358         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 359         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 360         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 361         /* Manual start */
 362         config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
 363         /* Little endian by default */
 364         config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
 365         /* Disable poll time out */
 366         config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
 367         /* Set hold bit */
 368         config_reg |= GQSPI_CFG_WP_HOLD_MASK;
 369         /* Clear pre-scalar by default */
 370         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 371         /* CPHA 0 */
 372         config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
 373         /* CPOL 0 */
 374         config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
 375         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 376
 377         /* Clear the TX and RX FIFO */
 378         zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
 379                            GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
 380                            GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
 381                            GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
 382         /* Set by default to allow for high frequencies */
 383         zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
 384                            zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
 385                            GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 386         /* Reset thresholds */
 387         zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
 388                            GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
 389         zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
 390                            GQSPI_RX_FIFO_THRESHOLD);
 391         zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
 392                            GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
 393         zynqmp_gqspi_selectslave(xqspi,
 394                                  GQSPI_SELECT_FLASH_CS_LOWER,
 395                                  GQSPI_SELECT_FLASH_BUS_LOWER);
 396         if (!xqspi->io_mode) {
 397                 /* Initialize DMA */
 398                 zynqmp_gqspi_write(xqspi,
 399                         GQSPI_QSPIDMA_DST_CTRL_OFST,
 400                         GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
 401         }
 402         /* Enable the GQSPI */
 403         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 404 }
 405
 406 /**
 407  * zynqmp_qspi_copy_read_data - Copy data to RX buffer
 408  * @xqspi:      Pointer to the zynqmp_qspi structure
 409  * @data:       The variable where data is stored
 410  * @size:       Number of bytes to be copied from data to RX buffer
 411  */
 412 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
 413                                        ulong data, u8 size)
 414 {
 415         memcpy(xqspi->rxbuf, &data, size);
 416         xqspi->rxbuf += size;
 417         xqspi->bytes_to_receive -= size;
 418 }
 419
 420 /**
 421  * zynqmp_prepare_transfer_hardware -   Prepares hardware for transfer.
 422  * @master:     Pointer to the spi_master structure which provides
 423  *              information about the controller.
 424  *
 425  * This function enables SPI master controller.
 426  *
 427  * Return:      0 on success; error value otherwise
 428  */
 429 static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
 430 {
 431         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 432
 433         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 434         return 0;
 435 }
 436
 437 /**
 438  * zynqmp_unprepare_transfer_hardware - Relaxes hardware after transfer
 439  * @master:     Pointer to the spi_master structure which provides
 440  *              information about the controller.
 441  *
 442  * This function disables the SPI master controller.
 443  *
 444  * Return:      Always 0
 445  */
 446 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
 447 {
 448         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 449
 450         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 451         return 0;
 452 }
 453
 454 /**
 455  * zynqmp_qspi_chipselect -     Select or deselect the chip select line
 456  * @qspi:       Pointer to the spi_device structure
 457  * @is_high:    Select(0) or deselect (1) the chip select line
 458  */
 459 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
 460 {
 461         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 462         ulong timeout;
 463         u32 genfifoentry = 0x0, statusreg;
 464
 465         genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 466
 467         if (qspi->master->flags & SPI_MASTER_BOTH_CS) {
 468                 zynqmp_gqspi_selectslave(xqspi,
 469                         GQSPI_SELECT_FLASH_CS_BOTH,
 470                         GQSPI_SELECT_FLASH_BUS_BOTH);
 471         } else if (qspi->master->flags & SPI_MASTER_U_PAGE) {
 472                 zynqmp_gqspi_selectslave(xqspi,
 473                         GQSPI_SELECT_FLASH_CS_UPPER,
 474                         GQSPI_SELECT_FLASH_BUS_LOWER);
 475         } else {
 476                 zynqmp_gqspi_selectslave(xqspi,
 477                         GQSPI_SELECT_FLASH_CS_LOWER,
 478                         GQSPI_SELECT_FLASH_BUS_LOWER);
 479         }
 480
 481         genfifoentry |= xqspi->genfifobus;
 482
 483         if (!is_high) {
 484                 genfifoentry |= xqspi->genfifocs;
 485                 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
 486                 xqspi->isinstr = true;
 487         } else {
 488                 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
 489         }
 490
 491         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 492
 493         /* Dummy generic FIFO entry */
 494         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 495
 496         /* Manually start the generic FIFO command */
 497         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 498                         zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 499                         GQSPI_CFG_START_GEN_FIFO_MASK);
 500
 501         timeout = jiffies + msecs_to_jiffies(1000);
 502
 503         /* Wait until the generic FIFO command is empty */
 504         do {
 505                 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 506
 507                 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
 508                         (statusreg & GQSPI_ISR_TXEMPTY_MASK))
 509                         break;
 510                 cpu_relax();
 511         } while (!time_after_eq(jiffies, timeout));
 512
 513         if (time_after_eq(jiffies, timeout))
 514                 dev_err(xqspi->dev, "Chip select timed out\n");
 515 }
 516
 517 /**
 518  * zynqmp_qspi_setup_transfer - Configure QSPI controller for specified
 519  *                              transfer
 520  * @qspi:       Pointer to the spi_device structure
 521  * @transfer:   Pointer to the spi_transfer structure which provides
 522  *              information about next transfer setup parameters
 523  *
 524  * Sets the operational mode of QSPI controller for the next QSPI transfer and
 525  * sets the requested clock frequency.
 526  *
 527  * Return:      Always 0
 528  *
 529  * Note:
 530  *      If the requested frequency is not an exact match with what can be
 531  *      obtained using the pre-scalar value, the driver sets the clock
 532  *      frequency which is lower than the requested frequency (maximum lower)
 533  *      for the transfer.
 534  *
 535  *      If the requested frequency is higher or lower than that is supported
 536  *      by the QSPI controller the driver will set the highest or lowest
 537  *      frequency supported by controller.
 538  */
 539 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
 540                                       struct spi_transfer *transfer)
 541 {
 542         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 543         ulong clk_rate;
 544         u32 config_reg, req_hz, baud_rate_val = 0;
 545
 546         if (transfer)
 547                 req_hz = transfer->speed_hz;
 548         else
 549                 req_hz = qspi->max_speed_hz;
 550
 551         if (xqspi->speed_hz != req_hz) {
 552                 /* Set the clock frequency */
 553                 /* If req_hz == 0, default to lowest speed */
 554                 clk_rate = clk_get_rate(xqspi->refclk);
 555
 556                 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
 557                        (clk_rate /
 558                         (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
 559                         baud_rate_val++;
 560
 561                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 562
 563                 /* Set the QSPI clock phase and clock polarity */
 564                 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) &
 565                         (~GQSPI_CFG_CLK_POL_MASK);
 566
 567                 if (qspi->mode & SPI_CPHA)
 568                         config_reg |= GQSPI_CFG_CLK_PHA_MASK;
 569                 if (qspi->mode & SPI_CPOL)
 570                         config_reg |= GQSPI_CFG_CLK_POL_MASK;
 571                 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 572                 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
 573                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 574                 xqspi->speed_hz = clk_rate / (GQSPI_BAUD_DIV_SHIFT <<
 575                                 baud_rate_val);
 576                 zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
 577         }
 578
 579         return 0;
 580 }
 581
 582 /**
 583  * zynqmp_qspi_setup -  Configure the QSPI controller
 584  * @qspi:       Pointer to the spi_device structure
 585  *
 586  * Sets the operational mode of QSPI controller for the next QSPI transfer,
 587  * baud rate and divisor value to setup the requested qspi clock.
 588  *
 589  * Return:      0 on success; error value otherwise.
 590  */
 591 static int zynqmp_qspi_setup(struct spi_device *qspi)
 592 {
 593         if (qspi->master->busy)
 594                 return -EBUSY;
 595         return 0;
 596 }
 597
 598 /**
 599  * zynqmp_qspi_filltxfifo -     Fills the TX FIFO as long as there is room in
 600  *                              the FIFO or the bytes required to be
 601  *                              transmitted.
 602  * @xqspi:      Pointer to the zynqmp_qspi structure
 603  * @size:       Number of bytes to be copied from TX buffer to TX FIFO
 604  */
 605 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
 606 {
 607         u32 count = 0, intermediate;
 608
 609         while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
 610                 memcpy(&intermediate, xqspi->txbuf, 4);
 611                 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
 612
 613                 if (xqspi->bytes_to_transfer >= 4) {
 614                         xqspi->txbuf += 4;
 615                         xqspi->bytes_to_transfer -= 4;
 616                 } else {
 617                         xqspi->txbuf += xqspi->bytes_to_transfer;
 618                         xqspi->bytes_to_transfer = 0;
 619                 }
 620                 count++;
 621         }
 622 }
 623
 624 /**
 625  * zynqmp_qspi_readrxfifo -     Fills the RX FIFO as long as there is room in
 626  *                              the FIFO.
 627  * @xqspi:      Pointer to the zynqmp_qspi structure
 628  * @size:       Number of bytes to be copied from RX buffer to RX FIFO
 629  */
 630 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
 631 {
 632         ulong data;
 633         int count = 0;
 634
 635         while ((count < size) && (xqspi->bytes_to_receive > 0)) {
 636                 if (xqspi->bytes_to_receive >= 4) {
 637                         (*(u32 *) xqspi->rxbuf) =
 638                                 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 639                         xqspi->rxbuf += 4;
 640                         xqspi->bytes_to_receive -= 4;
 641                         count += 4;
 642                 } else {
 643                         data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 644                         count += xqspi->bytes_to_receive;
 645                         zynqmp_qspi_copy_read_data(xqspi, data,
 646                                                    xqspi->bytes_to_receive);
 647                         xqspi->bytes_to_receive = 0;
 648                 }
 649         }
 650 }
 651
 652 /**
 653  * zynqmp_qspi_preparedummy -   Prepares the dummy entry
 654  *
 655  * @xqspi:      Pointer to the zynqmp_qspi structure
 656  * @transfer:   It is a pointer to the structure containing transfer data.
 657  * @genfifoentry:       genfifoentry is pointer to the variable in which
 658  *                      GENFIFO mask is returned to calling function
 659  */
 660 static void zynqmp_qspi_preparedummy(struct zynqmp_qspi *xqspi,
 661                                         struct spi_transfer *transfer,
 662                                         u32 *genfifoentry)
 663 {
 664         /* For dummy Tx and Rx are NULL */
 665         *genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
 666
 667         /* SPI mode */
 668         *genfifoentry &= ~GQSPI_GENFIFO_MODE_QUADSPI;
 669         if (xqspi->rx_bus_width == GQSPI_RX_BUS_WIDTH_QUAD)
 670                 *genfifoentry |= GQSPI_GENFIFO_MODE_QUADSPI;
 671         else if (xqspi->rx_bus_width == GQSPI_RX_BUS_WIDTH_DUAL)
 672                 *genfifoentry |= GQSPI_GENFIFO_MODE_DUALSPI;
 673         else
 674                 *genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 675
 676         /* Immediate data */
 677         *genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 678         *genfifoentry |= transfer->dummy;
 679 }
 680
 681 /**
 682  * zynqmp_process_dma_irq -     Handler for DMA done interrupt of QSPI
 683  *                              controller
 684  * @xqspi:      zynqmp_qspi instance pointer
 685  *
 686  * This function handles DMA interrupt only.
 687  */
 688 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
 689 {
 690         u32 config_reg, genfifoentry;
 691
 692         dma_unmap_single(xqspi->dev, xqspi->dma_addr,
 693                                 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
 694         xqspi->rxbuf += xqspi->dma_rx_bytes;
 695         xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
 696         xqspi->dma_rx_bytes = 0;
 697
 698         /* Disabling the DMA interrupts */
 699         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
 700                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 701
 702         if (xqspi->bytes_to_receive > 0) {
 703                 /* Switch to IO mode,for remaining bytes to receive */
 704                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 705                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 706                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 707
 708                 /* Initiate the transfer of remaining bytes */
 709                 genfifoentry = xqspi->genfifoentry;
 710                 genfifoentry |= xqspi->bytes_to_receive;
 711                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 712
 713                 /* Dummy generic FIFO entry */
 714                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 715
 716                 /* Manual start */
 717                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 718                         (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 719                         GQSPI_CFG_START_GEN_FIFO_MASK));
 720
 721                 /* Enable the RX interrupts for IO mode */
 722                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 723                                 GQSPI_IER_GENFIFOEMPTY_MASK |
 724                                 GQSPI_IER_RXNEMPTY_MASK |
 725                                 GQSPI_IER_RXEMPTY_MASK);
 726         }
 727 }
 728
 729 /**
 730  * zynqmp_qspi_irq -    Interrupt service routine of the QSPI controller
 731  * @irq:        IRQ number
 732  * @dev_id:     Pointer to the xqspi structure
 733  *
 734  * This function handles TX empty only.
 735  * On TX empty interrupt this function reads the received data from RX FIFO
 736  * and fills the TX FIFO if there is any data remaining to be transferred.
 737  *
 738  * Return:      IRQ_HANDLED when interrupt is handled
 739  *              IRQ_NONE otherwise.
 740  */
 741 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
 742 {
 743         struct spi_master *master = dev_id;
 744         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 745         int ret = IRQ_NONE;
 746         u32 status, mask, dma_status = 0;
 747
 748         status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 749         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
 750         mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
 751
 752         /* Read and clear DMA status */
 753         if (xqspi->mode == GQSPI_MODE_DMA) {
 754                 dma_status =
 755                         zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
 756                 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 757                                                                 dma_status);
 758         }
 759
 760         if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
 761                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
 762                 ret = IRQ_HANDLED;
 763         }
 764
 765         if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
 766                 zynqmp_process_dma_irq(xqspi);
 767                 ret = IRQ_HANDLED;
 768         } else if ((mask & GQSPI_IER_RXNEMPTY_MASK)) {
 769                 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
 770                 ret = IRQ_HANDLED;
 771         }
 772         if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
 773                 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
 774                 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
 775                 ret = IRQ_HANDLED;
 776         }
 777
 778         if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
 779                         && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
 780                 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
 781                 xqspi->isinstr = false;
 782                 spi_finalize_current_transfer(master);
 783                 ret = IRQ_HANDLED;
 784         }
 785         return ret;
 786 }
 787
 788 /**
 789  * zynqmp_qspi_selectspimode -  Selects SPI mode - x1 or x2 or x4.
 790  * @xqspi:      xqspi is a pointer to the GQSPI instance
 791  * @spimode:    spimode - SPI or DUAL or QUAD.
 792  * Return:      Mask to set desired SPI mode in GENFIFO entry.
 793  */
 794 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
 795                                                 u8 spimode)
 796 {
 797         u32 mask = 0;
 798
 799         switch (spimode) {
 800         case GQSPI_SELECT_MODE_DUALSPI:
 801                 mask = GQSPI_GENFIFO_MODE_DUALSPI;
 802                 break;
 803         case GQSPI_SELECT_MODE_QUADSPI:
 804                 mask = GQSPI_GENFIFO_MODE_QUADSPI;
 805                 break;
 806         case GQSPI_SELECT_MODE_SPI:
 807                 mask = GQSPI_GENFIFO_MODE_SPI;
 808                 break;
 809         default:
 810                 dev_warn(xqspi->dev, "Invalid SPI mode\n");
 811         }
 812
 813         return mask;
 814 }
 815
 816 /**
 817  * zynq_qspi_setuprxdma -       This function sets up the RX DMA operation
 818  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 819  */
 820 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
 821 {
 822         u32 rx_bytes, rx_rem, config_reg;
 823         dma_addr_t addr;
 824         u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
 825
 826         if (((xqspi->bytes_to_receive < 8) || (xqspi->io_mode)) ||
 827                 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
 828                 /* Setting to IO mode */
 829                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 830                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 831                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 832                 xqspi->mode = GQSPI_MODE_IO;
 833                 xqspi->dma_rx_bytes = 0;
 834                 return;
 835         }
 836
 837         rx_rem = xqspi->bytes_to_receive % 4;
 838         rx_bytes = (xqspi->bytes_to_receive - rx_rem);
 839
 840         addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
 841                                                 rx_bytes, DMA_FROM_DEVICE);
 842         if (dma_mapping_error(xqspi->dev, addr))
 843                 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
 844
 845         xqspi->dma_rx_bytes = rx_bytes;
 846         xqspi->dma_addr = addr;
 847         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
 848                                 (u32)(addr & 0xffffffff));
 849         addr = ((addr >> 16) >> 16);
 850         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
 851                                 ((u32)addr) & 0xfff);
 852
 853         /* Enabling the DMA mode */
 854         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 855         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 856         config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
 857         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 858
 859         /* Switch to DMA mode */
 860         xqspi->mode = GQSPI_MODE_DMA;
 861
 862         /* Write the number of bytes to transfer */
 863         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
 864 }
 865
 866 /**
 867  * zynqmp_qspi_txrxsetup -      This function checks the TX/RX buffers in
 868  *                              the transfer and sets up the GENFIFO entries,
 869  *                              TX FIFO as required.
 870  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 871  * @transfer:   It is a pointer to the structure containing transfer data.
 872  * @genfifoentry:       genfifoentry is pointer to the variable in which
 873  *                      GENFIFO mask is returned to calling function
 874  */
 875 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
 876                                   struct spi_transfer *transfer,
 877                                   u32 *genfifoentry)
 878 {
 879         u32 config_reg;
 880
 881         /* Transmit */
 882         if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
 883                 /* Setup data to be TXed */
 884                 *genfifoentry &= ~GQSPI_GENFIFO_RX;
 885                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 886                 *genfifoentry |= GQSPI_GENFIFO_TX;
 887                 *genfifoentry |=
 888                         zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
 889                 xqspi->bytes_to_transfer = transfer->len - (transfer->dummy/8);
 890                 if (xqspi->mode == GQSPI_MODE_DMA) {
 891                         config_reg = zynqmp_gqspi_read(xqspi,
 892                                                         GQSPI_CONFIG_OFST);
 893                         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 894                         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 895                                                                 config_reg);
 896                         xqspi->mode = GQSPI_MODE_IO;
 897                 }
 898                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
 899                 /* Discard RX data */
 900                 xqspi->bytes_to_receive = 0;
 901         } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
 902                 /* Receive */
 903
 904                 /* TX auto fill */
 905                 *genfifoentry &= ~GQSPI_GENFIFO_TX;
 906                 /* Setup RX */
 907                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 908                 *genfifoentry |= GQSPI_GENFIFO_RX;
 909                 *genfifoentry |=
 910                         zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
 911                 xqspi->bytes_to_transfer = 0;
 912                 xqspi->bytes_to_receive = transfer->len;
 913                 zynq_qspi_setuprxdma(xqspi);
 914         }
 915 }
 916
 917 /**
 918  * zynqmp_qspi_start_transfer - Initiates the QSPI transfer
 919  * @master:     Pointer to the spi_master structure which provides
 920  *              information about the controller.
 921  * @qspi:       Pointer to the spi_device structure
 922  * @transfer:   Pointer to the spi_transfer structure which provide information
 923  *              about next transfer parameters
 924  *
 925  * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 926  * transfer to be completed.
 927  *
 928  * Return:      Number of bytes transferred in the last transfer
 929  */
 930 static int zynqmp_qspi_start_transfer(struct spi_master *master,
 931                                       struct spi_device *qspi,
 932                                       struct spi_transfer *transfer)
 933 {
 934         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 935         u32 genfifoentry = 0x0, transfer_len;
 936
 937         xqspi->txbuf = transfer->tx_buf;
 938         xqspi->rxbuf = transfer->rx_buf;
 939
 940         zynqmp_qspi_setup_transfer(qspi, transfer);
 941
 942         genfifoentry |= xqspi->genfifocs;
 943         genfifoentry |= xqspi->genfifobus;
 944
 945         if ((!xqspi->isinstr) &&
 946                 (master->flags & SPI_MASTER_DATA_STRIPE))
 947                 genfifoentry |= GQSPI_GENFIFO_STRIPE;
 948
 949         zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
 950
 951         if (xqspi->mode == GQSPI_MODE_DMA)
 952                 transfer_len = xqspi->dma_rx_bytes;
 953         else
 954                 transfer_len = transfer->len - (transfer->dummy/8);
 955
 956         xqspi->genfifoentry = genfifoentry;
 957         if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
 958                 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 959                 genfifoentry |= transfer_len;
 960                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 961                 if (transfer->dummy) {
 962                         zynqmp_qspi_preparedummy(xqspi, transfer,
 963                                         &genfifoentry);
 964                         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
 965                                         genfifoentry);
 966                 }
 967         } else {
 968                 int tempcount = transfer_len;
 969                 u32 exponent = 8;       /* 2^8 = 256 */
 970                 u8 imm_data = tempcount & 0xFF;
 971
 972                 tempcount &= ~(tempcount & 0xFF);
 973                 /* Immediate entry */
 974                 if (tempcount != 0) {
 975                         /* Exponent entries */
 976                         genfifoentry |= GQSPI_GENFIFO_EXP;
 977                         while (tempcount != 0) {
 978                                 if (tempcount & GQSPI_GENFIFO_EXP_START) {
 979                                         genfifoentry &=
 980                                             ~GQSPI_GENFIFO_IMM_DATA_MASK;
 981                                         genfifoentry |= exponent;
 982                                         zynqmp_gqspi_write(xqspi,
 983                                                            GQSPI_GEN_FIFO_OFST,
 984                                                            genfifoentry);
 985                                 }
 986                                 tempcount = tempcount >> 1;
 987                                 exponent++;
 988                         }
 989                 }
 990                 if (imm_data != 0) {
 991                         genfifoentry &= ~GQSPI_GENFIFO_EXP;
 992                         genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 993                         if (imm_data % 4 != 0) {
 994                                 if (((imm_data + 4 - (imm_data % 4)) & 0xFF) == 0x00)
 995                                         imm_data = 0xFF;
 996                                 else
 997                                         imm_data = imm_data + 4 - (imm_data % 4);
 998                         }
 999                         genfifoentry |= (u8) (imm_data & 0xFF);
1000                         zynqmp_gqspi_write(xqspi,
1001                                            GQSPI_GEN_FIFO_OFST, genfifoentry);
1002                 }
1003         }
1004
1005         if ((xqspi->mode == GQSPI_MODE_IO) &&
1006                         (xqspi->rxbuf != NULL)) {
1007                 /* Dummy generic FIFO entry */
1008                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
1009         }
1010
1011         /* Since we are using manual mode */
1012         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1013                            zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1014                            GQSPI_CFG_START_GEN_FIFO_MASK);
1015
1016         if (xqspi->txbuf != NULL)
1017                 /* Enable interrupts for TX */
1018                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1019                                    GQSPI_IER_TXEMPTY_MASK |
1020                                         GQSPI_IER_GENFIFOEMPTY_MASK |
1021                                         GQSPI_IER_TXNOT_FULL_MASK);
1022
1023         if (xqspi->rxbuf != NULL) {
1024                 /* Enable interrupts for RX */
1025                 if (xqspi->mode == GQSPI_MODE_DMA) {
1026                         /* Enable DMA interrupts */
1027                         zynqmp_gqspi_write(xqspi,
1028                                         GQSPI_QSPIDMA_DST_I_EN_OFST,
1029                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1030                 } else {
1031                         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1032                                         GQSPI_IER_GENFIFOEMPTY_MASK |
1033                                         GQSPI_IER_RXNEMPTY_MASK |
1034                                         GQSPI_IER_RXEMPTY_MASK);
1035                 }
1036         }
1037
1038         return transfer->len;
1039 }
1040
1041 /**
1042  * zynqmp_qspi_suspend -        Suspend method for the QSPI driver
1043  * @dev:        Address of the platform_device structure
1044  *
1045  * This function stops the QSPI driver queue and disables the QSPI controller
1046  *
1047  * Return:      Always 0
1048  */
1049 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
1050 {
1051         struct platform_device *pdev = to_platform_device(dev);
1052         struct spi_master *master = platform_get_drvdata(pdev);
1053
1054         spi_master_suspend(master);
1055
1056         zynqmp_unprepare_transfer_hardware(master);
1057
1058         return 0;
1059 }
1060
1061 /**
1062  * zynqmp_qspi_resume - Resume method for the QSPI driver
1063  * @dev:        Address of the platform_device structure
1064  *
1065  * The function starts the QSPI driver queue and initializes the QSPI
1066  * controller
1067  *
1068  * Return:      0 on success; error value otherwise
1069  */
1070 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
1071 {
1072         struct platform_device *pdev = to_platform_device(dev);
1073         struct spi_master *master = platform_get_drvdata(pdev);
1074         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1075         int ret = 0;
1076
1077         ret = clk_enable(xqspi->pclk);
1078         if (ret) {
1079                 dev_err(dev, "Cannot enable APB clock.\n");
1080                 return ret;
1081         }
1082
1083         ret = clk_enable(xqspi->refclk);
1084         if (ret) {
1085                 dev_err(dev, "Cannot enable device clock.\n");
1086                 clk_disable(xqspi->pclk);
1087                 return ret;
1088         }
1089
1090         zynqmp_qspi_init_hw(xqspi);
1091         spi_master_resume(master);
1092
1093         clk_disable(xqspi->refclk);
1094         clk_disable(xqspi->pclk);
1095
1096         return 0;
1097 }
1098
1099 /**
1100  * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
1101  * @dev:        Address of the platform_device structure
1102  *
1103  * This function disables the clocks
1104  *
1105  * Return:      Always 0
1106  */
1107 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
1108 {
1109         struct platform_device *pdev = to_platform_device(dev);
1110         struct spi_master *master = platform_get_drvdata(pdev);
1111         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1112
1113         clk_disable(xqspi->refclk);
1114         clk_disable(xqspi->pclk);
1115
1116         return 0;
1117 }
1118
1119 /**
1120  * zynqmp_runtime_resume - Runtime resume method for the SPI driver
1121  * @dev:        Address of the platform_device structure
1122  *
1123  * This function enables the clocks
1124  *
1125  * Return:      0 on success and error value on error
1126  */
1127 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
1128 {
1129         struct platform_device *pdev = to_platform_device(dev);
1130         struct spi_master *master = platform_get_drvdata(pdev);
1131         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1132         int ret;
1133
1134         ret = clk_enable(xqspi->pclk);
1135         if (ret) {
1136                 dev_err(dev, "Cannot enable APB clock.\n");
1137                 return ret;
1138         }
1139
1140         ret = clk_enable(xqspi->refclk);
1141         if (ret) {
1142                 dev_err(dev, "Cannot enable device clock.\n");
1143                 clk_disable(xqspi->pclk);
1144                 return ret;
1145         }
1146
1147         return 0;
1148 }
1149
1150 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1151         SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1152                            zynqmp_runtime_resume, NULL)
1153         SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1154 };
1155
1156 /**
1157  * zynqmp_qspi_probe -  Probe method for the QSPI driver
1158  * @pdev:       Pointer to the platform_device structure
1159  *
1160  * This function initializes the driver data structures and the hardware.
1161  *
1162  * Return:      0 on success; error value otherwise
1163  */
1164 static int zynqmp_qspi_probe(struct platform_device *pdev)
1165 {
1166         int ret = 0;
1167         struct spi_master *master;
1168         struct zynqmp_qspi *xqspi;
1169         struct resource *res;
1170         struct device *dev = &pdev->dev;
1171         struct device_node *nc;
1172         u32 num_cs;
1173         u32 rx_bus_width;
1174
1175         master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1176         if (!master)
1177                 return -ENOMEM;
1178
1179         xqspi = spi_master_get_devdata(master);
1180         master->dev.of_node = pdev->dev.of_node;
1181         platform_set_drvdata(pdev, master);
1182
1183         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184         xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1185         if (IS_ERR(xqspi->regs)) {
1186                 ret = PTR_ERR(xqspi->regs);
1187                 goto remove_master;
1188         }
1189
1190         xqspi->dev = dev;
1191         xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1192         if (IS_ERR(xqspi->pclk)) {
1193                 dev_err(dev, "pclk clock not found.\n");
1194                 ret = PTR_ERR(xqspi->pclk);
1195                 goto remove_master;
1196         }
1197
1198         ret = clk_prepare_enable(xqspi->pclk);
1199         if (ret) {
1200                 dev_err(dev, "Unable to enable APB clock.\n");
1201                 goto remove_master;
1202         }
1203
1204         xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1205         if (IS_ERR(xqspi->refclk)) {
1206                 dev_err(dev, "ref_clk clock not found.\n");
1207                 ret = PTR_ERR(xqspi->refclk);
1208                 goto clk_dis_pclk;
1209         }
1210
1211         ret = clk_prepare_enable(xqspi->refclk);
1212         if (ret) {
1213                 dev_err(dev, "Unable to enable device clock.\n");
1214                 goto clk_dis_pclk;
1215         }
1216
1217         pm_runtime_use_autosuspend(&pdev->dev);
1218         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1219         pm_runtime_set_active(&pdev->dev);
1220         pm_runtime_enable(&pdev->dev);
1221
1222         if (of_property_read_bool(pdev->dev.of_node, "has-io-mode"))
1223                 xqspi->io_mode = true;
1224
1225         /* QSPI controller initializations */
1226         zynqmp_qspi_init_hw(xqspi);
1227
1228         pm_runtime_mark_last_busy(&pdev->dev);
1229         pm_runtime_put_autosuspend(&pdev->dev);
1230
1231         xqspi->irq = platform_get_irq(pdev, 0);
1232         if (xqspi->irq <= 0) {
1233                 ret = -ENXIO;
1234                 dev_err(dev, "irq resource not found\n");
1235                 goto clk_dis_all;
1236         }
1237         ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1238                                0, pdev->name, master);
1239         if (ret != 0) {
1240                 ret = -ENXIO;
1241                 dev_err(dev, "request_irq failed\n");
1242                 goto clk_dis_all;
1243         }
1244
1245         xqspi->rx_bus_width = GQSPI_RX_BUS_WIDTH_SINGLE;
1246         for_each_available_child_of_node(pdev->dev.of_node, nc) {
1247                 ret = of_property_read_u32(nc, "spi-rx-bus-width",
1248                                         &rx_bus_width);
1249                 if (!ret) {
1250                         xqspi->rx_bus_width = rx_bus_width;
1251                         break;
1252                 }
1253         }
1254         if (ret)
1255                 dev_err(dev, "rx bus width not found\n");
1256
1257         ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
1258         if (ret < 0)
1259                 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1260         else
1261                 master->num_chipselect = num_cs;
1262
1263         master->setup = zynqmp_qspi_setup;
1264         master->set_cs = zynqmp_qspi_chipselect;
1265         master->transfer_one = zynqmp_qspi_start_transfer;
1266         master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1267         master->unprepare_transfer_hardware =
1268                                         zynqmp_unprepare_transfer_hardware;
1269         master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1270         master->bits_per_word_mask = SPI_BPW_MASK(8);
1271         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1272                             SPI_TX_DUAL | SPI_TX_QUAD;
1273         xqspi->speed_hz = master->max_speed_hz;
1274         master->auto_runtime_pm = true;
1275
1276         if (master->dev.parent == NULL)
1277                 master->dev.parent = &master->dev;
1278
1279         ret = spi_register_master(master);
1280         if (ret)
1281                 goto clk_dis_all;
1282
1283         dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1284
1285         return 0;
1286
1287 clk_dis_all:
1288         pm_runtime_set_suspended(&pdev->dev);
1289         pm_runtime_disable(&pdev->dev);
1290         clk_disable_unprepare(xqspi->refclk);
1291 clk_dis_pclk:
1292         clk_disable_unprepare(xqspi->pclk);
1293 remove_master:
1294         spi_master_put(master);
1295
1296         return ret;
1297 }
1298
1299 /**
1300  * zynqmp_qspi_remove - Remove method for the QSPI driver
1301  * @pdev:       Pointer to the platform_device structure
1302  *
1303  * This function is called if a device is physically removed from the system or
1304  * if the driver module is being unloaded. It frees all resources allocated to
1305  * the device.
1306  *
1307  * Return:      0 Always
1308  */
1309 static int zynqmp_qspi_remove(struct platform_device *pdev)
1310 {
1311         struct spi_master *master = platform_get_drvdata(pdev);
1312         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1313
1314         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1315         clk_disable_unprepare(xqspi->refclk);
1316         clk_disable_unprepare(xqspi->pclk);
1317         pm_runtime_set_suspended(&pdev->dev);
1318         pm_runtime_disable(&pdev->dev);
1319
1320         spi_unregister_master(master);
1321
1322         return 0;
1323 }
1324
1325 static const struct of_device_id zynqmp_qspi_of_match[] = {
1326         { .compatible = "xlnx,zynqmp-qspi-1.0", },
1327         { /* End of table */ }
1328 };
1329
1330 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1331
1332 static struct platform_driver zynqmp_qspi_driver = {
1333         .probe = zynqmp_qspi_probe,
1334         .remove = zynqmp_qspi_remove,
1335         .driver = {
1336                 .name = "zynqmp-qspi",
1337                 .of_match_table = zynqmp_qspi_of_match,
1338                 .pm = &zynqmp_qspi_dev_pm_ops,
1339         },
1340 };
1341
1342 module_platform_driver(zynqmp_qspi_driver);
1343
1344 MODULE_AUTHOR("Xilinx, Inc.");
1345 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1346 MODULE_LICENSE("GPL");