5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #include <linux/interrupt.h>
44 #include <linux/bitops.h>
45 #include <linux/leds.h>
47 #include <linux/mtd/partitions.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8 = {
60 static struct nand_ecclayout nand_oob_16 = {
62 .eccpos = {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64 = {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128 = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info *mtd, int new_state);
95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger);
104 static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
107 struct nand_chip *chip = mtd->priv;
110 /* Start address must align on block boundary */
111 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__);
116 /* Length must align on block boundary */
117 if (len & ((1 << chip->phys_erase_shift) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info *mtd)
133 struct nand_chip *chip = mtd->priv;
135 /* Release the controller and the chip */
136 spin_lock(&chip->controller->lock);
137 chip->controller->active = NULL;
138 chip->state = FL_READY;
139 wake_up(&chip->controller->wq);
140 spin_unlock(&chip->controller->lock);
144 * nand_read_byte - [DEFAULT] read one byte from the chip
145 * @mtd: MTD device structure
147 * Default read function for 8bit buswidth
149 static uint8_t nand_read_byte(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return readb(chip->IO_ADDR_R);
156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
157 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
158 * @mtd: MTD device structure
160 * Default read function for 16bit buswidth with endianness conversion.
163 static uint8_t nand_read_byte16(struct mtd_info *mtd)
165 struct nand_chip *chip = mtd->priv;
166 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
170 * nand_read_word - [DEFAULT] read one word from the chip
171 * @mtd: MTD device structure
173 * Default read function for 16bit buswidth without endianness conversion.
175 static u16 nand_read_word(struct mtd_info *mtd)
177 struct nand_chip *chip = mtd->priv;
178 return readw(chip->IO_ADDR_R);
182 * nand_select_chip - [DEFAULT] control CE line
183 * @mtd: MTD device structure
184 * @chipnr: chipnumber to select, -1 for deselect
186 * Default select function for 1 chip devices.
188 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
190 struct nand_chip *chip = mtd->priv;
194 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
205 * nand_write_buf - [DEFAULT] write buffer to chip
206 * @mtd: MTD device structure
208 * @len: number of bytes to write
210 * Default write function for 8bit buswidth.
212 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
215 struct nand_chip *chip = mtd->priv;
217 for (i = 0; i < len; i++)
218 writeb(buf[i], chip->IO_ADDR_W);
222 * nand_read_buf - [DEFAULT] read chip data into buffer
223 * @mtd: MTD device structure
224 * @buf: buffer to store date
225 * @len: number of bytes to read
227 * Default read function for 8bit buswidth.
229 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
232 struct nand_chip *chip = mtd->priv;
234 for (i = 0; i < len; i++)
235 buf[i] = readb(chip->IO_ADDR_R);
239 * nand_write_buf16 - [DEFAULT] write buffer to chip
240 * @mtd: MTD device structure
242 * @len: number of bytes to write
244 * Default write function for 16bit buswidth.
246 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
249 struct nand_chip *chip = mtd->priv;
250 u16 *p = (u16 *) buf;
253 for (i = 0; i < len; i++)
254 writew(p[i], chip->IO_ADDR_W);
259 * nand_read_buf16 - [DEFAULT] read chip data into buffer
260 * @mtd: MTD device structure
261 * @buf: buffer to store date
262 * @len: number of bytes to read
264 * Default read function for 16bit buswidth.
266 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
269 struct nand_chip *chip = mtd->priv;
270 u16 *p = (u16 *) buf;
273 for (i = 0; i < len; i++)
274 p[i] = readw(chip->IO_ADDR_R);
278 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
279 * @mtd: MTD device structure
280 * @ofs: offset from device start
281 * @getchip: 0, if the chip is already selected
283 * Check, if the block is bad.
285 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
287 int page, chipnr, res = 0, i = 0;
288 struct nand_chip *chip = mtd->priv;
291 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
292 ofs += mtd->erasesize - mtd->writesize;
294 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
297 chipnr = (int)(ofs >> chip->chip_shift);
299 nand_get_device(mtd, FL_READING);
301 /* Select the NAND device */
302 chip->select_chip(mtd, chipnr);
306 if (chip->options & NAND_BUSWIDTH_16) {
307 chip->cmdfunc(mtd, NAND_CMD_READOOB,
308 chip->badblockpos & 0xFE, page);
309 bad = cpu_to_le16(chip->read_word(mtd));
310 if (chip->badblockpos & 0x1)
315 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
317 bad = chip->read_byte(mtd);
320 if (likely(chip->badblockbits == 8))
323 res = hweight8(bad) < chip->badblockbits;
324 ofs += mtd->writesize;
325 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
327 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
330 chip->select_chip(mtd, -1);
331 nand_release_device(mtd);
338 * nand_default_block_markbad - [DEFAULT] mark a block bad
339 * @mtd: MTD device structure
340 * @ofs: offset from device start
342 * This is the default implementation, which can be overridden by a hardware
343 * specific driver. We try operations in the following order, according to our
344 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
345 * (1) erase the affected block, to allow OOB marker to be written cleanly
346 * (2) update in-memory BBT
347 * (3) write bad block marker to OOB area of affected block
348 * (4) update flash-based BBT
349 * Note that we retain the first error encountered in (3) or (4), finish the
350 * procedures, and dump the error in the end.
352 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
354 struct nand_chip *chip = mtd->priv;
355 uint8_t buf[2] = { 0, 0 };
356 int block, res, ret = 0, i = 0;
357 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
360 struct erase_info einfo;
362 /* Attempt erase before marking OOB */
363 memset(&einfo, 0, sizeof(einfo));
366 einfo.len = 1 << chip->phys_erase_shift;
367 nand_erase_nand(mtd, &einfo, 0);
370 /* Get block number */
371 block = (int)(ofs >> chip->bbt_erase_shift);
372 /* Mark block bad in memory-based BBT */
374 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
376 /* Write bad block marker to OOB */
378 struct mtd_oob_ops ops;
381 nand_get_device(mtd, FL_WRITING);
385 ops.ooboffs = chip->badblockpos;
386 if (chip->options & NAND_BUSWIDTH_16) {
387 ops.ooboffs &= ~0x01;
388 ops.len = ops.ooblen = 2;
390 ops.len = ops.ooblen = 1;
392 ops.mode = MTD_OPS_PLACE_OOB;
394 /* Write to first/last page(s) if necessary */
395 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
396 wr_ofs += mtd->erasesize - mtd->writesize;
398 res = nand_do_write_oob(mtd, wr_ofs, &ops);
403 wr_ofs += mtd->writesize;
404 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
406 nand_release_device(mtd);
409 /* Update flash-based bad block table */
410 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
411 res = nand_update_bbt(mtd, ofs);
417 mtd->ecc_stats.badblocks++;
423 * nand_check_wp - [GENERIC] check if the chip is write protected
424 * @mtd: MTD device structure
426 * Check, if the device is write protected. The function expects, that the
427 * device is already selected.
429 static int nand_check_wp(struct mtd_info *mtd)
431 struct nand_chip *chip = mtd->priv;
433 /* Broken xD cards report WP despite being writable */
434 if (chip->options & NAND_BROKEN_XD)
437 /* Check the WP bit */
438 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
439 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
443 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
444 * @mtd: MTD device structure
445 * @ofs: offset from device start
446 * @getchip: 0, if the chip is already selected
447 * @allowbbt: 1, if its allowed to access the bbt area
449 * Check, if the block is bad. Either by reading the bad block table or
450 * calling of the scan function.
452 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
455 struct nand_chip *chip = mtd->priv;
458 return chip->block_bad(mtd, ofs, getchip);
460 /* Return info from the table */
461 return nand_isbad_bbt(mtd, ofs, allowbbt);
465 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
466 * @mtd: MTD device structure
469 * Helper function for nand_wait_ready used when needing to wait in interrupt
472 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
474 struct nand_chip *chip = mtd->priv;
477 /* Wait for the device to get ready */
478 for (i = 0; i < timeo; i++) {
479 if (chip->dev_ready(mtd))
481 touch_softlockup_watchdog();
486 /* Wait for the ready pin, after a command. The timeout is caught later. */
487 void nand_wait_ready(struct mtd_info *mtd)
489 struct nand_chip *chip = mtd->priv;
490 unsigned long timeo = jiffies + msecs_to_jiffies(20);
493 if (in_interrupt() || oops_in_progress)
494 return panic_nand_wait_ready(mtd, 400);
496 led_trigger_event(nand_led_trigger, LED_FULL);
497 /* Wait until command is processed or timeout occurs */
499 if (chip->dev_ready(mtd))
501 touch_softlockup_watchdog();
502 } while (time_before(jiffies, timeo));
503 led_trigger_event(nand_led_trigger, LED_OFF);
505 EXPORT_SYMBOL_GPL(nand_wait_ready);
508 * nand_command - [DEFAULT] Send command to NAND device
509 * @mtd: MTD device structure
510 * @command: the command to be sent
511 * @column: the column address for this command, -1 if none
512 * @page_addr: the page address for this command, -1 if none
514 * Send command to NAND device. This function is used for small page devices
515 * (512 Bytes per page).
517 static void nand_command(struct mtd_info *mtd, unsigned int command,
518 int column, int page_addr)
520 register struct nand_chip *chip = mtd->priv;
521 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
523 /* Write out the command to the device */
524 if (command == NAND_CMD_SEQIN) {
527 if (column >= mtd->writesize) {
529 column -= mtd->writesize;
530 readcmd = NAND_CMD_READOOB;
531 } else if (column < 256) {
532 /* First 256 bytes --> READ0 */
533 readcmd = NAND_CMD_READ0;
536 readcmd = NAND_CMD_READ1;
538 chip->cmd_ctrl(mtd, readcmd, ctrl);
539 ctrl &= ~NAND_CTRL_CHANGE;
541 chip->cmd_ctrl(mtd, command, ctrl);
543 /* Address cycle, when necessary */
544 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
545 /* Serially input address */
547 /* Adjust columns for 16 bit buswidth */
548 if (chip->options & NAND_BUSWIDTH_16)
550 chip->cmd_ctrl(mtd, column, ctrl);
551 ctrl &= ~NAND_CTRL_CHANGE;
553 if (page_addr != -1) {
554 chip->cmd_ctrl(mtd, page_addr, ctrl);
555 ctrl &= ~NAND_CTRL_CHANGE;
556 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
557 /* One more address cycle for devices > 32MiB */
558 if (chip->chipsize > (32 << 20))
559 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
561 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
564 * Program and erase have their own busy handlers status and sequential
569 case NAND_CMD_PAGEPROG:
570 case NAND_CMD_ERASE1:
571 case NAND_CMD_ERASE2:
573 case NAND_CMD_STATUS:
579 udelay(chip->chip_delay);
580 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
581 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
583 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
584 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
588 /* This applies to read commands */
591 * If we don't have access to the busy pin, we apply the given
594 if (!chip->dev_ready) {
595 udelay(chip->chip_delay);
600 * Apply this short delay always to ensure that we do wait tWB in
601 * any case on any machine.
605 nand_wait_ready(mtd);
609 * nand_command_lp - [DEFAULT] Send command to NAND large page device
610 * @mtd: MTD device structure
611 * @command: the command to be sent
612 * @column: the column address for this command, -1 if none
613 * @page_addr: the page address for this command, -1 if none
615 * Send command to NAND device. This is the version for the new large page
616 * devices. We don't have the separate regions as we have in the small page
617 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
619 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
620 int column, int page_addr)
622 register struct nand_chip *chip = mtd->priv;
624 /* Emulate NAND_CMD_READOOB */
625 if (command == NAND_CMD_READOOB) {
626 column += mtd->writesize;
627 command = NAND_CMD_READ0;
630 /* Command latch cycle */
631 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
633 if (column != -1 || page_addr != -1) {
634 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
636 /* Serially input address */
638 /* Adjust columns for 16 bit buswidth */
639 if (chip->options & NAND_BUSWIDTH_16)
641 chip->cmd_ctrl(mtd, column, ctrl);
642 ctrl &= ~NAND_CTRL_CHANGE;
643 chip->cmd_ctrl(mtd, column >> 8, ctrl);
645 if (page_addr != -1) {
646 chip->cmd_ctrl(mtd, page_addr, ctrl);
647 chip->cmd_ctrl(mtd, page_addr >> 8,
648 NAND_NCE | NAND_ALE);
649 /* One more address cycle for devices > 128MiB */
650 if (chip->chipsize > (128 << 20))
651 chip->cmd_ctrl(mtd, page_addr >> 16,
652 NAND_NCE | NAND_ALE);
655 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
658 * Program and erase have their own busy handlers status, sequential
659 * in, and deplete1 need no delay.
663 case NAND_CMD_CACHEDPROG:
664 case NAND_CMD_PAGEPROG:
665 case NAND_CMD_ERASE1:
666 case NAND_CMD_ERASE2:
669 case NAND_CMD_STATUS:
675 udelay(chip->chip_delay);
676 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
677 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
678 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
679 NAND_NCE | NAND_CTRL_CHANGE);
680 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
684 case NAND_CMD_RNDOUT:
685 /* No ready / busy check necessary */
686 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
687 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
688 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
689 NAND_NCE | NAND_CTRL_CHANGE);
693 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
694 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
695 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
696 NAND_NCE | NAND_CTRL_CHANGE);
698 /* This applies to read commands */
701 * If we don't have access to the busy pin, we apply the given
704 if (!chip->dev_ready) {
705 udelay(chip->chip_delay);
711 * Apply this short delay always to ensure that we do wait tWB in
712 * any case on any machine.
716 nand_wait_ready(mtd);
720 * panic_nand_get_device - [GENERIC] Get chip for selected access
721 * @chip: the nand chip descriptor
722 * @mtd: MTD device structure
723 * @new_state: the state which is requested
725 * Used when in panic, no locks are taken.
727 static void panic_nand_get_device(struct nand_chip *chip,
728 struct mtd_info *mtd, int new_state)
730 /* Hardware controller shared among independent devices */
731 chip->controller->active = chip;
732 chip->state = new_state;
736 * nand_get_device - [GENERIC] Get chip for selected access
737 * @mtd: MTD device structure
738 * @new_state: the state which is requested
740 * Get the device and lock it for exclusive access
743 nand_get_device(struct mtd_info *mtd, int new_state)
745 struct nand_chip *chip = mtd->priv;
746 spinlock_t *lock = &chip->controller->lock;
747 wait_queue_head_t *wq = &chip->controller->wq;
748 DECLARE_WAITQUEUE(wait, current);
752 /* Hardware controller shared among independent devices */
753 if (!chip->controller->active)
754 chip->controller->active = chip;
756 if (chip->controller->active == chip && chip->state == FL_READY) {
757 chip->state = new_state;
761 if (new_state == FL_PM_SUSPENDED) {
762 if (chip->controller->active->state == FL_PM_SUSPENDED) {
763 chip->state = FL_PM_SUSPENDED;
768 set_current_state(TASK_UNINTERRUPTIBLE);
769 add_wait_queue(wq, &wait);
772 remove_wait_queue(wq, &wait);
777 * panic_nand_wait - [GENERIC] wait until the command is done
778 * @mtd: MTD device structure
779 * @chip: NAND chip structure
782 * Wait for command done. This is a helper function for nand_wait used when
783 * we are in interrupt context. May happen when in panic and trying to write
784 * an oops through mtdoops.
786 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
790 for (i = 0; i < timeo; i++) {
791 if (chip->dev_ready) {
792 if (chip->dev_ready(mtd))
795 if (chip->read_byte(mtd) & NAND_STATUS_READY)
803 * nand_wait - [DEFAULT] wait until the command is done
804 * @mtd: MTD device structure
805 * @chip: NAND chip structure
807 * Wait for command done. This applies to erase and program only. Erase can
808 * take up to 400ms and program up to 20ms according to general NAND and
811 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
814 int status, state = chip->state;
815 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
817 #if defined(ARCH_ZYNQ) && (CONFIG_HZ == 20)
818 /* Xilinx Zynq NAND work around for HZ=20 */
822 led_trigger_event(nand_led_trigger, LED_FULL);
825 * Apply this short delay always to ensure that we do wait tWB in any
826 * case on any machine.
830 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
832 if (in_interrupt() || oops_in_progress)
833 panic_nand_wait(mtd, chip, timeo);
835 timeo = jiffies + msecs_to_jiffies(timeo);
836 while (time_before(jiffies, timeo)) {
837 if (chip->dev_ready) {
838 if (chip->dev_ready(mtd))
841 if (chip->read_byte(mtd) & NAND_STATUS_READY)
847 led_trigger_event(nand_led_trigger, LED_OFF);
849 status = (int)chip->read_byte(mtd);
850 /* This can happen if in case of timeout or buggy dev_ready */
851 WARN_ON(!(status & NAND_STATUS_READY));
856 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
858 * @ofs: offset to start unlock from
859 * @len: length to unlock
860 * @invert: when = 0, unlock the range of blocks within the lower and
861 * upper boundary address
862 * when = 1, unlock the range of blocks outside the boundaries
863 * of the lower and upper boundary address
865 * Returs unlock status.
867 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
868 uint64_t len, int invert)
872 struct nand_chip *chip = mtd->priv;
874 /* Submit address of first page to unlock */
875 page = ofs >> chip->page_shift;
876 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
878 /* Submit address of last page to unlock */
879 page = (ofs + len) >> chip->page_shift;
880 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
881 (page | invert) & chip->pagemask);
883 /* Call wait ready function */
884 status = chip->waitfunc(mtd, chip);
885 /* See if device thinks it succeeded */
886 if (status & NAND_STATUS_FAIL) {
887 pr_debug("%s: error status = 0x%08x\n",
896 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
898 * @ofs: offset to start unlock from
899 * @len: length to unlock
901 * Returns unlock status.
903 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
907 struct nand_chip *chip = mtd->priv;
909 pr_debug("%s: start = 0x%012llx, len = %llu\n",
910 __func__, (unsigned long long)ofs, len);
912 if (check_offs_len(mtd, ofs, len))
915 /* Align to last block address if size addresses end of the device */
916 if (ofs + len == mtd->size)
917 len -= mtd->erasesize;
919 nand_get_device(mtd, FL_UNLOCKING);
921 /* Shift to get chip number */
922 chipnr = ofs >> chip->chip_shift;
924 chip->select_chip(mtd, chipnr);
926 /* Check, if it is write protected */
927 if (nand_check_wp(mtd)) {
928 pr_debug("%s: device is write protected!\n",
934 ret = __nand_unlock(mtd, ofs, len, 0);
937 chip->select_chip(mtd, -1);
938 nand_release_device(mtd);
942 EXPORT_SYMBOL(nand_unlock);
945 * nand_lock - [REPLACEABLE] locks all blocks present in the device
947 * @ofs: offset to start unlock from
948 * @len: length to unlock
950 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
951 * have this feature, but it allows only to lock all blocks, not for specified
952 * range for block. Implementing 'lock' feature by making use of 'unlock', for
955 * Returns lock status.
957 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
960 int chipnr, status, page;
961 struct nand_chip *chip = mtd->priv;
963 pr_debug("%s: start = 0x%012llx, len = %llu\n",
964 __func__, (unsigned long long)ofs, len);
966 if (check_offs_len(mtd, ofs, len))
969 nand_get_device(mtd, FL_LOCKING);
971 /* Shift to get chip number */
972 chipnr = ofs >> chip->chip_shift;
974 chip->select_chip(mtd, chipnr);
976 /* Check, if it is write protected */
977 if (nand_check_wp(mtd)) {
978 pr_debug("%s: device is write protected!\n",
980 status = MTD_ERASE_FAILED;
985 /* Submit address of first page to lock */
986 page = ofs >> chip->page_shift;
987 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
989 /* Call wait ready function */
990 status = chip->waitfunc(mtd, chip);
991 /* See if device thinks it succeeded */
992 if (status & NAND_STATUS_FAIL) {
993 pr_debug("%s: error status = 0x%08x\n",
999 ret = __nand_unlock(mtd, ofs, len, 0x1);
1002 chip->select_chip(mtd, -1);
1003 nand_release_device(mtd);
1007 EXPORT_SYMBOL(nand_lock);
1010 * nand_read_page_raw - [INTERN] read raw page data without ecc
1011 * @mtd: mtd info structure
1012 * @chip: nand chip info structure
1013 * @buf: buffer to store read data
1014 * @oob_required: caller requires OOB data read to chip->oob_poi
1015 * @page: page number to read
1017 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1019 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1020 uint8_t *buf, int oob_required, int page)
1022 chip->read_buf(mtd, buf, mtd->writesize);
1024 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1029 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1030 * @mtd: mtd info structure
1031 * @chip: nand chip info structure
1032 * @buf: buffer to store read data
1033 * @oob_required: caller requires OOB data read to chip->oob_poi
1034 * @page: page number to read
1036 * We need a special oob layout and handling even when OOB isn't used.
1038 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1039 struct nand_chip *chip, uint8_t *buf,
1040 int oob_required, int page)
1042 int eccsize = chip->ecc.size;
1043 int eccbytes = chip->ecc.bytes;
1044 uint8_t *oob = chip->oob_poi;
1047 for (steps = chip->ecc.steps; steps > 0; steps--) {
1048 chip->read_buf(mtd, buf, eccsize);
1051 if (chip->ecc.prepad) {
1052 chip->read_buf(mtd, oob, chip->ecc.prepad);
1053 oob += chip->ecc.prepad;
1056 chip->read_buf(mtd, oob, eccbytes);
1059 if (chip->ecc.postpad) {
1060 chip->read_buf(mtd, oob, chip->ecc.postpad);
1061 oob += chip->ecc.postpad;
1065 size = mtd->oobsize - (oob - chip->oob_poi);
1067 chip->read_buf(mtd, oob, size);
1073 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1074 * @mtd: mtd info structure
1075 * @chip: nand chip info structure
1076 * @buf: buffer to store read data
1077 * @oob_required: caller requires OOB data read to chip->oob_poi
1078 * @page: page number to read
1080 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1081 uint8_t *buf, int oob_required, int page)
1083 int i, eccsize = chip->ecc.size;
1084 int eccbytes = chip->ecc.bytes;
1085 int eccsteps = chip->ecc.steps;
1087 uint8_t *ecc_calc = chip->buffers->ecccalc;
1088 uint8_t *ecc_code = chip->buffers->ecccode;
1089 uint32_t *eccpos = chip->ecc.layout->eccpos;
1090 unsigned int max_bitflips = 0;
1092 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1094 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1095 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1097 for (i = 0; i < chip->ecc.total; i++)
1098 ecc_code[i] = chip->oob_poi[eccpos[i]];
1100 eccsteps = chip->ecc.steps;
1103 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1106 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1108 mtd->ecc_stats.failed++;
1110 mtd->ecc_stats.corrected += stat;
1111 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1114 return max_bitflips;
1118 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1119 * @mtd: mtd info structure
1120 * @chip: nand chip info structure
1121 * @data_offs: offset of requested data within the page
1122 * @readlen: data length
1123 * @bufpoi: buffer to store read data
1125 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1126 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1128 int start_step, end_step, num_steps;
1129 uint32_t *eccpos = chip->ecc.layout->eccpos;
1131 int data_col_addr, i, gaps = 0;
1132 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1133 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1135 unsigned int max_bitflips = 0;
1137 /* Column address within the page aligned to ECC size (256bytes) */
1138 start_step = data_offs / chip->ecc.size;
1139 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1140 num_steps = end_step - start_step + 1;
1142 /* Data size aligned to ECC ecc.size */
1143 datafrag_len = num_steps * chip->ecc.size;
1144 eccfrag_len = num_steps * chip->ecc.bytes;
1146 data_col_addr = start_step * chip->ecc.size;
1147 /* If we read not a page aligned data */
1148 if (data_col_addr != 0)
1149 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1151 p = bufpoi + data_col_addr;
1152 chip->read_buf(mtd, p, datafrag_len);
1155 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1156 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1159 * The performance is faster if we position offsets according to
1160 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1162 for (i = 0; i < eccfrag_len - 1; i++) {
1163 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1164 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1170 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1171 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1174 * Send the command to read the particular ECC bytes take care
1175 * about buswidth alignment in read_buf.
1177 index = start_step * chip->ecc.bytes;
1179 aligned_pos = eccpos[index] & ~(busw - 1);
1180 aligned_len = eccfrag_len;
1181 if (eccpos[index] & (busw - 1))
1183 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1186 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1187 mtd->writesize + aligned_pos, -1);
1188 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1191 for (i = 0; i < eccfrag_len; i++)
1192 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1194 p = bufpoi + data_col_addr;
1195 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1198 stat = chip->ecc.correct(mtd, p,
1199 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1201 mtd->ecc_stats.failed++;
1203 mtd->ecc_stats.corrected += stat;
1204 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1207 return max_bitflips;
1211 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1212 * @mtd: mtd info structure
1213 * @chip: nand chip info structure
1214 * @buf: buffer to store read data
1215 * @oob_required: caller requires OOB data read to chip->oob_poi
1216 * @page: page number to read
1218 * Not for syndrome calculating ECC controllers which need a special oob layout.
1220 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1221 uint8_t *buf, int oob_required, int page)
1223 int i, eccsize = chip->ecc.size;
1224 int eccbytes = chip->ecc.bytes;
1225 int eccsteps = chip->ecc.steps;
1227 uint8_t *ecc_calc = chip->buffers->ecccalc;
1228 uint8_t *ecc_code = chip->buffers->ecccode;
1229 uint32_t *eccpos = chip->ecc.layout->eccpos;
1230 unsigned int max_bitflips = 0;
1232 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1233 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1234 chip->read_buf(mtd, p, eccsize);
1235 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1237 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1239 for (i = 0; i < chip->ecc.total; i++)
1240 ecc_code[i] = chip->oob_poi[eccpos[i]];
1242 eccsteps = chip->ecc.steps;
1245 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1248 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1250 mtd->ecc_stats.failed++;
1252 mtd->ecc_stats.corrected += stat;
1253 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1256 return max_bitflips;
1260 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1261 * @mtd: mtd info structure
1262 * @chip: nand chip info structure
1263 * @buf: buffer to store read data
1264 * @oob_required: caller requires OOB data read to chip->oob_poi
1265 * @page: page number to read
1267 * Hardware ECC for large page chips, require OOB to be read first. For this
1268 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1269 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1270 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1271 * the data area, by overwriting the NAND manufacturer bad block markings.
1273 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1274 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1276 int i, eccsize = chip->ecc.size;
1277 int eccbytes = chip->ecc.bytes;
1278 int eccsteps = chip->ecc.steps;
1280 uint8_t *ecc_code = chip->buffers->ecccode;
1281 uint32_t *eccpos = chip->ecc.layout->eccpos;
1282 uint8_t *ecc_calc = chip->buffers->ecccalc;
1283 unsigned int max_bitflips = 0;
1285 /* Read the OOB area first */
1286 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1287 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1288 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1290 for (i = 0; i < chip->ecc.total; i++)
1291 ecc_code[i] = chip->oob_poi[eccpos[i]];
1293 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1296 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1297 chip->read_buf(mtd, p, eccsize);
1298 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1300 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1302 mtd->ecc_stats.failed++;
1304 mtd->ecc_stats.corrected += stat;
1305 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1308 return max_bitflips;
1312 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1313 * @mtd: mtd info structure
1314 * @chip: nand chip info structure
1315 * @buf: buffer to store read data
1316 * @oob_required: caller requires OOB data read to chip->oob_poi
1317 * @page: page number to read
1319 * The hw generator calculates the error syndrome automatically. Therefore we
1320 * need a special oob layout and handling.
1322 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1323 uint8_t *buf, int oob_required, int page)
1325 int i, eccsize = chip->ecc.size;
1326 int eccbytes = chip->ecc.bytes;
1327 int eccsteps = chip->ecc.steps;
1329 uint8_t *oob = chip->oob_poi;
1330 unsigned int max_bitflips = 0;
1332 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1335 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1336 chip->read_buf(mtd, p, eccsize);
1338 if (chip->ecc.prepad) {
1339 chip->read_buf(mtd, oob, chip->ecc.prepad);
1340 oob += chip->ecc.prepad;
1343 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1344 chip->read_buf(mtd, oob, eccbytes);
1345 stat = chip->ecc.correct(mtd, p, oob, NULL);
1348 mtd->ecc_stats.failed++;
1350 mtd->ecc_stats.corrected += stat;
1351 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1356 if (chip->ecc.postpad) {
1357 chip->read_buf(mtd, oob, chip->ecc.postpad);
1358 oob += chip->ecc.postpad;
1362 /* Calculate remaining oob bytes */
1363 i = mtd->oobsize - (oob - chip->oob_poi);
1365 chip->read_buf(mtd, oob, i);
1367 return max_bitflips;
1371 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1372 * @chip: nand chip structure
1373 * @oob: oob destination address
1374 * @ops: oob ops structure
1375 * @len: size of oob to transfer
1377 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1378 struct mtd_oob_ops *ops, size_t len)
1380 switch (ops->mode) {
1382 case MTD_OPS_PLACE_OOB:
1384 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1387 case MTD_OPS_AUTO_OOB: {
1388 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1389 uint32_t boffs = 0, roffs = ops->ooboffs;
1392 for (; free->length && len; free++, len -= bytes) {
1393 /* Read request not from offset 0? */
1394 if (unlikely(roffs)) {
1395 if (roffs >= free->length) {
1396 roffs -= free->length;
1399 boffs = free->offset + roffs;
1400 bytes = min_t(size_t, len,
1401 (free->length - roffs));
1404 bytes = min_t(size_t, len, free->length);
1405 boffs = free->offset;
1407 memcpy(oob, chip->oob_poi + boffs, bytes);
1419 * nand_do_read_ops - [INTERN] Read data with ECC
1420 * @mtd: MTD device structure
1421 * @from: offset to read from
1422 * @ops: oob ops structure
1424 * Internal function. Called with chip held.
1426 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1427 struct mtd_oob_ops *ops)
1429 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1430 struct nand_chip *chip = mtd->priv;
1431 struct mtd_ecc_stats stats;
1433 uint32_t readlen = ops->len;
1434 uint32_t oobreadlen = ops->ooblen;
1435 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1436 mtd->oobavail : mtd->oobsize;
1438 uint8_t *bufpoi, *oob, *buf;
1439 unsigned int max_bitflips = 0;
1441 stats = mtd->ecc_stats;
1443 chipnr = (int)(from >> chip->chip_shift);
1444 chip->select_chip(mtd, chipnr);
1446 realpage = (int)(from >> chip->page_shift);
1447 page = realpage & chip->pagemask;
1449 col = (int)(from & (mtd->writesize - 1));
1453 oob_required = oob ? 1 : 0;
1456 bytes = min(mtd->writesize - col, readlen);
1457 aligned = (bytes == mtd->writesize);
1459 /* Is the current page in the buffer? */
1460 if (realpage != chip->pagebuf || oob) {
1461 bufpoi = aligned ? buf : chip->buffers->databuf;
1463 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1466 * Now read the page into the buffer. Absent an error,
1467 * the read methods return max bitflips per ecc step.
1469 if (unlikely(ops->mode == MTD_OPS_RAW))
1470 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1473 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1475 ret = chip->ecc.read_subpage(mtd, chip,
1476 col, bytes, bufpoi);
1478 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1479 oob_required, page);
1482 /* Invalidate page cache */
1487 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1489 /* Transfer not aligned data */
1491 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1492 !(mtd->ecc_stats.failed - stats.failed) &&
1493 (ops->mode != MTD_OPS_RAW)) {
1494 chip->pagebuf = realpage;
1495 chip->pagebuf_bitflips = ret;
1497 /* Invalidate page cache */
1500 memcpy(buf, chip->buffers->databuf + col, bytes);
1505 if (unlikely(oob)) {
1506 int toread = min(oobreadlen, max_oobsize);
1509 oob = nand_transfer_oob(chip,
1511 oobreadlen -= toread;
1515 if (chip->options & NAND_NEED_READRDY) {
1516 /* Apply delay or wait for ready/busy pin */
1517 if (!chip->dev_ready)
1518 udelay(chip->chip_delay);
1520 nand_wait_ready(mtd);
1523 memcpy(buf, chip->buffers->databuf + col, bytes);
1525 max_bitflips = max_t(unsigned int, max_bitflips,
1526 chip->pagebuf_bitflips);
1534 /* For subsequent reads align to page boundary */
1536 /* Increment page address */
1539 page = realpage & chip->pagemask;
1540 /* Check, if we cross a chip boundary */
1543 chip->select_chip(mtd, -1);
1544 chip->select_chip(mtd, chipnr);
1547 chip->select_chip(mtd, -1);
1549 ops->retlen = ops->len - (size_t) readlen;
1551 ops->oobretlen = ops->ooblen - oobreadlen;
1556 if (mtd->ecc_stats.failed - stats.failed)
1559 return max_bitflips;
1563 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1564 * @mtd: MTD device structure
1565 * @from: offset to read from
1566 * @len: number of bytes to read
1567 * @retlen: pointer to variable to store the number of read bytes
1568 * @buf: the databuffer to put data
1570 * Get hold of the chip and call nand_do_read.
1572 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1573 size_t *retlen, uint8_t *buf)
1575 struct mtd_oob_ops ops;
1578 nand_get_device(mtd, FL_READING);
1582 ops.mode = MTD_OPS_PLACE_OOB;
1583 ret = nand_do_read_ops(mtd, from, &ops);
1584 *retlen = ops.retlen;
1585 nand_release_device(mtd);
1590 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1591 * @mtd: mtd info structure
1592 * @chip: nand chip info structure
1593 * @page: page number to read
1595 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1598 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1599 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1604 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1606 * @mtd: mtd info structure
1607 * @chip: nand chip info structure
1608 * @page: page number to read
1610 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1613 uint8_t *buf = chip->oob_poi;
1614 int length = mtd->oobsize;
1615 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1616 int eccsize = chip->ecc.size;
1617 uint8_t *bufpoi = buf;
1618 int i, toread, sndrnd = 0, pos;
1620 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1621 for (i = 0; i < chip->ecc.steps; i++) {
1623 pos = eccsize + i * (eccsize + chunk);
1624 if (mtd->writesize > 512)
1625 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1627 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1630 toread = min_t(int, length, chunk);
1631 chip->read_buf(mtd, bufpoi, toread);
1636 chip->read_buf(mtd, bufpoi, length);
1642 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1643 * @mtd: mtd info structure
1644 * @chip: nand chip info structure
1645 * @page: page number to write
1647 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1651 const uint8_t *buf = chip->oob_poi;
1652 int length = mtd->oobsize;
1654 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1655 chip->write_buf(mtd, buf, length);
1656 /* Send command to program the OOB data */
1657 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1659 status = chip->waitfunc(mtd, chip);
1661 return status & NAND_STATUS_FAIL ? -EIO : 0;
1665 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1666 * with syndrome - only for large page flash
1667 * @mtd: mtd info structure
1668 * @chip: nand chip info structure
1669 * @page: page number to write
1671 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1672 struct nand_chip *chip, int page)
1674 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1675 int eccsize = chip->ecc.size, length = mtd->oobsize;
1676 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1677 const uint8_t *bufpoi = chip->oob_poi;
1680 * data-ecc-data-ecc ... ecc-oob
1682 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1684 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1685 pos = steps * (eccsize + chunk);
1690 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1691 for (i = 0; i < steps; i++) {
1693 if (mtd->writesize <= 512) {
1694 uint32_t fill = 0xFFFFFFFF;
1698 int num = min_t(int, len, 4);
1699 chip->write_buf(mtd, (uint8_t *)&fill,
1704 pos = eccsize + i * (eccsize + chunk);
1705 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1709 len = min_t(int, length, chunk);
1710 chip->write_buf(mtd, bufpoi, len);
1715 chip->write_buf(mtd, bufpoi, length);
1717 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1718 status = chip->waitfunc(mtd, chip);
1720 return status & NAND_STATUS_FAIL ? -EIO : 0;
1724 * nand_do_read_oob - [INTERN] NAND read out-of-band
1725 * @mtd: MTD device structure
1726 * @from: offset to read from
1727 * @ops: oob operations description structure
1729 * NAND read out-of-band data from the spare area.
1731 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1732 struct mtd_oob_ops *ops)
1734 int page, realpage, chipnr;
1735 struct nand_chip *chip = mtd->priv;
1736 struct mtd_ecc_stats stats;
1737 int readlen = ops->ooblen;
1739 uint8_t *buf = ops->oobbuf;
1742 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1743 __func__, (unsigned long long)from, readlen);
1745 stats = mtd->ecc_stats;
1747 if (ops->mode == MTD_OPS_AUTO_OOB)
1748 len = chip->ecc.layout->oobavail;
1752 if (unlikely(ops->ooboffs >= len)) {
1753 pr_debug("%s: attempt to start read outside oob\n",
1758 /* Do not allow reads past end of device */
1759 if (unlikely(from >= mtd->size ||
1760 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1761 (from >> chip->page_shift)) * len)) {
1762 pr_debug("%s: attempt to read beyond end of device\n",
1767 chipnr = (int)(from >> chip->chip_shift);
1768 chip->select_chip(mtd, chipnr);
1770 /* Shift to get page */
1771 realpage = (int)(from >> chip->page_shift);
1772 page = realpage & chip->pagemask;
1775 if (ops->mode == MTD_OPS_RAW)
1776 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1778 ret = chip->ecc.read_oob(mtd, chip, page);
1783 len = min(len, readlen);
1784 buf = nand_transfer_oob(chip, buf, ops, len);
1786 if (chip->options & NAND_NEED_READRDY) {
1787 /* Apply delay or wait for ready/busy pin */
1788 if (!chip->dev_ready)
1789 udelay(chip->chip_delay);
1791 nand_wait_ready(mtd);
1798 /* Increment page address */
1801 page = realpage & chip->pagemask;
1802 /* Check, if we cross a chip boundary */
1805 chip->select_chip(mtd, -1);
1806 chip->select_chip(mtd, chipnr);
1809 chip->select_chip(mtd, -1);
1811 ops->oobretlen = ops->ooblen - readlen;
1816 if (mtd->ecc_stats.failed - stats.failed)
1819 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1823 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1824 * @mtd: MTD device structure
1825 * @from: offset to read from
1826 * @ops: oob operation description structure
1828 * NAND read data and/or out-of-band data.
1830 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1831 struct mtd_oob_ops *ops)
1833 int ret = -ENOTSUPP;
1837 /* Do not allow reads past end of device */
1838 if (ops->datbuf && (from + ops->len) > mtd->size) {
1839 pr_debug("%s: attempt to read beyond end of device\n",
1844 nand_get_device(mtd, FL_READING);
1846 switch (ops->mode) {
1847 case MTD_OPS_PLACE_OOB:
1848 case MTD_OPS_AUTO_OOB:
1857 ret = nand_do_read_oob(mtd, from, ops);
1859 ret = nand_do_read_ops(mtd, from, ops);
1862 nand_release_device(mtd);
1868 * nand_write_page_raw - [INTERN] raw page write function
1869 * @mtd: mtd info structure
1870 * @chip: nand chip info structure
1872 * @oob_required: must write chip->oob_poi to OOB
1874 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1876 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1877 const uint8_t *buf, int oob_required)
1879 chip->write_buf(mtd, buf, mtd->writesize);
1881 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1887 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1888 * @mtd: mtd info structure
1889 * @chip: nand chip info structure
1891 * @oob_required: must write chip->oob_poi to OOB
1893 * We need a special oob layout and handling even when ECC isn't checked.
1895 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1896 struct nand_chip *chip,
1897 const uint8_t *buf, int oob_required)
1899 int eccsize = chip->ecc.size;
1900 int eccbytes = chip->ecc.bytes;
1901 uint8_t *oob = chip->oob_poi;
1904 for (steps = chip->ecc.steps; steps > 0; steps--) {
1905 chip->write_buf(mtd, buf, eccsize);
1908 if (chip->ecc.prepad) {
1909 chip->write_buf(mtd, oob, chip->ecc.prepad);
1910 oob += chip->ecc.prepad;
1913 chip->read_buf(mtd, oob, eccbytes);
1916 if (chip->ecc.postpad) {
1917 chip->write_buf(mtd, oob, chip->ecc.postpad);
1918 oob += chip->ecc.postpad;
1922 size = mtd->oobsize - (oob - chip->oob_poi);
1924 chip->write_buf(mtd, oob, size);
1929 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1930 * @mtd: mtd info structure
1931 * @chip: nand chip info structure
1933 * @oob_required: must write chip->oob_poi to OOB
1935 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1936 const uint8_t *buf, int oob_required)
1938 int i, eccsize = chip->ecc.size;
1939 int eccbytes = chip->ecc.bytes;
1940 int eccsteps = chip->ecc.steps;
1941 uint8_t *ecc_calc = chip->buffers->ecccalc;
1942 const uint8_t *p = buf;
1943 uint32_t *eccpos = chip->ecc.layout->eccpos;
1945 /* Software ECC calculation */
1946 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1947 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1949 for (i = 0; i < chip->ecc.total; i++)
1950 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1952 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1956 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1957 * @mtd: mtd info structure
1958 * @chip: nand chip info structure
1960 * @oob_required: must write chip->oob_poi to OOB
1962 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1963 const uint8_t *buf, int oob_required)
1965 int i, eccsize = chip->ecc.size;
1966 int eccbytes = chip->ecc.bytes;
1967 int eccsteps = chip->ecc.steps;
1968 uint8_t *ecc_calc = chip->buffers->ecccalc;
1969 const uint8_t *p = buf;
1970 uint32_t *eccpos = chip->ecc.layout->eccpos;
1972 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1973 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1974 chip->write_buf(mtd, p, eccsize);
1975 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1978 for (i = 0; i < chip->ecc.total; i++)
1979 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1981 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1988 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1989 * @mtd: mtd info structure
1990 * @chip: nand chip info structure
1991 * @column: column address of subpage within the page
1992 * @data_len: data length
1993 * @oob_required: must write chip->oob_poi to OOB
1995 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1996 struct nand_chip *chip, uint32_t offset,
1997 uint32_t data_len, const uint8_t *data_buf,
2000 uint8_t *oob_buf = chip->oob_poi;
2001 uint8_t *ecc_calc = chip->buffers->ecccalc;
2002 int ecc_size = chip->ecc.size;
2003 int ecc_bytes = chip->ecc.bytes;
2004 int ecc_steps = chip->ecc.steps;
2005 uint32_t *eccpos = chip->ecc.layout->eccpos;
2006 uint32_t start_step = offset / ecc_size;
2007 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2008 int oob_bytes = mtd->oobsize / ecc_steps;
2011 for (step = 0; step < ecc_steps; step++) {
2012 /* configure controller for WRITE access */
2013 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2015 /* write data (untouched subpages already masked by 0xFF) */
2016 chip->write_buf(mtd, data_buf, ecc_size);
2018 /* mask ECC of un-touched subpages by padding 0xFF */
2019 if ((step < start_step) || (step > end_step))
2020 memset(ecc_calc, 0xff, ecc_bytes);
2022 chip->ecc.calculate(mtd, data_buf, ecc_calc);
2024 /* mask OOB of un-touched subpages by padding 0xFF */
2025 /* if oob_required, preserve OOB metadata of written subpage */
2026 if (!oob_required || (step < start_step) || (step > end_step))
2027 memset(oob_buf, 0xff, oob_bytes);
2029 data_buf += ecc_size;
2030 ecc_calc += ecc_bytes;
2031 oob_buf += oob_bytes;
2034 /* copy calculated ECC for whole page to chip->buffer->oob */
2035 /* this include masked-value(0xFF) for unwritten subpages */
2036 ecc_calc = chip->buffers->ecccalc;
2037 for (i = 0; i < chip->ecc.total; i++)
2038 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2040 /* write OOB buffer to NAND device */
2041 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2048 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2049 * @mtd: mtd info structure
2050 * @chip: nand chip info structure
2052 * @oob_required: must write chip->oob_poi to OOB
2054 * The hw generator calculates the error syndrome automatically. Therefore we
2055 * need a special oob layout and handling.
2057 static int nand_write_page_syndrome(struct mtd_info *mtd,
2058 struct nand_chip *chip,
2059 const uint8_t *buf, int oob_required)
2061 int i, eccsize = chip->ecc.size;
2062 int eccbytes = chip->ecc.bytes;
2063 int eccsteps = chip->ecc.steps;
2064 const uint8_t *p = buf;
2065 uint8_t *oob = chip->oob_poi;
2067 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2069 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2070 chip->write_buf(mtd, p, eccsize);
2072 if (chip->ecc.prepad) {
2073 chip->write_buf(mtd, oob, chip->ecc.prepad);
2074 oob += chip->ecc.prepad;
2077 chip->ecc.calculate(mtd, p, oob);
2078 chip->write_buf(mtd, oob, eccbytes);
2081 if (chip->ecc.postpad) {
2082 chip->write_buf(mtd, oob, chip->ecc.postpad);
2083 oob += chip->ecc.postpad;
2087 /* Calculate remaining oob bytes */
2088 i = mtd->oobsize - (oob - chip->oob_poi);
2090 chip->write_buf(mtd, oob, i);
2096 * nand_write_page - [REPLACEABLE] write one page
2097 * @mtd: MTD device structure
2098 * @chip: NAND chip descriptor
2099 * @offset: address offset within the page
2100 * @data_len: length of actual data to be written
2101 * @buf: the data to write
2102 * @oob_required: must write chip->oob_poi to OOB
2103 * @page: page number to write
2104 * @cached: cached programming
2105 * @raw: use _raw version of write_page
2107 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2108 uint32_t offset, int data_len, const uint8_t *buf,
2109 int oob_required, int page, int cached, int raw)
2111 int status, subpage;
2113 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2114 chip->ecc.write_subpage)
2115 subpage = offset || (data_len < mtd->writesize);
2119 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2122 status = chip->ecc.write_page_raw(mtd, chip, buf,
2125 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2128 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2134 * Cached progamming disabled for now. Not sure if it's worth the
2135 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2139 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2141 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2142 status = chip->waitfunc(mtd, chip);
2144 * See if operation failed and additional status checks are
2147 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2148 status = chip->errstat(mtd, chip, FL_WRITING, status,
2151 if (status & NAND_STATUS_FAIL)
2154 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2155 status = chip->waitfunc(mtd, chip);
2162 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2163 * @mtd: MTD device structure
2164 * @oob: oob data buffer
2165 * @len: oob data write length
2166 * @ops: oob ops structure
2168 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2169 struct mtd_oob_ops *ops)
2171 struct nand_chip *chip = mtd->priv;
2174 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2175 * data from a previous OOB read.
2177 memset(chip->oob_poi, 0xff, mtd->oobsize);
2179 switch (ops->mode) {
2181 case MTD_OPS_PLACE_OOB:
2183 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2186 case MTD_OPS_AUTO_OOB: {
2187 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2188 uint32_t boffs = 0, woffs = ops->ooboffs;
2191 for (; free->length && len; free++, len -= bytes) {
2192 /* Write request not from offset 0? */
2193 if (unlikely(woffs)) {
2194 if (woffs >= free->length) {
2195 woffs -= free->length;
2198 boffs = free->offset + woffs;
2199 bytes = min_t(size_t, len,
2200 (free->length - woffs));
2203 bytes = min_t(size_t, len, free->length);
2204 boffs = free->offset;
2206 memcpy(chip->oob_poi + boffs, oob, bytes);
2217 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2220 * nand_do_write_ops - [INTERN] NAND write with ECC
2221 * @mtd: MTD device structure
2222 * @to: offset to write to
2223 * @ops: oob operations description structure
2225 * NAND write with ECC.
2227 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2228 struct mtd_oob_ops *ops)
2230 int chipnr, realpage, page, blockmask, column;
2231 struct nand_chip *chip = mtd->priv;
2232 uint32_t writelen = ops->len;
2234 uint32_t oobwritelen = ops->ooblen;
2235 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2236 mtd->oobavail : mtd->oobsize;
2238 uint8_t *oob = ops->oobbuf;
2239 uint8_t *buf = ops->datbuf;
2241 int oob_required = oob ? 1 : 0;
2247 /* Reject writes, which are not page aligned */
2248 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2249 pr_notice("%s: attempt to write non page aligned data\n",
2254 column = to & (mtd->writesize - 1);
2256 chipnr = (int)(to >> chip->chip_shift);
2257 chip->select_chip(mtd, chipnr);
2259 /* Check, if it is write protected */
2260 if (nand_check_wp(mtd)) {
2265 realpage = (int)(to >> chip->page_shift);
2266 page = realpage & chip->pagemask;
2267 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2269 /* Invalidate the page cache, when we write to the cached page */
2270 if (to <= (chip->pagebuf << chip->page_shift) &&
2271 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2274 /* Don't allow multipage oob writes with offset */
2275 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2281 int bytes = mtd->writesize;
2282 int cached = writelen > bytes && page != blockmask;
2283 uint8_t *wbuf = buf;
2285 /* Partial page write? */
2286 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2288 bytes = min_t(int, bytes - column, (int) writelen);
2290 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2291 memcpy(&chip->buffers->databuf[column], buf, bytes);
2292 wbuf = chip->buffers->databuf;
2295 if (unlikely(oob)) {
2296 size_t len = min(oobwritelen, oobmaxlen);
2297 oob = nand_fill_oob(mtd, oob, len, ops);
2300 /* We still need to erase leftover OOB data */
2301 memset(chip->oob_poi, 0xff, mtd->oobsize);
2303 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2304 oob_required, page, cached,
2305 (ops->mode == MTD_OPS_RAW));
2317 page = realpage & chip->pagemask;
2318 /* Check, if we cross a chip boundary */
2321 chip->select_chip(mtd, -1);
2322 chip->select_chip(mtd, chipnr);
2326 ops->retlen = ops->len - writelen;
2328 ops->oobretlen = ops->ooblen;
2331 chip->select_chip(mtd, -1);
2336 * panic_nand_write - [MTD Interface] NAND write with ECC
2337 * @mtd: MTD device structure
2338 * @to: offset to write to
2339 * @len: number of bytes to write
2340 * @retlen: pointer to variable to store the number of written bytes
2341 * @buf: the data to write
2343 * NAND write with ECC. Used when performing writes in interrupt context, this
2344 * may for example be called by mtdoops when writing an oops while in panic.
2346 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2347 size_t *retlen, const uint8_t *buf)
2349 struct nand_chip *chip = mtd->priv;
2350 struct mtd_oob_ops ops;
2353 /* Wait for the device to get ready */
2354 panic_nand_wait(mtd, chip, 400);
2356 /* Grab the device */
2357 panic_nand_get_device(chip, mtd, FL_WRITING);
2360 ops.datbuf = (uint8_t *)buf;
2362 ops.mode = MTD_OPS_PLACE_OOB;
2364 ret = nand_do_write_ops(mtd, to, &ops);
2366 *retlen = ops.retlen;
2371 * nand_write - [MTD Interface] NAND write with ECC
2372 * @mtd: MTD device structure
2373 * @to: offset to write to
2374 * @len: number of bytes to write
2375 * @retlen: pointer to variable to store the number of written bytes
2376 * @buf: the data to write
2378 * NAND write with ECC.
2380 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2381 size_t *retlen, const uint8_t *buf)
2383 struct mtd_oob_ops ops;
2386 nand_get_device(mtd, FL_WRITING);
2388 ops.datbuf = (uint8_t *)buf;
2390 ops.mode = MTD_OPS_PLACE_OOB;
2391 ret = nand_do_write_ops(mtd, to, &ops);
2392 *retlen = ops.retlen;
2393 nand_release_device(mtd);
2398 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2399 * @mtd: MTD device structure
2400 * @to: offset to write to
2401 * @ops: oob operation description structure
2403 * NAND write out-of-band.
2405 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2406 struct mtd_oob_ops *ops)
2408 int chipnr, page, status, len;
2409 struct nand_chip *chip = mtd->priv;
2411 pr_debug("%s: to = 0x%08x, len = %i\n",
2412 __func__, (unsigned int)to, (int)ops->ooblen);
2414 if (ops->mode == MTD_OPS_AUTO_OOB)
2415 len = chip->ecc.layout->oobavail;
2419 /* Do not allow write past end of page */
2420 if ((ops->ooboffs + ops->ooblen) > len) {
2421 pr_debug("%s: attempt to write past end of page\n",
2426 if (unlikely(ops->ooboffs >= len)) {
2427 pr_debug("%s: attempt to start write outside oob\n",
2432 /* Do not allow write past end of device */
2433 if (unlikely(to >= mtd->size ||
2434 ops->ooboffs + ops->ooblen >
2435 ((mtd->size >> chip->page_shift) -
2436 (to >> chip->page_shift)) * len)) {
2437 pr_debug("%s: attempt to write beyond end of device\n",
2442 chipnr = (int)(to >> chip->chip_shift);
2443 chip->select_chip(mtd, chipnr);
2445 /* Shift to get page */
2446 page = (int)(to >> chip->page_shift);
2449 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2450 * of my DiskOnChip 2000 test units) will clear the whole data page too
2451 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2452 * it in the doc2000 driver in August 1999. dwmw2.
2454 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2456 /* Check, if it is write protected */
2457 if (nand_check_wp(mtd)) {
2458 chip->select_chip(mtd, -1);
2462 /* Invalidate the page cache, if we write to the cached page */
2463 if (page == chip->pagebuf)
2466 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2468 if (ops->mode == MTD_OPS_RAW)
2469 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2471 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2473 chip->select_chip(mtd, -1);
2478 ops->oobretlen = ops->ooblen;
2484 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2485 * @mtd: MTD device structure
2486 * @to: offset to write to
2487 * @ops: oob operation description structure
2489 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2490 struct mtd_oob_ops *ops)
2492 int ret = -ENOTSUPP;
2496 /* Do not allow writes past end of device */
2497 if (ops->datbuf && (to + ops->len) > mtd->size) {
2498 pr_debug("%s: attempt to write beyond end of device\n",
2503 nand_get_device(mtd, FL_WRITING);
2505 switch (ops->mode) {
2506 case MTD_OPS_PLACE_OOB:
2507 case MTD_OPS_AUTO_OOB:
2516 ret = nand_do_write_oob(mtd, to, ops);
2518 ret = nand_do_write_ops(mtd, to, ops);
2521 nand_release_device(mtd);
2526 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2527 * @mtd: MTD device structure
2528 * @page: the page address of the block which will be erased
2530 * Standard erase command for NAND chips.
2532 static void single_erase_cmd(struct mtd_info *mtd, int page)
2534 struct nand_chip *chip = mtd->priv;
2535 /* Send commands to erase a block */
2536 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2537 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2541 * nand_erase - [MTD Interface] erase block(s)
2542 * @mtd: MTD device structure
2543 * @instr: erase instruction
2545 * Erase one ore more blocks.
2547 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2549 return nand_erase_nand(mtd, instr, 0);
2553 * nand_erase_nand - [INTERN] erase block(s)
2554 * @mtd: MTD device structure
2555 * @instr: erase instruction
2556 * @allowbbt: allow erasing the bbt area
2558 * Erase one ore more blocks.
2560 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2563 int page, status, pages_per_block, ret, chipnr;
2564 struct nand_chip *chip = mtd->priv;
2567 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2568 __func__, (unsigned long long)instr->addr,
2569 (unsigned long long)instr->len);
2571 if (check_offs_len(mtd, instr->addr, instr->len))
2574 /* Grab the lock and see if the device is available */
2575 nand_get_device(mtd, FL_ERASING);
2577 /* Shift to get first page */
2578 page = (int)(instr->addr >> chip->page_shift);
2579 chipnr = (int)(instr->addr >> chip->chip_shift);
2581 /* Calculate pages in each block */
2582 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2584 /* Select the NAND device */
2585 chip->select_chip(mtd, chipnr);
2587 /* Check, if it is write protected */
2588 if (nand_check_wp(mtd)) {
2589 pr_debug("%s: device is write protected!\n",
2591 instr->state = MTD_ERASE_FAILED;
2595 /* Loop through the pages */
2598 instr->state = MTD_ERASING;
2601 /* Check if we have a bad block, we do not erase bad blocks! */
2602 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2603 chip->page_shift, 0, allowbbt)) {
2604 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2606 instr->state = MTD_ERASE_FAILED;
2611 * Invalidate the page cache, if we erase the block which
2612 * contains the current cached page.
2614 if (page <= chip->pagebuf && chip->pagebuf <
2615 (page + pages_per_block))
2618 chip->erase_cmd(mtd, page & chip->pagemask);
2620 status = chip->waitfunc(mtd, chip);
2623 * See if operation failed and additional status checks are
2626 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2627 status = chip->errstat(mtd, chip, FL_ERASING,
2630 /* See if block erase succeeded */
2631 if (status & NAND_STATUS_FAIL) {
2632 pr_debug("%s: failed erase, page 0x%08x\n",
2634 instr->state = MTD_ERASE_FAILED;
2636 ((loff_t)page << chip->page_shift);
2640 /* Increment page address and decrement length */
2641 len -= (1 << chip->phys_erase_shift);
2642 page += pages_per_block;
2644 /* Check, if we cross a chip boundary */
2645 if (len && !(page & chip->pagemask)) {
2647 chip->select_chip(mtd, -1);
2648 chip->select_chip(mtd, chipnr);
2651 instr->state = MTD_ERASE_DONE;
2655 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2657 /* Deselect and wake up anyone waiting on the device */
2658 chip->select_chip(mtd, -1);
2659 nand_release_device(mtd);
2661 /* Do call back function */
2663 mtd_erase_callback(instr);
2665 /* Return more or less happy */
2670 * nand_sync - [MTD Interface] sync
2671 * @mtd: MTD device structure
2673 * Sync is actually a wait for chip ready function.
2675 static void nand_sync(struct mtd_info *mtd)
2677 pr_debug("%s: called\n", __func__);
2679 /* Grab the lock and see if the device is available */
2680 nand_get_device(mtd, FL_SYNCING);
2681 /* Release it and go back */
2682 nand_release_device(mtd);
2686 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2687 * @mtd: MTD device structure
2688 * @offs: offset relative to mtd start
2690 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2692 return nand_block_checkbad(mtd, offs, 1, 0);
2696 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2697 * @mtd: MTD device structure
2698 * @ofs: offset relative to mtd start
2700 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2702 struct nand_chip *chip = mtd->priv;
2705 ret = nand_block_isbad(mtd, ofs);
2707 /* If it was bad already, return success and do nothing */
2713 return chip->block_markbad(mtd, ofs);
2717 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2718 * @mtd: MTD device structure
2719 * @chip: nand chip info structure
2720 * @addr: feature address.
2721 * @subfeature_param: the subfeature parameters, a four bytes array.
2723 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2724 int addr, uint8_t *subfeature_param)
2728 if (!chip->onfi_version)
2731 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2732 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2733 status = chip->waitfunc(mtd, chip);
2734 if (status & NAND_STATUS_FAIL)
2740 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2741 * @mtd: MTD device structure
2742 * @chip: nand chip info structure
2743 * @addr: feature address.
2744 * @subfeature_param: the subfeature parameters, a four bytes array.
2746 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2747 int addr, uint8_t *subfeature_param)
2749 if (!chip->onfi_version)
2752 /* clear the sub feature parameters */
2753 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2755 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2756 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2761 * nand_suspend - [MTD Interface] Suspend the NAND flash
2762 * @mtd: MTD device structure
2764 static int nand_suspend(struct mtd_info *mtd)
2766 return nand_get_device(mtd, FL_PM_SUSPENDED);
2770 * nand_resume - [MTD Interface] Resume the NAND flash
2771 * @mtd: MTD device structure
2773 static void nand_resume(struct mtd_info *mtd)
2775 struct nand_chip *chip = mtd->priv;
2777 if (chip->state == FL_PM_SUSPENDED)
2778 nand_release_device(mtd);
2780 pr_err("%s called for a chip which is not in suspended state\n",
2784 /* Set default functions */
2785 static void nand_set_defaults(struct nand_chip *chip, int busw)
2787 /* check for proper chip_delay setup, set 20us if not */
2788 if (!chip->chip_delay)
2789 chip->chip_delay = 20;
2791 /* check, if a user supplied command function given */
2792 if (chip->cmdfunc == NULL)
2793 chip->cmdfunc = nand_command;
2795 /* check, if a user supplied wait function given */
2796 if (chip->waitfunc == NULL)
2797 chip->waitfunc = nand_wait;
2799 if (!chip->select_chip)
2800 chip->select_chip = nand_select_chip;
2801 if (!chip->read_byte)
2802 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2803 if (!chip->read_word)
2804 chip->read_word = nand_read_word;
2805 if (!chip->block_bad)
2806 chip->block_bad = nand_block_bad;
2807 if (!chip->block_markbad)
2808 chip->block_markbad = nand_default_block_markbad;
2809 if (!chip->write_buf)
2810 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2811 if (!chip->read_buf)
2812 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2813 if (!chip->scan_bbt)
2814 chip->scan_bbt = nand_default_bbt;
2816 if (!chip->controller) {
2817 chip->controller = &chip->hwcontrol;
2818 spin_lock_init(&chip->controller->lock);
2819 init_waitqueue_head(&chip->controller->wq);
2824 /* Sanitize ONFI strings so we can safely print them */
2825 static void sanitize_string(uint8_t *s, size_t len)
2829 /* Null terminate */
2832 /* Remove non printable chars */
2833 for (i = 0; i < len - 1; i++) {
2834 if (s[i] < ' ' || s[i] > 127)
2838 /* Remove trailing spaces */
2842 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2847 for (i = 0; i < 8; i++)
2848 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2855 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2857 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2860 struct nand_onfi_params *p = &chip->onfi_params;
2864 #ifdef CONFIG_MTD_NAND_XILINX_PS
2866 unsigned int options;
2870 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2871 if (chip->options & NAND_BUSWIDTH_16) {
2872 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2876 /* Try ONFI for unknown chip or LP */
2877 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2878 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2879 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2882 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2883 for (i = 0; i < 3; i++) {
2884 #ifdef CONFIG_MTD_NAND_XILINX_PS
2886 for(j = 0;j < 256;j++)
2887 buf[j] = chip->read_byte(mtd);
2889 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2891 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2892 le16_to_cpu(p->crc)) {
2893 pr_info("ONFI param page %d valid\n", i);
2902 val = le16_to_cpu(p->revision);
2904 chip->onfi_version = 23;
2905 else if (val & (1 << 4))
2906 chip->onfi_version = 22;
2907 else if (val & (1 << 3))
2908 chip->onfi_version = 21;
2909 else if (val & (1 << 2))
2910 chip->onfi_version = 20;
2911 else if (val & (1 << 1))
2912 chip->onfi_version = 10;
2914 if (!chip->onfi_version) {
2915 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2919 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2920 sanitize_string(p->model, sizeof(p->model));
2922 mtd->name = p->model;
2923 mtd->writesize = le32_to_cpu(p->byte_per_page);
2924 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2925 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2926 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2927 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2929 if (le16_to_cpu(p->features) & 1)
2930 *busw = NAND_BUSWIDTH_16;
2932 #ifdef CONFIG_MTD_NAND_XILINX_PS
2933 /* Read the chip options before clearing the bits */
2934 options = chip->options;
2937 pr_info("ONFI flash detected\n");
2938 #ifdef CONFIG_MTD_NAND_XILINX_PS
2939 /* set the bus width option */
2940 if (options & NAND_BUSWIDTH_16)
2941 chip->options |= NAND_BUSWIDTH_16;
2947 * nand_id_has_period - Check if an ID string has a given wraparound period
2948 * @id_data: the ID string
2949 * @arrlen: the length of the @id_data array
2950 * @period: the period of repitition
2952 * Check if an ID string is repeated within a given sequence of bytes at
2953 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2954 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
2955 * if the repetition has a period of @period; otherwise, returns zero.
2957 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2960 for (i = 0; i < period; i++)
2961 for (j = i + period; j < arrlen; j += period)
2962 if (id_data[i] != id_data[j])
2968 * nand_id_len - Get the length of an ID string returned by CMD_READID
2969 * @id_data: the ID string
2970 * @arrlen: the length of the @id_data array
2972 * Returns the length of the ID string, according to known wraparound/trailing
2973 * zero patterns. If no pattern exists, returns the length of the array.
2975 static int nand_id_len(u8 *id_data, int arrlen)
2977 int last_nonzero, period;
2979 /* Find last non-zero byte */
2980 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2981 if (id_data[last_nonzero])
2985 if (last_nonzero < 0)
2988 /* Calculate wraparound period */
2989 for (period = 1; period < arrlen; period++)
2990 if (nand_id_has_period(id_data, arrlen, period))
2993 /* There's a repeated pattern */
2994 if (period < arrlen)
2997 /* There are trailing zeros */
2998 if (last_nonzero < arrlen - 1)
2999 return last_nonzero + 1;
3001 /* No pattern detected */
3006 * Many new NAND share similar device ID codes, which represent the size of the
3007 * chip. The rest of the parameters must be decoded according to generic or
3008 * manufacturer-specific "extended ID" decoding patterns.
3010 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3011 u8 id_data[8], int *busw)
3014 /* The 3rd id byte holds MLC / multichip data */
3015 chip->cellinfo = id_data[2];
3016 /* The 4th id byte is the important one */
3019 id_len = nand_id_len(id_data, 8);
3022 * Field definitions are in the following datasheets:
3023 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3024 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3025 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3027 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3028 * ID to decide what to do.
3030 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3031 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3032 id_data[5] != 0x00) {
3034 mtd->writesize = 2048 << (extid & 0x03);
3037 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3054 default: /* Other cases are "reserved" (unknown) */
3059 /* Calc blocksize */
3060 mtd->erasesize = (128 * 1024) <<
3061 (((extid >> 1) & 0x04) | (extid & 0x03));
3063 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3064 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3068 mtd->writesize = 2048 << (extid & 0x03);
3071 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3095 /* Calc blocksize */
3096 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3098 mtd->erasesize = (128 * 1024) << tmp;
3099 else if (tmp == 0x03)
3100 mtd->erasesize = 768 * 1024;
3102 mtd->erasesize = (64 * 1024) << tmp;
3106 mtd->writesize = 1024 << (extid & 0x03);
3109 mtd->oobsize = (8 << (extid & 0x01)) *
3110 (mtd->writesize >> 9);
3112 /* Calc blocksize. Blocksize is multiples of 64KiB */
3113 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3115 /* Get buswidth information */
3116 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3121 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3122 * decodes a matching ID table entry and assigns the MTD size parameters for
3125 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3126 struct nand_flash_dev *type, u8 id_data[8],
3129 int maf_id = id_data[0];
3131 mtd->erasesize = type->erasesize;
3132 mtd->writesize = type->pagesize;
3133 mtd->oobsize = mtd->writesize / 32;
3134 *busw = type->options & NAND_BUSWIDTH_16;
3137 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3138 * some Spansion chips have erasesize that conflicts with size
3139 * listed in nand_ids table.
3140 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3142 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3143 && id_data[6] == 0x00 && id_data[7] == 0x00
3144 && mtd->writesize == 512) {
3145 mtd->erasesize = 128 * 1024;
3146 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3151 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3152 * heuristic patterns using various detected parameters (e.g., manufacturer,
3153 * page size, cell-type information).
3155 static void nand_decode_bbm_options(struct mtd_info *mtd,
3156 struct nand_chip *chip, u8 id_data[8])
3158 int maf_id = id_data[0];
3160 /* Set the bad block position */
3161 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3162 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3164 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3167 * Bad block marker is stored in the last page of each block on Samsung
3168 * and Hynix MLC devices; stored in first two pages of each block on
3169 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3170 * AMD/Spansion, and Macronix. All others scan only the first page.
3172 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3173 (maf_id == NAND_MFR_SAMSUNG ||
3174 maf_id == NAND_MFR_HYNIX))
3175 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3176 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3177 (maf_id == NAND_MFR_SAMSUNG ||
3178 maf_id == NAND_MFR_HYNIX ||
3179 maf_id == NAND_MFR_TOSHIBA ||
3180 maf_id == NAND_MFR_AMD ||
3181 maf_id == NAND_MFR_MACRONIX)) ||
3182 (mtd->writesize == 2048 &&
3183 maf_id == NAND_MFR_MICRON))
3184 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3187 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3189 return type->id_len;
3192 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3193 struct nand_flash_dev *type, u8 *id_data, int *busw)
3195 if (!strncmp(type->id, id_data, type->id_len)) {
3196 mtd->writesize = type->pagesize;
3197 mtd->erasesize = type->erasesize;
3198 mtd->oobsize = type->oobsize;
3200 chip->cellinfo = id_data[2];
3201 chip->chipsize = (uint64_t)type->chipsize << 20;
3202 chip->options |= type->options;
3204 *busw = type->options & NAND_BUSWIDTH_16;
3212 * Get the flash and manufacturer id and lookup if the type is supported.
3214 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3215 struct nand_chip *chip,
3217 int *maf_id, int *dev_id,
3218 struct nand_flash_dev *type)
3223 /* Select the device */
3224 chip->select_chip(mtd, 0);
3227 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3230 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3232 /* Send the command for reading device ID */
3233 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3235 /* Read manufacturer and device IDs */
3236 *maf_id = chip->read_byte(mtd);
3237 *dev_id = chip->read_byte(mtd);
3240 * Try again to make sure, as some systems the bus-hold or other
3241 * interface concerns can cause random data which looks like a
3242 * possibly credible NAND flash to appear. If the two results do
3243 * not match, ignore the device completely.
3246 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3248 /* Read entire ID string */
3249 for (i = 0; i < 8; i++)
3250 id_data[i] = chip->read_byte(mtd);
3252 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3253 pr_info("%s: second ID read did not match "
3254 "%02x,%02x against %02x,%02x\n", __func__,
3255 *maf_id, *dev_id, id_data[0], id_data[1]);
3256 return ERR_PTR(-ENODEV);
3260 type = nand_flash_ids;
3262 for (; type->name != NULL; type++) {
3263 if (is_full_id_nand(type)) {
3264 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3266 } else if (*dev_id == type->dev_id) {
3271 chip->onfi_version = 0;
3272 if (!type->name || !type->pagesize) {
3273 /* Check is chip is ONFI compliant */
3274 if (nand_flash_detect_onfi(mtd, chip, &busw))
3279 return ERR_PTR(-ENODEV);
3282 mtd->name = type->name;
3284 chip->chipsize = (uint64_t)type->chipsize << 20;
3286 if (!type->pagesize && chip->init_size) {
3287 /* Set the pagesize, oobsize, erasesize by the driver */
3288 busw = chip->init_size(mtd, chip, id_data);
3289 } else if (!type->pagesize) {
3290 /* Decode parameters from extended ID */
3291 nand_decode_ext_id(mtd, chip, id_data, &busw);
3293 nand_decode_id(mtd, chip, type, id_data, &busw);
3295 /* Get chip options */
3296 chip->options |= type->options;
3299 * Check if chip is not a Samsung device. Do not clear the
3300 * options for chips which do not have an extended id.
3302 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3303 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3306 /* Try to identify manufacturer */
3307 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3308 if (nand_manuf_ids[maf_idx].id == *maf_id)
3312 if (chip->options & NAND_BUSWIDTH_AUTO) {
3313 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3314 chip->options |= busw;
3315 nand_set_defaults(chip, busw);
3316 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3318 * Check, if buswidth is correct. Hardware drivers should set
3321 pr_info("NAND device: Manufacturer ID:"
3322 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3323 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3324 pr_warn("NAND bus width %d instead %d bit\n",
3325 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3327 return ERR_PTR(-EINVAL);
3330 nand_decode_bbm_options(mtd, chip, id_data);
3332 /* Calculate the address shift from the page size */
3333 chip->page_shift = ffs(mtd->writesize) - 1;
3334 /* Convert chipsize to number of pages per chip -1 */
3335 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3337 chip->bbt_erase_shift = chip->phys_erase_shift =
3338 ffs(mtd->erasesize) - 1;
3339 if (chip->chipsize & 0xffffffff)
3340 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3342 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3343 chip->chip_shift += 32 - 1;
3346 chip->badblockbits = 8;
3347 chip->erase_cmd = single_erase_cmd;
3349 /* Do not replace user supplied command function! */
3350 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3351 chip->cmdfunc = nand_command_lp;
3353 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3354 " %dMiB, page size: %d, OOB size: %d\n",
3355 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3356 chip->onfi_version ? chip->onfi_params.model : type->name,
3357 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
3363 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3364 * @mtd: MTD device structure
3365 * @maxchips: number of chips to scan for
3366 * @table: alternative NAND ID table
3368 * This is the first phase of the normal nand_scan() function. It reads the
3369 * flash ID and sets up MTD fields accordingly.
3371 * The mtd->owner field must be set to the module of the caller.
3373 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3374 struct nand_flash_dev *table)
3376 int i, busw, nand_maf_id, nand_dev_id;
3377 struct nand_chip *chip = mtd->priv;
3378 struct nand_flash_dev *type;
3380 /* Get buswidth to select the correct functions */
3381 busw = chip->options & NAND_BUSWIDTH_16;
3382 /* Set the default functions */
3383 nand_set_defaults(chip, busw);
3385 /* Read the flash type */
3386 type = nand_get_flash_type(mtd, chip, busw,
3387 &nand_maf_id, &nand_dev_id, table);
3390 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3391 pr_warn("No NAND device found\n");
3392 chip->select_chip(mtd, -1);
3393 return PTR_ERR(type);
3396 chip->select_chip(mtd, -1);
3398 /* Check for a chip array */
3399 for (i = 1; i < maxchips; i++) {
3400 chip->select_chip(mtd, i);
3401 /* See comment in nand_get_flash_type for reset */
3402 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3403 /* Send the command for reading device ID */
3404 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3405 /* Read manufacturer and device IDs */
3406 if (nand_maf_id != chip->read_byte(mtd) ||
3407 nand_dev_id != chip->read_byte(mtd)) {
3408 chip->select_chip(mtd, -1);
3411 chip->select_chip(mtd, -1);
3414 pr_info("%d NAND chips detected\n", i);
3416 /* Store the number of chips and calc total size for mtd */
3418 mtd->size = i * chip->chipsize;
3422 EXPORT_SYMBOL(nand_scan_ident);
3426 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3427 * @mtd: MTD device structure
3429 * This is the second phase of the normal nand_scan() function. It fills out
3430 * all the uninitialized function pointers with the defaults and scans for a
3431 * bad block table if appropriate.
3433 int nand_scan_tail(struct mtd_info *mtd)
3436 struct nand_chip *chip = mtd->priv;
3438 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3439 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3440 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3442 if (!(chip->options & NAND_OWN_BUFFERS))
3443 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3447 /* Set the internal oob buffer location, just after the page data */
3448 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3451 * If no default placement scheme is given, select an appropriate one.
3453 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3454 switch (mtd->oobsize) {
3456 chip->ecc.layout = &nand_oob_8;
3459 chip->ecc.layout = &nand_oob_16;
3462 chip->ecc.layout = &nand_oob_64;
3465 chip->ecc.layout = &nand_oob_128;
3468 pr_warn("No oob scheme defined for oobsize %d\n",
3474 if (!chip->write_page)
3475 chip->write_page = nand_write_page;
3477 /* set for ONFI nand */
3478 if (!chip->onfi_set_features)
3479 chip->onfi_set_features = nand_onfi_set_features;
3480 if (!chip->onfi_get_features)
3481 chip->onfi_get_features = nand_onfi_get_features;
3484 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3485 * selected and we have 256 byte pagesize fallback to software ECC
3488 switch (chip->ecc.mode) {
3489 case NAND_ECC_HW_OOB_FIRST:
3490 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3491 if (!chip->ecc.calculate || !chip->ecc.correct ||
3493 pr_warn("No ECC functions supplied; "
3494 "hardware ECC not possible\n");
3497 if (!chip->ecc.read_page)
3498 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3501 /* Use standard hwecc read page function? */
3502 if (!chip->ecc.read_page)
3503 chip->ecc.read_page = nand_read_page_hwecc;
3504 if (!chip->ecc.write_page)
3505 chip->ecc.write_page = nand_write_page_hwecc;
3506 if (!chip->ecc.read_page_raw)
3507 chip->ecc.read_page_raw = nand_read_page_raw;
3508 if (!chip->ecc.write_page_raw)
3509 chip->ecc.write_page_raw = nand_write_page_raw;
3510 if (!chip->ecc.read_oob)
3511 chip->ecc.read_oob = nand_read_oob_std;
3512 if (!chip->ecc.write_oob)
3513 chip->ecc.write_oob = nand_write_oob_std;
3514 if (!chip->ecc.read_subpage)
3515 chip->ecc.read_subpage = nand_read_subpage;
3516 if (!chip->ecc.write_subpage)
3517 chip->ecc.write_subpage = nand_write_subpage_hwecc;
3519 case NAND_ECC_HW_SYNDROME:
3520 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3521 !chip->ecc.hwctl) &&
3522 (!chip->ecc.read_page ||
3523 chip->ecc.read_page == nand_read_page_hwecc ||
3524 !chip->ecc.write_page ||
3525 chip->ecc.write_page == nand_write_page_hwecc)) {
3526 pr_warn("No ECC functions supplied; "
3527 "hardware ECC not possible\n");
3530 /* Use standard syndrome read/write page function? */
3531 if (!chip->ecc.read_page)
3532 chip->ecc.read_page = nand_read_page_syndrome;
3533 if (!chip->ecc.write_page)
3534 chip->ecc.write_page = nand_write_page_syndrome;
3535 if (!chip->ecc.read_page_raw)
3536 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3537 if (!chip->ecc.write_page_raw)
3538 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3539 if (!chip->ecc.read_oob)
3540 chip->ecc.read_oob = nand_read_oob_syndrome;
3541 if (!chip->ecc.write_oob)
3542 chip->ecc.write_oob = nand_write_oob_syndrome;
3544 if (mtd->writesize >= chip->ecc.size) {
3545 if (!chip->ecc.strength) {
3546 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3551 pr_warn("%d byte HW ECC not possible on "
3552 "%d byte page size, fallback to SW ECC\n",
3553 chip->ecc.size, mtd->writesize);
3554 chip->ecc.mode = NAND_ECC_SOFT;
3557 chip->ecc.calculate = nand_calculate_ecc;
3558 chip->ecc.correct = nand_correct_data;
3559 chip->ecc.read_page = nand_read_page_swecc;
3560 chip->ecc.read_subpage = nand_read_subpage;
3561 chip->ecc.write_page = nand_write_page_swecc;
3562 chip->ecc.read_page_raw = nand_read_page_raw;
3563 chip->ecc.write_page_raw = nand_write_page_raw;
3564 chip->ecc.read_oob = nand_read_oob_std;
3565 chip->ecc.write_oob = nand_write_oob_std;
3566 if (!chip->ecc.size)
3567 chip->ecc.size = 256;
3568 chip->ecc.bytes = 3;
3569 chip->ecc.strength = 1;
3572 case NAND_ECC_SOFT_BCH:
3573 if (!mtd_nand_has_bch()) {
3574 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3577 chip->ecc.calculate = nand_bch_calculate_ecc;
3578 chip->ecc.correct = nand_bch_correct_data;
3579 chip->ecc.read_page = nand_read_page_swecc;
3580 chip->ecc.read_subpage = nand_read_subpage;
3581 chip->ecc.write_page = nand_write_page_swecc;
3582 chip->ecc.read_page_raw = nand_read_page_raw;
3583 chip->ecc.write_page_raw = nand_write_page_raw;
3584 chip->ecc.read_oob = nand_read_oob_std;
3585 chip->ecc.write_oob = nand_write_oob_std;
3587 * Board driver should supply ecc.size and ecc.bytes values to
3588 * select how many bits are correctable; see nand_bch_init()
3589 * for details. Otherwise, default to 4 bits for large page
3592 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3593 chip->ecc.size = 512;
3594 chip->ecc.bytes = 7;
3596 chip->ecc.priv = nand_bch_init(mtd,
3600 if (!chip->ecc.priv) {
3601 pr_warn("BCH ECC initialization failed!\n");
3604 chip->ecc.strength =
3605 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3609 pr_warn("NAND_ECC_NONE selected by board driver. "
3610 "This is not recommended!\n");
3611 chip->ecc.read_page = nand_read_page_raw;
3612 chip->ecc.write_page = nand_write_page_raw;
3613 chip->ecc.read_oob = nand_read_oob_std;
3614 chip->ecc.read_page_raw = nand_read_page_raw;
3615 chip->ecc.write_page_raw = nand_write_page_raw;
3616 chip->ecc.write_oob = nand_write_oob_std;
3617 chip->ecc.size = mtd->writesize;
3618 chip->ecc.bytes = 0;
3619 chip->ecc.strength = 0;
3623 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3627 /* For many systems, the standard OOB write also works for raw */
3628 if (!chip->ecc.read_oob_raw)
3629 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3630 if (!chip->ecc.write_oob_raw)
3631 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3634 * The number of bytes available for a client to place data into
3635 * the out of band area.
3637 chip->ecc.layout->oobavail = 0;
3638 for (i = 0; chip->ecc.layout->oobfree[i].length
3639 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3640 chip->ecc.layout->oobavail +=
3641 chip->ecc.layout->oobfree[i].length;
3642 mtd->oobavail = chip->ecc.layout->oobavail;
3645 * Set the number of read / write steps for one page depending on ECC
3648 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3649 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3650 pr_warn("Invalid ECC parameters\n");
3653 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3655 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3656 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3657 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3658 switch (chip->ecc.steps) {
3660 mtd->subpage_sft = 1;
3665 mtd->subpage_sft = 2;
3669 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3671 /* Initialize state */
3672 chip->state = FL_READY;
3674 /* Invalidate the pagebuffer reference */
3677 /* Large page NAND with SOFT_ECC should support subpage reads */
3678 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3679 chip->options |= NAND_SUBPAGE_READ;
3681 /* Fill in remaining MTD driver data */
3682 mtd->type = MTD_NANDFLASH;
3683 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3685 mtd->_erase = nand_erase;
3687 mtd->_unpoint = NULL;
3688 mtd->_read = nand_read;
3689 mtd->_write = nand_write;
3690 mtd->_panic_write = panic_nand_write;
3691 mtd->_read_oob = nand_read_oob;
3692 mtd->_write_oob = nand_write_oob;
3693 mtd->_sync = nand_sync;
3695 mtd->_unlock = NULL;
3696 mtd->_suspend = nand_suspend;
3697 mtd->_resume = nand_resume;
3698 mtd->_block_isbad = nand_block_isbad;
3699 mtd->_block_markbad = nand_block_markbad;
3700 mtd->writebufsize = mtd->writesize;
3702 /* propagate ecc info to mtd_info */
3703 mtd->ecclayout = chip->ecc.layout;
3704 mtd->ecc_strength = chip->ecc.strength;
3706 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3707 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3710 if (!mtd->bitflip_threshold)
3711 mtd->bitflip_threshold = mtd->ecc_strength;
3713 /* Check, if we should skip the bad block table scan */
3714 if (chip->options & NAND_SKIP_BBTSCAN)
3717 /* Build bad block table */
3718 return chip->scan_bbt(mtd);
3720 EXPORT_SYMBOL(nand_scan_tail);
3723 * is_module_text_address() isn't exported, and it's mostly a pointless
3724 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3725 * to call us from in-kernel code if the core NAND support is modular.
3728 #define caller_is_module() (1)
3730 #define caller_is_module() \
3731 is_module_text_address((unsigned long)__builtin_return_address(0))
3735 * nand_scan - [NAND Interface] Scan for the NAND device
3736 * @mtd: MTD device structure
3737 * @maxchips: number of chips to scan for
3739 * This fills out all the uninitialized function pointers with the defaults.
3740 * The flash ID is read and the mtd/chip structures are filled with the
3741 * appropriate values. The mtd->owner field must be set to the module of the
3744 int nand_scan(struct mtd_info *mtd, int maxchips)
3748 /* Many callers got this wrong, so check for it for a while... */
3749 if (!mtd->owner && caller_is_module()) {
3750 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3754 ret = nand_scan_ident(mtd, maxchips, NULL);
3756 ret = nand_scan_tail(mtd);
3759 EXPORT_SYMBOL(nand_scan);
3762 * nand_release - [NAND Interface] Free resources held by the NAND device
3763 * @mtd: MTD device structure
3765 void nand_release(struct mtd_info *mtd)
3767 struct nand_chip *chip = mtd->priv;
3769 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3770 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3772 mtd_device_unregister(mtd);
3774 /* Free bad block table memory */
3776 if (!(chip->options & NAND_OWN_BUFFERS))
3777 kfree(chip->buffers);
3779 /* Free bad block descriptor memory */
3780 if (chip->badblock_pattern && chip->badblock_pattern->options
3781 & NAND_BBT_DYNAMICSTRUCT)
3782 kfree(chip->badblock_pattern);
3784 EXPORT_SYMBOL_GPL(nand_release);
3786 static int __init nand_base_init(void)
3788 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3792 static void __exit nand_base_exit(void)
3794 led_trigger_unregister_simple(nand_led_trigger);
3797 module_init(nand_base_init);
3798 module_exit(nand_base_exit);
3800 MODULE_LICENSE("GPL");
3801 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3802 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3803 MODULE_DESCRIPTION("Generic NAND flash driver code");