2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_pci.h>
33 #include <linux/export.h>
35 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
40 static DEFINE_SPINLOCK(hose_spinlock);
43 /* XXX kill that some day ... */
44 static int global_phb_number; /* Global phb counter */
46 /* ISA Memory physical address */
47 resource_size_t isa_mem_base;
49 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
51 unsigned long isa_io_base;
52 unsigned long pci_dram_offset;
53 static int pci_bus_count;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
83 void pcibios_free_controller(struct pci_controller *phb)
85 spin_lock(&hose_spinlock);
86 list_del(&phb->list_node);
87 spin_unlock(&hose_spinlock);
93 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
95 return resource_size(&hose->io_resource);
98 int pcibios_vaddr_is_ioport(void __iomem *address)
101 struct pci_controller *hose;
102 resource_size_t size;
104 spin_lock(&hose_spinlock);
105 list_for_each_entry(hose, &hose_list, list_node) {
106 size = pcibios_io_size(hose);
107 if (address >= hose->io_base_virt &&
108 address < (hose->io_base_virt + size)) {
113 spin_unlock(&hose_spinlock);
117 unsigned long pci_address_to_pio(phys_addr_t address)
119 struct pci_controller *hose;
120 resource_size_t size;
121 unsigned long ret = ~0;
123 spin_lock(&hose_spinlock);
124 list_for_each_entry(hose, &hose_list, list_node) {
125 size = pcibios_io_size(hose);
126 if (address >= hose->io_base_phys &&
127 address < (hose->io_base_phys + size)) {
129 (unsigned long)hose->io_base_virt - _IO_BASE;
130 ret = base + (address - hose->io_base_phys);
134 spin_unlock(&hose_spinlock);
138 EXPORT_SYMBOL_GPL(pci_address_to_pio);
141 * Return the domain number for this bus.
143 int pci_domain_nr(struct pci_bus *bus)
145 struct pci_controller *hose = pci_bus_to_host(bus);
147 return hose->global_number;
149 EXPORT_SYMBOL(pci_domain_nr);
151 /* This routine is meant to be used early during boot, when the
152 * PCI bus numbers have not yet been assigned, and you need to
153 * issue PCI config cycles to an OF device.
154 * It could also be used to "fix" RTAS config cycles if you want
155 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
158 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
161 struct pci_controller *hose, *tmp;
162 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
163 if (hose->dn == node)
170 static ssize_t pci_show_devspec(struct device *dev,
171 struct device_attribute *attr, char *buf)
173 struct pci_dev *pdev;
174 struct device_node *np;
176 pdev = to_pci_dev(dev);
177 np = pci_device_to_OF_node(pdev);
178 if (np == NULL || np->full_name == NULL)
180 return sprintf(buf, "%s", np->full_name);
182 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
184 /* Add sysfs properties */
185 int pcibios_add_platform_entries(struct pci_dev *pdev)
187 return device_create_file(&pdev->dev, &dev_attr_devspec);
190 #ifndef CONFIG_XILINX_AXIPCIE
191 void pcibios_set_master(struct pci_dev *dev)
193 /* No special bus mastering setup handling */
198 * Reads the interrupt pin to determine if interrupt is use by card.
199 * If the interrupt is used, then gets the interrupt line from the
200 * openfirmware and sets it in the pci_dev and pci_config line.
202 int pci_read_irq_line(struct pci_dev *pci_dev)
207 /* The current device-tree that iSeries generates from the HV
208 * PCI informations doesn't contain proper interrupt routing,
209 * and all the fallback would do is print out crap, so we
210 * don't attempt to resolve the interrupts here at all, some
211 * iSeries specific fixup does it.
213 * In the long run, we will hopefully fix the generated device-tree
216 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
219 memset(&oirq, 0xff, sizeof(oirq));
221 /* Try to get a mapping from the device-tree */
222 if (of_irq_map_pci(pci_dev, &oirq)) {
225 /* If that fails, lets fallback to what is in the config
226 * space and map that through the default controller. We
227 * also set the type to level low since that's what PCI
228 * interrupts are. If your platform does differently, then
229 * either provide a proper interrupt tree or don't use this
232 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
236 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
237 line == 0xff || line == 0) {
240 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
243 virq = irq_create_mapping(NULL, line);
245 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
247 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
248 oirq.size, oirq.specifier[0], oirq.specifier[1],
249 of_node_full_name(oirq.controller));
251 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
255 pr_debug(" Failed to map !\n");
259 pr_debug(" Mapped to linux irq %d\n", virq);
265 EXPORT_SYMBOL(pci_read_irq_line);
268 * Platform support for /proc/bus/pci/X/Y mmap()s,
269 * modelled on the sparc64 implementation by Dave Miller.
274 * Adjust vm_pgoff of VMA such that it is the physical page offset
275 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
277 * Basically, the user finds the base address for his device which he wishes
278 * to mmap. They read the 32-bit value from the config space base register,
279 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
280 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
282 * Returns negative error code on failure, zero on success.
284 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
285 resource_size_t *offset,
286 enum pci_mmap_state mmap_state)
288 struct pci_controller *hose = pci_bus_to_host(dev->bus);
289 unsigned long io_offset = 0;
293 return NULL; /* should never happen */
295 /* If memory, add on the PCI bridge address offset */
296 if (mmap_state == pci_mmap_mem) {
297 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
298 *offset += hose->pci_mem_offset;
300 res_bit = IORESOURCE_MEM;
302 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
303 *offset += io_offset;
304 res_bit = IORESOURCE_IO;
308 * Check that the offset requested corresponds to one of the
309 * resources of the device.
311 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
312 struct resource *rp = &dev->resource[i];
313 int flags = rp->flags;
315 /* treat ROM as memory (should be already) */
316 if (i == PCI_ROM_RESOURCE)
317 flags |= IORESOURCE_MEM;
319 /* Active and same type? */
320 if ((flags & res_bit) == 0)
323 /* In the range of this resource? */
324 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
327 /* found it! construct the final physical address */
328 if (mmap_state == pci_mmap_io)
329 *offset += hose->io_base_phys - io_offset;
337 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
340 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
342 enum pci_mmap_state mmap_state,
345 pgprot_t prot = protection;
347 /* Write combine is always 0 on non-memory space mappings. On
348 * memory space, if the user didn't pass 1, we check for a
349 * "prefetchable" resource. This is a bit hackish, but we use
350 * this to workaround the inability of /sysfs to provide a write
353 if (mmap_state != pci_mmap_mem)
355 else if (write_combine == 0) {
356 if (rp->flags & IORESOURCE_PREFETCH)
360 return pgprot_noncached(prot);
364 * This one is used by /dev/mem and fbdev who have no clue about the
365 * PCI device, it tries to find the PCI device first and calls the
368 pgprot_t pci_phys_mem_access_prot(struct file *file,
373 struct pci_dev *pdev = NULL;
374 struct resource *found = NULL;
375 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
378 if (page_is_ram(pfn))
381 prot = pgprot_noncached(prot);
382 for_each_pci_dev(pdev) {
383 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
384 struct resource *rp = &pdev->resource[i];
385 int flags = rp->flags;
387 /* Active and same type? */
388 if ((flags & IORESOURCE_MEM) == 0)
390 /* In the range of this resource? */
391 if (offset < (rp->start & PAGE_MASK) ||
401 if (found->flags & IORESOURCE_PREFETCH)
402 prot = pgprot_noncached_wc(prot);
406 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
407 (unsigned long long)offset, pgprot_val(prot));
413 * Perform the actual remap of the pages for a PCI device mapping, as
414 * appropriate for this architecture. The region in the process to map
415 * is described by vm_start and vm_end members of VMA, the base physical
416 * address is found in vm_pgoff.
417 * The pci device structure is provided so that architectures may make mapping
418 * decisions on a per-device or per-bus basis.
420 * Returns a negative error code on failure, zero on success.
422 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
423 enum pci_mmap_state mmap_state, int write_combine)
425 resource_size_t offset =
426 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
430 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
434 vma->vm_pgoff = offset >> PAGE_SHIFT;
435 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
437 mmap_state, write_combine);
439 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
440 vma->vm_end - vma->vm_start, vma->vm_page_prot);
445 /* This provides legacy IO read access on a bus */
446 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
448 unsigned long offset;
449 struct pci_controller *hose = pci_bus_to_host(bus);
450 struct resource *rp = &hose->io_resource;
453 /* Check if port can be supported by that bus. We only check
454 * the ranges of the PHB though, not the bus itself as the rules
455 * for forwarding legacy cycles down bridges are not our problem
456 * here. So if the host bridge supports it, we do it.
458 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
461 if (!(rp->flags & IORESOURCE_IO))
463 if (offset < rp->start || (offset + size) > rp->end)
465 addr = hose->io_base_virt + port;
469 *((u8 *)val) = in_8(addr);
474 *((u16 *)val) = in_le16(addr);
479 *((u32 *)val) = in_le32(addr);
485 /* This provides legacy IO write access on a bus */
486 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
488 unsigned long offset;
489 struct pci_controller *hose = pci_bus_to_host(bus);
490 struct resource *rp = &hose->io_resource;
493 /* Check if port can be supported by that bus. We only check
494 * the ranges of the PHB though, not the bus itself as the rules
495 * for forwarding legacy cycles down bridges are not our problem
496 * here. So if the host bridge supports it, we do it.
498 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
501 if (!(rp->flags & IORESOURCE_IO))
503 if (offset < rp->start || (offset + size) > rp->end)
505 addr = hose->io_base_virt + port;
507 /* WARNING: The generic code is idiotic. It gets passed a pointer
508 * to what can be a 1, 2 or 4 byte quantity and always reads that
509 * as a u32, which means that we have to correct the location of
510 * the data read within those 32 bits for size 1 and 2
514 out_8(addr, val >> 24);
519 out_le16(addr, val >> 16);
530 /* This provides legacy IO or memory mmap access on a bus */
531 int pci_mmap_legacy_page_range(struct pci_bus *bus,
532 struct vm_area_struct *vma,
533 enum pci_mmap_state mmap_state)
535 struct pci_controller *hose = pci_bus_to_host(bus);
536 resource_size_t offset =
537 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
538 resource_size_t size = vma->vm_end - vma->vm_start;
541 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
542 pci_domain_nr(bus), bus->number,
543 mmap_state == pci_mmap_mem ? "MEM" : "IO",
544 (unsigned long long)offset,
545 (unsigned long long)(offset + size - 1));
547 if (mmap_state == pci_mmap_mem) {
550 * Because X is lame and can fail starting if it gets an error
551 * trying to mmap legacy_mem (instead of just moving on without
552 * legacy memory access) we fake it here by giving it anonymous
553 * memory, effectively behaving just like /dev/zero
555 if ((offset + size) > hose->isa_mem_size) {
557 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
558 current->comm, current->pid);
559 pr_debug("legacy memory for 0%04x:%02x\n",
560 pci_domain_nr(bus), bus->number);
562 if (vma->vm_flags & VM_SHARED)
563 return shmem_zero_setup(vma);
566 offset += hose->isa_mem_phys;
568 unsigned long io_offset = (unsigned long)hose->io_base_virt -
570 unsigned long roffset = offset + io_offset;
571 rp = &hose->io_resource;
572 if (!(rp->flags & IORESOURCE_IO))
574 if (roffset < rp->start || (roffset + size) > rp->end)
576 offset += hose->io_base_phys;
578 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
580 vma->vm_pgoff = offset >> PAGE_SHIFT;
581 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
582 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
583 vma->vm_end - vma->vm_start,
587 void pci_resource_to_user(const struct pci_dev *dev, int bar,
588 const struct resource *rsrc,
589 resource_size_t *start, resource_size_t *end)
591 struct pci_controller *hose = pci_bus_to_host(dev->bus);
592 resource_size_t offset = 0;
597 if (rsrc->flags & IORESOURCE_IO)
598 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
600 /* We pass a fully fixed up address to userland for MMIO instead of
601 * a BAR value because X is lame and expects to be able to use that
602 * to pass to /dev/mem !
604 * That means that we'll have potentially 64 bits values where some
605 * userland apps only expect 32 (like X itself since it thinks only
606 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
609 * Hopefully, the sysfs insterface is immune to that gunk. Once X
610 * has been fixed (and the fix spread enough), we can re-enable the
611 * 2 lines below and pass down a BAR value to userland. In that case
612 * we'll also have to re-enable the matching code in
613 * __pci_mmap_make_offset().
618 else if (rsrc->flags & IORESOURCE_MEM)
619 offset = hose->pci_mem_offset;
622 *start = rsrc->start - offset;
623 *end = rsrc->end - offset;
627 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
628 * @hose: newly allocated pci_controller to be setup
629 * @dev: device node of the host bridge
630 * @primary: set if primary bus (32 bits only, soon to be deprecated)
632 * This function will parse the "ranges" property of a PCI host bridge device
633 * node and setup the resource mapping of a pci controller based on its
636 * Life would be boring if it wasn't for a few issues that we have to deal
639 * - We can only cope with one IO space range and up to 3 Memory space
640 * ranges. However, some machines (thanks Apple !) tend to split their
641 * space into lots of small contiguous ranges. So we have to coalesce.
643 * - We can only cope with all memory ranges having the same offset
644 * between CPU addresses and PCI addresses. Unfortunately, some bridges
645 * are setup for a large 1:1 mapping along with a small "window" which
646 * maps PCI address 0 to some arbitrary high address of the CPU space in
647 * order to give access to the ISA memory hole.
648 * The way out of here that I've chosen for now is to always set the
649 * offset based on the first resource found, then override it if we
650 * have a different offset and the previous was set by an ISA hole.
652 * - Some busses have IO space not starting at 0, which causes trouble with
653 * the way we do our IO resource renumbering. The code somewhat deals with
654 * it for 64 bits but I would expect problems on 32 bits.
656 * - Some 32 bits platforms such as 4xx can have physical space larger than
657 * 32 bits so we need to use 64 bits values for the parsing
659 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
660 struct device_node *dev, int primary)
664 /* The address cells of PCIe parent node */
665 int pna = of_n_addr_cells(dev);
667 int memno = 0, isa_hole = -1;
669 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
670 unsigned long long isa_mb = 0;
671 struct resource *res;
673 pr_info("PCI host bridge %s %s ranges:\n",
674 dev->full_name, primary ? "(primary)" : "");
676 /* Get ranges property */
677 ranges = of_get_property(dev, "ranges", &rlen);
682 pr_debug("Parsing ranges property...\n");
683 while ((rlen -= np * 4) >= 0) {
684 /* Read next ranges element */
685 pci_space = be32_to_cpup(ranges);
686 pci_addr = of_read_number(ranges + 1, 2);
687 cpu_addr = of_translate_address(dev, ranges + 3);
688 size = of_read_number(ranges + pna + 3, 2);
690 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
691 pci_space, pci_addr);
692 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
697 /* If we failed translation or got a zero-sized region
698 * (some FW try to feed us with non sensical zero sized regions
699 * such as power3 which look like some kind of attempt
700 * at exposing the VGA memory hole)
702 if (cpu_addr == OF_BAD_ADDR || size == 0)
705 /* Now consume following elements while they are contiguous */
706 for (; rlen >= np * sizeof(u32);
707 ranges += np, rlen -= np * 4) {
708 if (be32_to_cpup(ranges) != pci_space)
710 pci_next = of_read_number(ranges + 1, 2);
711 cpu_next = of_translate_address(dev, ranges + 3);
712 if (pci_next != pci_addr + size ||
713 cpu_next != cpu_addr + size)
715 size += of_read_number(ranges + pna + 3, 2);
718 /* Act based on address space type */
720 switch ((pci_space >> 24) & 0x3) {
721 case 1: /* PCI IO space */
722 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
723 cpu_addr, cpu_addr + size - 1, pci_addr);
725 /* We support only one IO range */
726 if (hose->pci_io_size) {
727 pr_info(" \\--> Skipped (too many) !\n");
730 /* On 32 bits, limit I/O space to 16MB */
731 if (size > 0x01000000)
734 /* 32 bits needs to map IOs here */
735 hose->io_base_virt = ioremap(cpu_addr, size);
737 /* Expect trouble if pci_addr is not 0 */
740 (unsigned long)hose->io_base_virt;
741 /* pci_io_size and io_base_phys always represent IO
742 * space starting at 0 so we factor in pci_addr
744 hose->pci_io_size = pci_addr + size;
745 hose->io_base_phys = cpu_addr - pci_addr;
748 res = &hose->io_resource;
749 res->flags = IORESOURCE_IO;
750 res->start = pci_addr;
752 case 2: /* PCI Memory space */
753 case 3: /* PCI 64 bits Memory space */
754 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
755 cpu_addr, cpu_addr + size - 1, pci_addr,
756 (pci_space & 0x40000000) ? "Prefetch" : "");
758 /* We support only 3 memory ranges */
760 pr_info(" \\--> Skipped (too many) !\n");
763 /* Handles ISA memory hole space here */
767 if (primary || isa_mem_base == 0)
768 isa_mem_base = cpu_addr;
769 hose->isa_mem_phys = cpu_addr;
770 hose->isa_mem_size = size;
773 /* We get the PCI/Mem offset from the first range or
774 * the, current one if the offset came from an ISA
775 * hole. If they don't match, bugger.
778 (isa_hole >= 0 && pci_addr != 0 &&
779 hose->pci_mem_offset == isa_mb))
780 hose->pci_mem_offset = cpu_addr - pci_addr;
781 else if (pci_addr != 0 &&
782 hose->pci_mem_offset != cpu_addr - pci_addr) {
783 pr_info(" \\--> Skipped (offset mismatch) !\n");
788 res = &hose->mem_resources[memno++];
789 res->flags = IORESOURCE_MEM;
790 if (pci_space & 0x40000000)
791 res->flags |= IORESOURCE_PREFETCH;
792 res->start = cpu_addr;
796 res->name = dev->full_name;
797 res->end = res->start + size - 1;
804 /* If there's an ISA hole and the pci_mem_offset is -not- matching
805 * the ISA hole offset, then we need to remove the ISA hole from
806 * the resource list for that brige
808 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
809 unsigned int next = isa_hole + 1;
810 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
812 memmove(&hose->mem_resources[isa_hole],
813 &hose->mem_resources[next],
814 sizeof(struct resource) * (memno - next));
815 hose->mem_resources[--memno].flags = 0;
819 /* Decide whether to display the domain number in /proc */
820 int pci_proc_domain(struct pci_bus *bus)
825 /* This header fixup will do the resource fixup for all devices as they are
826 * probed, but not for bridge ranges
828 static void pcibios_fixup_resources(struct pci_dev *dev)
830 struct pci_controller *hose = pci_bus_to_host(dev->bus);
834 pr_err("No host bridge for PCI dev %s !\n",
838 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
839 struct resource *res = dev->resource + i;
842 if (res->start == 0) {
843 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
845 (unsigned long long)res->start,
846 (unsigned long long)res->end,
847 (unsigned int)res->flags);
848 pr_debug("is unassigned\n");
849 res->end -= res->start;
851 res->flags |= IORESOURCE_UNSET;
855 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
857 (unsigned long long)res->start,
858 (unsigned long long)res->end,
859 (unsigned int)res->flags);
862 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
864 /* This function tries to figure out if a bridge resource has been initialized
865 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
866 * things go more smoothly when it gets it right. It should covers cases such
867 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
869 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
870 struct resource *res)
872 struct pci_controller *hose = pci_bus_to_host(bus);
873 struct pci_dev *dev = bus->self;
874 resource_size_t offset;
878 /* Job is a bit different between memory and IO */
879 if (res->flags & IORESOURCE_MEM) {
880 /* If the BAR is non-0 (res != pci_mem_offset) then it's
881 * probably been initialized by somebody
883 if (res->start != hose->pci_mem_offset)
886 /* The BAR is 0, let's check if memory decoding is enabled on
887 * the bridge. If not, we consider it unassigned
889 pci_read_config_word(dev, PCI_COMMAND, &command);
890 if ((command & PCI_COMMAND_MEMORY) == 0)
893 /* Memory decoding is enabled and the BAR is 0. If any of
894 * the bridge resources covers that starting address (0 then
895 * it's good enough for us for memory
897 for (i = 0; i < 3; i++) {
898 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
899 hose->mem_resources[i].start == hose->pci_mem_offset)
903 /* Well, it starts at 0 and we know it will collide so we may as
904 * well consider it as unassigned. That covers the Apple case.
908 /* If the BAR is non-0, then we consider it assigned */
909 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
910 if (((res->start - offset) & 0xfffffffful) != 0)
913 /* Here, we are a bit different than memory as typically IO
914 * space starting at low addresses -is- valid. What we do
915 * instead if that we consider as unassigned anything that
916 * doesn't have IO enabled in the PCI command register,
919 pci_read_config_word(dev, PCI_COMMAND, &command);
920 if (command & PCI_COMMAND_IO)
923 /* It's starting at 0 and IO is disabled in the bridge, consider
930 /* Fixup resources of a PCI<->PCI bridge */
931 static void pcibios_fixup_bridge(struct pci_bus *bus)
933 struct resource *res;
936 struct pci_dev *dev = bus->self;
938 pci_bus_for_each_resource(bus, res, i) {
943 if (i >= 3 && bus->self->transparent)
946 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
948 (unsigned long long)res->start,
949 (unsigned long long)res->end,
950 (unsigned int)res->flags);
952 /* Try to detect uninitialized P2P bridge resources,
953 * and clear them out so they get re-assigned later
955 if (pcibios_uninitialized_bridge_resource(bus, res)) {
957 pr_debug("PCI:%s (unassigned)\n",
960 pr_debug("PCI:%s %016llx-%016llx\n",
962 (unsigned long long)res->start,
963 (unsigned long long)res->end);
968 void pcibios_setup_bus_self(struct pci_bus *bus)
970 /* Fix up the bus resources for P2P bridges */
971 if (bus->self != NULL)
972 pcibios_fixup_bridge(bus);
975 void pcibios_setup_bus_devices(struct pci_bus *bus)
979 pr_debug("PCI: Fixup bus devices %d (%s)\n",
980 bus->number, bus->self ? pci_name(bus->self) : "PHB");
982 list_for_each_entry(dev, &bus->devices, bus_list) {
983 /* Setup OF node pointer in archdata */
984 #ifdef CONFIG_XILINX_AXIPCIE
985 /* Get the root complex node */
986 dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
988 dev->dev.of_node = pci_device_to_OF_node(dev);
991 /* Fixup NUMA node as it may not be setup yet by the generic
992 * code and is needed by the DMA init
994 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
996 /* Hook up default DMA ops */
997 set_dma_ops(&dev->dev, pci_dma_ops);
998 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
1000 /* Read default IRQs and fixup if necessary */
1001 pci_read_irq_line(dev);
1005 void pcibios_fixup_bus(struct pci_bus *bus)
1007 /* When called from the generic PCI probe, read PCI<->PCI bridge
1008 * bases. This is -not- called when generating the PCI tree from
1009 * the OF device-tree.
1011 if (bus->self != NULL)
1012 pci_read_bridge_bases(bus);
1014 /* Now fixup the bus bus */
1015 pcibios_setup_bus_self(bus);
1017 /* Now fixup devices on that bus */
1018 pcibios_setup_bus_devices(bus);
1020 EXPORT_SYMBOL(pcibios_fixup_bus);
1022 static int skip_isa_ioresource_align(struct pci_dev *dev)
1028 * We need to avoid collisions with `mirrored' VGA ports
1029 * and other strange ISA hardware, so we always want the
1030 * addresses to be allocated in the 0x000-0x0ff region
1033 * Why? Because some silly external IO cards only decode
1034 * the low 10 bits of the IO address. The 0x00-0xff region
1035 * is reserved for motherboard devices that decode all 16
1036 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1037 * but we want to try to avoid allocating at 0x2900-0x2bff
1038 * which might have be mirrored at 0x0100-0x03ff..
1040 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1041 resource_size_t size, resource_size_t align)
1043 struct pci_dev *dev = data;
1044 resource_size_t start = res->start;
1046 if (res->flags & IORESOURCE_IO) {
1047 if (skip_isa_ioresource_align(dev))
1050 start = (start + 0x3ff) & ~0x3ff;
1055 EXPORT_SYMBOL(pcibios_align_resource);
1058 * Reparent resource children of pr that conflict with res
1059 * under res, and make res replace those children.
1061 static int reparent_resources(struct resource *parent,
1062 struct resource *res)
1064 struct resource *p, **pp;
1065 struct resource **firstpp = NULL;
1067 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1068 if (p->end < res->start)
1070 if (res->end < p->start)
1072 if (p->start < res->start || p->end > res->end)
1073 return -1; /* not completely contained */
1074 if (firstpp == NULL)
1077 if (firstpp == NULL)
1078 return -1; /* didn't find any conflicting entries? */
1079 res->parent = parent;
1080 res->child = *firstpp;
1084 for (p = res->child; p != NULL; p = p->sibling) {
1086 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1088 (unsigned long long)p->start,
1089 (unsigned long long)p->end, res->name);
1095 * Handle resources of PCI devices. If the world were perfect, we could
1096 * just allocate all the resource regions and do nothing more. It isn't.
1097 * On the other hand, we cannot just re-allocate all devices, as it would
1098 * require us to know lots of host bridge internals. So we attempt to
1099 * keep as much of the original configuration as possible, but tweak it
1100 * when it's found to be wrong.
1102 * Known BIOS problems we have to work around:
1103 * - I/O or memory regions not configured
1104 * - regions configured, but not enabled in the command register
1105 * - bogus I/O addresses above 64K used
1106 * - expansion ROMs left enabled (this may sound harmless, but given
1107 * the fact the PCI specs explicitly allow address decoders to be
1108 * shared between expansion ROMs and other resource regions, it's
1109 * at least dangerous)
1112 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1113 * This gives us fixed barriers on where we can allocate.
1114 * (2) Allocate resources for all enabled devices. If there is
1115 * a collision, just mark the resource as unallocated. Also
1116 * disable expansion ROMs during this step.
1117 * (3) Try to allocate resources for disabled devices. If the
1118 * resources were assigned correctly, everything goes well,
1119 * if they weren't, they won't disturb allocation of other
1121 * (4) Assign new addresses to resources which were either
1122 * not configured at all or misconfigured. If explicitly
1123 * requested by the user, configure expansion ROM address
1127 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1131 struct resource *res, *pr;
1133 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1134 pci_domain_nr(bus), bus->number);
1136 pci_bus_for_each_resource(bus, res, i) {
1137 if (!res || !res->flags
1138 || res->start > res->end || res->parent)
1140 if (bus->parent == NULL)
1141 pr = (res->flags & IORESOURCE_IO) ?
1142 &ioport_resource : &iomem_resource;
1144 /* Don't bother with non-root busses when
1145 * re-assigning all resources. We clear the
1146 * resource flags as if they were colliding
1147 * and as such ensure proper re-allocation
1150 pr = pci_find_parent_resource(bus->self, res);
1152 /* this happens when the generic PCI
1153 * code (wrongly) decides that this
1154 * bridge is transparent -- paulus
1160 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
1161 bus->self ? pci_name(bus->self) : "PHB",
1163 (unsigned long long)res->start,
1164 (unsigned long long)res->end);
1165 pr_debug("[0x%x], parent %p (%s)\n",
1166 (unsigned int)res->flags,
1167 pr, (pr && pr->name) ? pr->name : "nil");
1169 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1170 if (request_resource(pr, res) == 0)
1173 * Must be a conflict with an existing entry.
1174 * Move that entry (or entries) under the
1175 * bridge resource and try again.
1177 if (reparent_resources(pr, res) == 0)
1180 pr_warn("PCI: Cannot allocate resource region ");
1181 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
1182 res->start = res->end = 0;
1186 list_for_each_entry(b, &bus->children, node)
1187 pcibios_allocate_bus_resources(b);
1190 static inline void alloc_resource(struct pci_dev *dev, int idx)
1192 struct resource *pr, *r = &dev->resource[idx];
1194 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1196 (unsigned long long)r->start,
1197 (unsigned long long)r->end,
1198 (unsigned int)r->flags);
1200 pr = pci_find_parent_resource(dev, r);
1201 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1202 request_resource(pr, r) < 0) {
1203 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1204 pr_cont("of device %s, will remap\n", pci_name(dev));
1206 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1208 (unsigned long long)pr->start,
1209 (unsigned long long)pr->end,
1210 (unsigned int)pr->flags);
1211 /* We'll assign a new address later */
1212 r->flags |= IORESOURCE_UNSET;
1218 static void __init pcibios_allocate_resources(int pass)
1220 struct pci_dev *dev = NULL;
1225 for_each_pci_dev(dev) {
1226 pci_read_config_word(dev, PCI_COMMAND, &command);
1227 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1228 r = &dev->resource[idx];
1229 if (r->parent) /* Already allocated */
1231 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1232 continue; /* Not assigned at all */
1233 /* We only allocate ROMs on pass 1 just in case they
1234 * have been screwed up by firmware
1236 if (idx == PCI_ROM_RESOURCE)
1238 if (r->flags & IORESOURCE_IO)
1239 disabled = !(command & PCI_COMMAND_IO);
1241 disabled = !(command & PCI_COMMAND_MEMORY);
1242 if (pass == disabled)
1243 alloc_resource(dev, idx);
1247 r = &dev->resource[PCI_ROM_RESOURCE];
1249 /* Turn the ROM off, leave the resource region,
1250 * but keep it unregistered.
1253 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1254 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1255 pr_debug("PCI: Switching off ROM of %s\n",
1257 r->flags &= ~IORESOURCE_ROM_ENABLE;
1258 pci_write_config_dword(dev, dev->rom_base_reg,
1259 reg & ~PCI_ROM_ADDRESS_ENABLE);
1265 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1267 struct pci_controller *hose = pci_bus_to_host(bus);
1268 resource_size_t offset;
1269 struct resource *res, *pres;
1272 pr_debug("Reserving legacy ranges for domain %04x\n",
1273 pci_domain_nr(bus));
1276 if (!(hose->io_resource.flags & IORESOURCE_IO))
1278 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1279 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1280 BUG_ON(res == NULL);
1281 res->name = "Legacy IO";
1282 res->flags = IORESOURCE_IO;
1283 res->start = offset;
1284 res->end = (offset + 0xfff) & 0xfffffffful;
1285 pr_debug("Candidate legacy IO: %pR\n", res);
1286 if (request_resource(&hose->io_resource, res)) {
1287 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1288 pci_domain_nr(bus), bus->number, res);
1293 /* Check for memory */
1294 offset = hose->pci_mem_offset;
1295 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1296 for (i = 0; i < 3; i++) {
1297 pres = &hose->mem_resources[i];
1298 if (!(pres->flags & IORESOURCE_MEM))
1300 pr_debug("hose mem res: %pR\n", pres);
1301 if ((pres->start - offset) <= 0xa0000 &&
1302 (pres->end - offset) >= 0xbffff)
1307 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1308 BUG_ON(res == NULL);
1309 res->name = "Legacy VGA memory";
1310 res->flags = IORESOURCE_MEM;
1311 res->start = 0xa0000 + offset;
1312 res->end = 0xbffff + offset;
1313 pr_debug("Candidate VGA memory: %pR\n", res);
1314 if (request_resource(pres, res)) {
1315 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1316 pci_domain_nr(bus), bus->number, res);
1321 void __init pcibios_resource_survey(void)
1325 /* Allocate and assign resources. If we re-assign everything, then
1326 * we skip the allocate phase
1328 list_for_each_entry(b, &pci_root_buses, node)
1329 pcibios_allocate_bus_resources(b);
1331 pcibios_allocate_resources(0);
1332 pcibios_allocate_resources(1);
1334 /* Before we start assigning unassigned resource, we try to reserve
1335 * the low IO area and the VGA memory area if they intersect the
1336 * bus available resources to avoid allocating things on top of them
1338 list_for_each_entry(b, &pci_root_buses, node)
1339 pcibios_reserve_legacy_regions(b);
1341 /* Now proceed to assigning things that were left unassigned */
1342 pr_debug("PCI: Assigning unassigned resources...\n");
1343 pci_assign_unassigned_resources();
1346 /* This is used by the PCI hotplug driver to allocate resource
1347 * of newly plugged busses. We can try to consolidate with the
1348 * rest of the code later, for now, keep it as-is as our main
1349 * resource allocation function doesn't deal with sub-trees yet.
1351 void pcibios_claim_one_bus(struct pci_bus *bus)
1353 struct pci_dev *dev;
1354 struct pci_bus *child_bus;
1356 list_for_each_entry(dev, &bus->devices, bus_list) {
1359 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1360 struct resource *r = &dev->resource[i];
1362 if (r->parent || !r->start || !r->flags)
1365 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1366 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1367 i, (unsigned long long)r->start,
1368 (unsigned long long)r->end,
1369 (unsigned int)r->flags);
1371 pci_claim_resource(dev, i);
1375 list_for_each_entry(child_bus, &bus->children, node)
1376 pcibios_claim_one_bus(child_bus);
1380 /* pcibios_finish_adding_to_bus
1382 * This is to be called by the hotplug code after devices have been
1383 * added to a bus, this include calling it for a PHB that is just
1386 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1388 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1389 pci_domain_nr(bus), bus->number);
1391 /* Allocate bus and devices resources */
1392 pcibios_allocate_bus_resources(bus);
1393 pcibios_claim_one_bus(bus);
1395 /* Add new devices to global lists. Register in proc, sysfs. */
1396 pci_bus_add_devices(bus);
1399 /* eeh_add_device_tree_late(bus); */
1401 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1403 int pcibios_enable_device(struct pci_dev *dev, int mask)
1405 return pci_enable_resources(dev, mask);
1408 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1409 struct list_head *resources)
1411 unsigned long io_offset;
1412 struct resource *res;
1415 /* Hookup PHB IO resource */
1416 res = &hose->io_resource;
1418 /* Fixup IO space offset */
1419 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1420 res->start = (res->start + io_offset) & 0xffffffffu;
1421 res->end = (res->end + io_offset) & 0xffffffffu;
1424 pr_warn("PCI: I/O resource not set for host ");
1425 pr_cont("bridge %s (domain %d)\n",
1426 hose->dn->full_name, hose->global_number);
1427 /* Workaround for lack of IO resource only on 32-bit */
1428 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1429 res->end = res->start + IO_SPACE_LIMIT;
1430 res->flags = IORESOURCE_IO;
1432 pci_add_resource_offset(resources, res,
1433 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1435 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1436 (unsigned long long)res->start,
1437 (unsigned long long)res->end,
1438 (unsigned long)res->flags);
1440 /* Hookup PHB Memory resources */
1441 for (i = 0; i < 3; ++i) {
1442 res = &hose->mem_resources[i];
1446 pr_err("PCI: Memory resource 0 not set for ");
1447 pr_cont("host bridge %s (domain %d)\n",
1448 hose->dn->full_name, hose->global_number);
1450 /* Workaround for lack of MEM resource only on 32-bit */
1451 res->start = hose->pci_mem_offset;
1452 res->end = (resource_size_t)-1LL;
1453 res->flags = IORESOURCE_MEM;
1456 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1458 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1459 i, (unsigned long long)res->start,
1460 (unsigned long long)res->end,
1461 (unsigned long)res->flags);
1464 pr_debug("PCI: PHB MEM offset = %016llx\n",
1465 (unsigned long long)hose->pci_mem_offset);
1466 pr_debug("PCI: PHB IO offset = %08lx\n",
1467 (unsigned long)hose->io_base_virt - _IO_BASE);
1470 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1472 struct pci_controller *hose = bus->sysdata;
1474 return of_node_get(hose->dn);
1477 static void pcibios_scan_phb(struct pci_controller *hose)
1479 LIST_HEAD(resources);
1480 struct pci_bus *bus;
1481 struct device_node *node = hose->dn;
1483 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1485 pcibios_setup_phb_resources(hose, &resources);
1487 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1488 hose->ops, hose, &resources);
1490 pr_err("Failed to create bus for PCI domain %04x\n",
1491 hose->global_number);
1492 pci_free_resource_list(&resources);
1495 bus->busn_res.start = hose->first_busno;
1498 hose->last_busno = bus->busn_res.end;
1501 static int __init pcibios_init(void)
1503 struct pci_controller *hose, *tmp;
1506 pr_info("PCI: Probing PCI hardware\n");
1508 /* Scan all of the recorded PCI controllers. */
1509 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1510 hose->last_busno = 0xff;
1511 pcibios_scan_phb(hose);
1512 if (next_busno <= hose->last_busno)
1513 next_busno = hose->last_busno + 1;
1515 pci_bus_count = next_busno;
1517 /* Call common code to handle resource allocation */
1518 pcibios_resource_survey();
1523 subsys_initcall(pcibios_init);
1525 static struct pci_controller *pci_bus_to_hose(int bus)
1527 struct pci_controller *hose, *tmp;
1529 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1530 if (bus >= hose->first_busno && bus <= hose->last_busno)
1535 /* Provide information on locations of various I/O regions in physical
1536 * memory. Do this on a per-card basis so that we choose the right
1538 * Note that the returned IO or memory base is a physical address
1541 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1543 struct pci_controller *hose;
1544 long result = -EOPNOTSUPP;
1546 hose = pci_bus_to_hose(bus);
1551 case IOBASE_BRIDGE_NUMBER:
1552 return (long)hose->first_busno;
1554 return (long)hose->pci_mem_offset;
1556 return (long)hose->io_base_phys;
1558 return (long)isa_io_base;
1559 case IOBASE_ISA_MEM:
1560 return (long)isa_mem_base;
1567 * Null PCI config access functions, for the case when we can't
1570 #define NULL_PCI_OP(rw, size, type) \
1572 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1574 return PCIBIOS_DEVICE_NOT_FOUND; \
1578 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1581 return PCIBIOS_DEVICE_NOT_FOUND;
1585 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1588 return PCIBIOS_DEVICE_NOT_FOUND;
1591 static struct pci_ops null_pci_ops = {
1592 .read = null_read_config,
1593 .write = null_write_config,
1597 * These functions are used early on before PCI scanning is done
1598 * and all of the pci_dev and pci_bus structures have been created.
1600 static struct pci_bus *
1601 fake_pci_bus(struct pci_controller *hose, int busnr)
1603 static struct pci_bus bus;
1606 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1610 bus.ops = hose ? hose->ops : &null_pci_ops;
1614 #define EARLY_PCI_OP(rw, size, type) \
1615 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1616 int devfn, int offset, type value) \
1618 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1619 devfn, offset, value); \
1622 EARLY_PCI_OP(read, byte, u8 *)
1623 EARLY_PCI_OP(read, word, u16 *)
1624 EARLY_PCI_OP(read, dword, u32 *)
1625 EARLY_PCI_OP(write, byte, u8)
1626 EARLY_PCI_OP(write, word, u16)
1627 EARLY_PCI_OP(write, dword, u32)
1629 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1632 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);