--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = arch board
--- /dev/null
+# Makefile.rules - OCERA make framework common project rules -*- makefile -*-
+#
+# (C) Copyright 2003 by Pavel Pisa - OCERA team member
+#
+# input variables
+# V .. if set to 1, full command text is shown else short form is used
+# SUBDIRS .. list of subdirectories intended for make from actual directory
+# default_CONFIG .. list of default config assignments CONFIG_XXX=y/n ...
+
+BUILD_DIR_NAME = _build
+COMPILED_DIR_NAME = _compiled
+ifndef GROUP_DIR_NAME
+GROUP_DIR_NAME = nogroup
+endif
+
+# We need to ensure definition of sources directory first
+ifndef SOURCES_DIR
+SOURCES_DIR := $(shell ( pwd -L ) )
+endif
+
+.PHONY: all default check-make-ver
+
+all: check-make-ver default
+
+#=========================
+# Include the config file
+
+# First, include for which target we are compiling
+-include $(MAKERULES_DIR)/config.target
+ifeq ($(wildcard $(MAKERULES_DIR)/config.target),)
+$(warning You may want to create $(MAKERULES_DIR)/config.target)
+endif
+
+
+ifndef CONFIG_FILE
+CONFIG_FILE := $(MAKERULES_DIR)/config.omk
+endif
+ifneq ($(wildcard $(CONFIG_FILE)-default),)
+-include $(CONFIG_FILE)-default
+else
+$(warning Please, run "make default-config" first)
+endif
+
+ifneq ($(wildcard $(CONFIG_FILE)),)
+include $(CONFIG_FILE)
+CONFIG_FILE_OK = y
+endif
+
+export SOURCES_DIR MAKERULES_DIR RELATIVE_DIR
+export CONFIG_FILE OMK_SERIALIZE_INCLUDED OMK_VERBOSE OMK_SILENT
+
+ifndef RELATIVE_DIR
+RELATIVE_DIR := $(SOURCES_DIR:$(MAKERULES_DIR)%=%)
+endif
+override RELATIVE_DIR := $(RELATIVE_DIR:/%=%)
+override RELATIVE_DIR := $(RELATIVE_DIR:\\%=%)
+#$(warning RELATIVE_DIR $(RELATIVE_DIR))
+override BACK2TOP_DIR := $(shell echo $(RELATIVE_DIR)/ | sed -e 's_//_/_g' -e 's_/\./_/_g' -e 's_^\./__g' -e 's_\([^/][^/]*\)_.._g' -e 's_/$$__')
+#$(warning BACK2TOP_DIR $(BACK2TOP_DIR))
+
+#$(warning SOURCES_DIR = $(SOURCES_DIR))
+#$(warning MAKERULES_DIR = $(MAKERULES_DIR))
+#$(warning RELATIVE_DIR = $(RELATIVE_DIR))
+
+LOCAL_BUILD_DIR=$(MAKERULES_DIR)/$(BUILD_DIR_NAME)/$(RELATIVE_DIR)
+#$(warning LOCAL_BUILD_DIR = $(LOCAL_BUILD_DIR))
+
+#vpath %.c $(SOURCES_DIR)
+#vpath %.cc $(SOURCES_DIR)
+#vpath %.cxx $(SOURCES_DIR)
+
+VPATH = $(SOURCES_DIR)
+srcdir = $(SOURCES_DIR)
+
+# Defines for quiet compilation
+ifdef V
+ ifeq ("$(origin V)", "command line")
+ OMK_VERBOSE = $(V)
+ endif
+endif
+ifndef OMK_VERBOSE
+ OMK_VERBOSE = 0
+endif
+ifeq ($(OMK_VERBOSE),1)
+ Q =
+else
+ Q = @
+endif
+ifneq ($(findstring s,$(MAKEFLAGS)),)
+ QUIET_CMD_ECHO = true
+ OMK_SILENT = 1
+else
+ QUIET_CMD_ECHO = echo
+ CP_FLAGS += -v
+endif
+
+# We have set up all important variables, so we can check and include
+# real OCERA style Makefile.omk now
+ifndef OMK_INCLUDED
+include $(SOURCES_DIR)/Makefile.omk
+OMK_INCLUDED := 1
+endif
+
+
+check-make-ver:
+ @GOOD_MAKE_VERSION=`echo $(MAKE_VERSION) | sed -n -e 's/^[4-9]\..*\|^3\.9[0-9].*\|^3\.8[1-9].*/y/p'` ; \
+ if [ x$$GOOD_MAKE_VERSION != xy ] ; then \
+ echo "Your make program version is too old and does not support OMK system." ; \
+ echo "Please update to make program 3.81beta1 or newer." ; exit 1 ; \
+ fi
+
+default-config:
+ @echo "# Start of OMK config file" > "$(CONFIG_FILE)-default"
+ @echo "# This file should not be altered manually" >> "$(CONFIG_FILE)-default"
+ @echo "# Overrides should be stored in file $(notdir $(CONFIG_FILE))" >> "$(CONFIG_FILE)-default"
+ @echo >> "$(CONFIG_FILE)-default"
+ @$(MAKE) --no-print-directory -C $(MAKERULES_DIR) \
+ RELATIVE_DIR="" SOURCES_DIR=$(MAKERULES_DIR) \
+ -f $(MAKERULES_DIR)/Makefile default-config-pass
+
+# Common OMK templates
+# ====================
+
+# Syntax: $(call mkdir,<pass name>,<local make flags>)
+define mkdir_def
+ [ -d $(1) ] || mkdir -p $(1) || exit 1
+endef
+
+# Syntax: $(call omk_pass_template,<pass name>,<local make flags>)
+define omk_pass_template
+.PHNOY: $(1) $(1)-local
+$(1):
+ +@$(foreach dir,$(SUBDIRS),$(call mkdir_def,$(LOCAL_BUILD_DIR)/$(dir)) ; \
+ $(MAKE) SOURCES_DIR=$(SOURCES_DIR)/$(dir) \
+ RELATIVE_DIR=$(RELATIVE_DIR)/$(dir) -C $(LOCAL_BUILD_DIR)/$(dir) \
+ -f $(SOURCES_DIR)/$(dir)/Makefile $$@ || exit 1 ;)
+ +@$(call mkdir_def,$(LOCAL_BUILD_DIR))
+ @$(MAKE) --no-print-directory -C $(LOCAL_BUILD_DIR) \
+ -f $(SOURCES_DIR)/Makefile $(2) $$(@:%=%-local)
+endef
+
+# =======================
+# DEFAULT CONFIG PASS
+
+$(eval $(call omk_pass_template,default-config-pass))
+default-config-pass-local:
+ @echo Default config for $(RELATIVE_DIR)
+ @echo "# Config for $(RELATIVE_DIR)" >> "$(CONFIG_FILE)-default"
+ @$(foreach x, $(default_CONFIG), echo $(x) | \
+ sed -e 's/^.*=x$$/#\0/' >> "$(CONFIG_FILE)-default" ; )
+
+
+# =======================
+
+
+# TODO: Put rules specific to C language to a separate file
+#include $(MAKERULES_DIR)/Makefile.rules.c-lang
+
+include $(MAKERULES_DIR)/Makefile.rules.h8300-boot
+
--- /dev/null
+# -*- makefile -*-
+
+# This Makefile is included from Makefile.rules and contains rules
+# specific to the h8300-boot project.
+
+# input variables
+# bin_PROGRAMS .. list of the require binary programs
+# include_HEADERS .. list of the user-space public header files
+# lib_LIBRARIES .. list of the user-space libraries
+# lib_LDSCRIPT .. list of LD scripts that should be copied to the lib direcotry
+# lib_obj_SOURCES .. list of source files which should be compiled and produced object file placed to lib directory (e.g. crt0.S)
+# shared_LIBRARIES .. list of the user-space shared libraries
+# nobase_include_HEADERS .. public headers copied even with directory part
+# renamed_include_HEADERS .. public headers copied to the different target name (xxx.h->yyy.h)
+# utils_PROGRAMS .. list of the development utility programs
+# xxx_SOURCES .. list of specific target sources
+# INCLUDES .. additional include directories and defines for user-space
+
+USER_COMPILED_DIR_NAME=$(MAKERULES_DIR)/$(COMPILED_DIR_NAME)
+
+USER_INCLUDE_DIR := $(USER_COMPILED_DIR_NAME)/include
+USER_LIB_DIR := $(USER_COMPILED_DIR_NAME)/lib
+USER_UTILS_DIR := $(USER_COMPILED_DIR_NAME)/bin-utils
+USER_BIN_DIR := $(USER_COMPILED_DIR_NAME)/bin
+USER_OBJS_DIR := $(LOCAL_BUILD_DIR)
+
+
+CFLAGS += $(TARGET_ARCH)
+CFLAGS += -g
+CFLAGS += -O2 -Wall
+CFLAGS += -I.
+CFLAGS += -I$(USER_INCLUDE_DIR)
+
+LOADLIBES += -L$(USER_LIB_DIR)
+LOADLIBES += $(lib_LOADLIBES:%=-l%)
+
+LDFLAGS = -nostartfiles
+
+LIB_CPPFLAGS += $(CPPFLAGS)
+LIB_CFLAGS += $(CFLAGS)
+
+SOLIB_PICFLAGS += -shared -fpic
+
+# Some support to serialize some targets for parallel make
+ifneq ($(OMK_SERIALIZE_INCLUDED),y)
+include-pass: check-dir
+library-pass: include-pass
+binary-pass utils-pass: library-pass
+
+OMK_SERIALIZE_INCLUDED = y
+endif
+
+#=====================================================================
+# Common utility rules
+
+ifdef LOCAL_CONFIG_H
+
+$(LOCAL_CONFIG_H) : $(wildcard $(CONFIG_FILE)) $(wildcard $(CONFIG_FILE)-default)
+ @echo LOCAL_CONFIG_H=`pwd`/$(LOCAL_CONFIG_H)
+ @echo "/* Automatically generated from */" > "$(LOCAL_CONFIG_H).tmp"
+ @echo "/* config file : $< */" >> "$(LOCAL_CONFIG_H).tmp"
+ @echo "#ifndef _LOCAL_CONFIG_H" >> "$(LOCAL_CONFIG_H).tmp"
+ @echo "#define _LOCAL_CONFIG_H" >> "$(LOCAL_CONFIG_H).tmp"
+ @( $(foreach x, $(shell echo $(default_CONFIG) | sed -e 's/\<\([^ ]*\)=[^ ]\>/\1/g' ), \
+ echo $(x).$($(x)) ; ) echo ; ) | \
+ sed -n -e 's/^\(.*\)\.[ym]$$/#define \1 1/p' \
+ >> "$(LOCAL_CONFIG_H).tmp"
+ @echo "#endif /*_LOCAL_CONFIG_H*/" >> "$(LOCAL_CONFIG_H).tmp"
+ @if cmp --quiet "$(LOCAL_CONFIG_H).tmp" "$(LOCAL_CONFIG_H)" ; then \
+ echo rm "$(LOCAL_CONFIG_H).tmp" ; \
+ else mv "$(LOCAL_CONFIG_H).tmp" "$(LOCAL_CONFIG_H)" ; \
+ echo Updated configuration "$(LOCAL_CONFIG_H)" ; fi
+
+endif
+
+#=====================================================================
+# User-space rules and templates to compile programs, libraries etc.
+
+ifdef USER_RULE_TEMPLATES
+
+-include $(USER_OBJS_DIR)/*.d
+
+#%.lo: %.c
+# $(CC) -o $@ $(LCFLAGS) -c $<
+
+S_o_COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) $(ASFLAGS) -DOMK_FOR_USER
+
+c_o_COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -DOMK_FOR_USER
+
+cc_o_COMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -DOMK_FOR_USER
+
+
+# Check GCC version for user build
+ifndef CC_MAJOR_VERSION
+CC_MAJOR_VERSION := $(shell $(CC) -dumpversion | sed -e 's/\([^.]\)\..*/\1/')
+endif
+# Prepare suitable define for dependency building
+ifeq ($(CC_MAJOR_VERSION),2)
+CC_DEPFLAGS = -Wp,-MD,"$@.d.tmp"
+else
+CC_DEPFLAGS = -MT $@ -MD -MP -MF "$@.d.tmp"
+endif
+
+
+
+# Syntax: $(call COMPILE_c_o_template,<source>,<target>,<additional c-flags>)
+define COMPILE_c_o_template
+$(2): $(1) $(LOCAL_CONFIG_H)
+ @$(QUIET_CMD_ECHO) " CC $$@"
+ $(Q) if $$(c_o_COMPILE) $$(CC_DEPFLAGS) $(3) -o $$@ -c $$< ; \
+ then mv -f "$$@.d.tmp" "$$@.d" ; \
+ else rm -f "$$@.d.tmp" ; exit 1; \
+ fi
+endef
+
+
+
+# Syntax: $(call COMPILE_cc_o_template,<source>,<target>,<additional c-flags>)
+define COMPILE_cc_o_template
+$(2): $(1) $(LOCAL_CONFIG_H)
+ @$(QUIET_CMD_ECHO) " CXX $$@"
+ $(Q) if $$(cc_o_COMPILE) $$(CC_DEPFLAGS) $(3) -o $$@ -c $$< ; \
+ then mv -f "$$@.d.tmp" "$$@.d" ; \
+ else rm -f "$$@.d.tmp" ; exit 1; \
+ fi
+endef
+
+# Syntax: $(call COMPILE_S_o_template,<source>,<target>,<additional c-flags>)
+define COMPILE_S_o_template
+$(2): $(1) $(LOCAL_CONFIG_H)
+ @$(QUIET_CMD_ECHO) " AS $$@"
+ $(Q) if $$(S_o_COMPILE) -D__ASSEMBLY__ $$(CC_DEPFLAGS) $(3) -o $$@ -c $$< ; \
+ then mv -f "$$@.d.tmp" "$$@.d" ; \
+ else rm -f "$$@.d.tmp" ; exit 1; \
+ fi
+endef
+
+
+# Syntax: $(call PROGRAM_template,<dir>,<executable-name>)
+define PROGRAM_template
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.c=%.o))
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.cc=%.o))
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.cxx=%.o))
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.S=%.o))
+$(1)_OBJS += $$(filter %.o,$(1)_SOURCES)
+$(1)_OBJS := $$(sort $$($(1)_OBJS))
+
+USER_OBJS += $$($(1)_OBJS) # Is this variable useful?
+USER_SOURCES += $$($(1)_SOURCES)
+
+$(2)/$(1): $$($(1)_OBJS)
+ @$(QUIET_CMD_ECHO) " LINK $$@"
+ $(Q) $$(shell if [ -z "$$(filter %.cc,$$($(1)_SOURCES))" ] ; \
+ then echo $$(CC) $$(CPPFLAGS) $$(AM_CPPFLAGS) $$(AM_CFLAGS) $$(CFLAGS) ; \
+ else echo $$(CXX) $$(CPPFLAGS) $$(AM_CPPFLAGS) $$(AM_CXXFLAGS) $$(CXXFLAGS) ; fi) \
+ $$(AM_LDFLAGS) -Wl,-T,$(USER_LIB_DIR)/$(BOARD_LAYOUT).ld-$(LINK_VARIANT) $$(LDFLAGS) $$($(1)_OBJS) $$(LOADLIBES) $$($(1)_LIBS:%=-l%) \
+ -o $(2)/$(1)
+# @echo "$(2)/$(1): \\" >$(USER_OBJS_DIR)/$(1).exe.d
+# @sed -n -e 's/^LOAD \(.*\)$$$$/ \1 \\/p' $(USER_OBJS_DIR)/$(1).exe.map >>$(USER_OBJS_DIR)/$(1).exe.d
+# @echo >>$(USER_OBJS_DIR)/$(1).exe.d
+
+endef
+
+%.bin: %
+ @$(QUIET_CMD_ECHO) " OBJCOPY $@"
+ $(Q) $(OBJCOPY) --output-target=binary -S $< $@
+
+# Syntax: $(call LIBRARY_template,<library-name>)
+define LIBRARY_template
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.c=%.o))
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.cc=%.o))
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.cxx=%.o))
+$(1)_OBJS += $$(filter %.o,$$($(1)_SOURCES:%.S=%.o))
+$(1)_OBJS := $$(sort $$($(1)_OBJS))
+
+USER_OBJS += $$($(1)_OBJS)
+USER_SOURCES += $$($(1)_SOURCES)
+
+$(USER_LIB_DIR)/lib$(1).a: $$($(1)_OBJS)
+ @$(QUIET_CMD_ECHO) " AR $$@"
+ $(Q) $(AR) rcs $$@ $$^
+endef
+
+
+# Syntax: $(call SOLIB_template,<library-name>)
+define SOLIB_template
+$(1)_OBJSLO += $$(filter %.lo,$$($(1)_SOURCES:%.c=%.lo))
+$(1)_OBJSLO += $$(filter %.lo,$$($(1)_SOURCES:%.cc=%.lo))
+$(1)_OBJSLO += $$(filter %.lo,$$($(1)_SOURCES:%.cxx=%.lo))
+$(1)_OBJSLO += $$(filter %.o,$$($(1)_SOURCES:%.S=%.o))
+$(1)_OBJSLO := $$(sort $$($(1)_OBJSLO))
+
+SOLIB_OBJS += $$($(1)_OBJSLO)
+SOLIB_SOURCES += $$($(1)_SOURCES)
+
+$(USER_LIB_DIR)/lib$(1).so: $$($(1)_OBJSLO)
+ @$(QUIET_CMD_ECHO) " LINK $$@"
+ $(Q) $(LD) --shared --soname=lib$(1).so -o $$@ $$^
+endef
+
+
+# lib_obj_SOURCES handling
+lib_OBJS = $(addsuffix .o,$(basename $(lib_obj_SOURCES)))
+USER_OBJS += $(lib_OBJS)
+USER_SOURCES += $(lib_obj_SOURCES)
+#$(warning lib_OBJS = $(lib_OBJS))
+
+# # Syntax: $(call LIBOBJ_template,<object-name>)
+# define LIBOBJ_template
+# $(USER_LIB_DIR)/$(1): $(1)
+# @cp $(CP_FLAGS) $$< $$@
+# endef
+$(USER_LIB_DIR)/%.o: %.o
+ @cp $(CP_FLAGS) $< $@
+
+# Local rules - rules executed to do some real work in current direcotry
+
+library-pass-local: $(lib_LIBRARIES:%=$(USER_LIB_DIR)/lib%.a) $(shared_LIBRARIES:%=$(USER_LIB_DIR)/lib%.so) $(addprefix $(USER_LIB_DIR)/,$(lib_OBJS))
+
+binary-pass-local: $(bin_PROGRAMS:%=$(USER_BIN_DIR)/%) $(bin_PROGRAMS:%=$(USER_BIN_DIR)/%.bin)
+
+utils-pass-local: $(utils_PROGRAMS:%=$(USER_UTILS_DIR)/%)
+
+$(foreach prog,$(utils_PROGRAMS),$(eval $(call PROGRAM_template,$(prog),$(USER_UTILS_DIR))))
+
+$(foreach prog,$(bin_PROGRAMS),$(eval $(call PROGRAM_template,$(prog),$(USER_BIN_DIR))))
+
+$(foreach lib,$(lib_LIBRARIES),$(eval $(call LIBRARY_template,$(lib))))
+
+$(foreach src,$(lib_obj_SOURCES),$(eval $(call LIBOBJ_template,$(addsuffix .o,$(basename $(src))))))
+
+$(foreach lib,$(shared_LIBRARIES),$(eval $(call SOLIB_template,$(lib))))
+
+# User-space static libraries and applications object files
+
+USER_SOURCES := $(sort $(USER_SOURCES))
+
+#$(warning USER_SOURCES = $(USER_SOURCES))
+
+$(foreach src,$(filter %.c,$(USER_SOURCES)),$(eval $(call COMPILE_c_o_template,$(SOURCES_DIR)/$(src),$(src:%.c=%.o),)))
+
+$(foreach src,$(filter %.cc,$(USER_SOURCES)),$(eval $(call COMPILE_cc_o_template,$(SOURCES_DIR)/$(src),$(src:%.cc=%.o),)))
+
+$(foreach src,$(filter %.cxx,$(USER_SOURCES)),$(eval $(call COMPILE_cc_o_template,$(SOURCES_DIR)/$(src),$(src:%.cxx=%.o),)))
+
+$(foreach src,$(filter %.S,$(USER_SOURCES)),$(eval $(call COMPILE_S_o_template,$(SOURCES_DIR)/$(src),$(src:%.S=%.o),)))
+
+# User-space shared libraries object files
+
+SOLIB_SOURCES := $(sort $(SOLIB_SOURCES))
+
+#$(warning SOLIB_SOURCES = $(SOLIB_SOURCES))
+
+$(foreach src,$(filter %.c,$(SOLIB_SOURCES)),$(eval $(call COMPILE_c_o_template,$(SOURCES_DIR)/$(src),$(src:%.c=%.lo),$(SOLIB_PICFLAGS))))
+
+$(foreach src,$(filter %.cc,$(SOLIB_SOURCES)),$(eval $(call COMPILE_cc_o_template,$(SOURCES_DIR)/$(src),$(src:%.cc=%.lo),$(SOLIB_PICFLAGS))))
+
+$(foreach src,$(filter %.cxx,$(SOLIB_SOURCES)),$(eval $(call COMPILE_cc_o_template,$(SOURCES_DIR)/$(src),$(src:%.cxx=%.lo),$(SOLIB_PICFLAGS))))
+
+$(foreach src,$(filter %.S,$(SOLIB_SOURCES)),$(eval $(call COMPILE_S_o_template,$(SOURCES_DIR)/$(src),$(src:%.S=%.lo),$(SOLIB_PICFLAGS))))
+
+endif # USER_RULE_TEMPLATES
+
+#=====================================================================
+# Generate pass rules from generic templates
+USER_PASSES = library-pass binary-pass utils-pass
+OTHER_PASSES = dep clean install check-dir include-pass
+
+$(eval $(call omk_pass_template,$(USER_PASSES),USER_RULE_TEMPLATES=y))
+$(eval $(call omk_pass_template,$(OTHER_PASSES),))
+
+
+dep-local:
+
+check-dir-local:
+ @$(call mkdir_def,$(USER_OBJS_DIR))
+ @$(call mkdir_def,$(USER_INCLUDE_DIR))
+ @$(call mkdir_def,$(USER_LIB_DIR))
+ @$(call mkdir_def,$(USER_BIN_DIR))
+ @$(call mkdir_def,$(USER_UTILS_DIR))
+
+install-local:
+
+# TODO: Check modification date of changed header files. If it is
+# newer that in source dir, show a warning.
+include-pass-local:
+ @$(call mkdir_def,$(USER_INCLUDE_DIR))
+ @$(foreach f, $(include_HEADERS), cmp --quiet $(SOURCES_DIR)/$(f) $(USER_INCLUDE_DIR)/$(notdir $(f)) \
+ || cp $(CP_FLAGS) $(SOURCES_DIR)/$(f) $(USER_INCLUDE_DIR)/$(notdir $(f)) || exit 1 ; )
+ @$(foreach f, $(nobase_include_HEADERS), cmp --quiet $(SOURCES_DIR)/$(f) $(USER_INCLUDE_DIR)/$(f) \
+ || ( mkdir -p $(USER_INCLUDE_DIR)/$(dir $(f)) && cp $(CP_FLAGS) $(SOURCES_DIR)/$(f) $(USER_INCLUDE_DIR)/$(f) ) || exit 1 ; )
+ @$(foreach f, $(renamed_include_HEADERS), \
+ srcfname=`echo '$(f)' | sed -e 's/^\(.*\)->.*$$/\1/'` ; destfname=`echo '$(f)' | sed -e 's/^.*->\(.*\)$$/\1/'` ; \
+ cmp --quiet $(SOURCES_DIR)/$${srcfname} $(USER_INCLUDE_DIR)/$${destfname} \
+ || ( mkdir -p `dirname $(USER_INCLUDE_DIR)/$${destfname}` && cp $(CP_FLAGS) $(SOURCES_DIR)/$${srcfname} $(USER_INCLUDE_DIR)/$${destfname} ) || exit 1 ; )
+ @$(call mkdir_def,$(USER_LIB_DIR))
+ @$(foreach f, $(lib_LDSCRIPT), cmp --quiet $(SOURCES_DIR)/$(f) $(USER_LIB_DIR)/$(notdir $(f)) \
+ || cp $(CP_FLAGS) $(SOURCES_DIR)/$(f) $(USER_LIB_DIR)/$(notdir $(f)) || exit 1 ; )
+
+
+
+clean-local:
+ @echo Cleaning in $(USER_OBJS_DIR)
+ @rm -f $(USER_OBJS_DIR)/*.o $(USER_OBJS_DIR)/*.lo \
+ $(USER_OBJS_DIR)/*.d \
+ $(USER_OBJS_DIR)/*.map \
+ $(LOCAL_CONFIG_H:%=$(USER_OBJS_DIR)/%)
+
+
+# Which passes to pass
+default: check-dir include-pass library-pass binary-pass utils-pass
--- /dev/null
+!!! TODO: Modify this to agree with h8300 project
+
+Description of OCERA Make System for CAN Components (OMK)
+=========================================================
+
+Important notice:
+This make system uses features found in recent versions of GNU Make
+program. If you encounter problems with package building,
+check, that you use correct version of Make program.
+The Make older than version 3.80, could not be used.
+Even Make version 3.80 has annoying bug which causes
+building fail with misleading message "virtual memory exhausted".
+Please, upgrade to last version of Make (3.81beta1).
+You can take it from GNU CVS, Paul D. Smith's site or from our local copy
+ http://paulandlesley.org/make/make-3.81beta1.tar.bz2
+ http://cmp.felk.cvut.cz/~pisa/can/make-3.81beta1.tar.gz
+
+
+There is list of features which we want to solve with our makesystem:
+ - central Makefile.rules for most of subcomponents and components
+ (our CAN framework includes more libraries common with our other projects,
+ we need to separate some utility libraries etc.)
+ - the rules in more spread Makefiles are way to the hell,
+ (update for different kernel, RT-Linux etc would be nightmare in other case)
+ - make system should allow to freely move with cross-dependant components
+ without need to update users of moved component
+ (I hate somethink like -I../../sched/rtlshwq/include in CAN makefiles
+ for example. Component could be renamed to different name or version
+ could be added to name and all Makefiles in CAN would require to
+ be updated)
+ - make system should be able to compile mutually cross-dependant libraries
+ and should ensure, that change in one component sources or headers
+ would result in relink or rebuild in components linked against that library
+ or including modified header file
+ - make system has to enable compilation out of OCERA full source tree
+ (we would lost many users of particular components in other case)
+ - compile should be able to do all above work without need to install
+ any files before successful finish of build.
+ - because we use some libraries for RT-Linux build and userspace
+ build, we need to solve how to compile from same sources to both targets.
+ - the build system should allow to call make for particular source
+ subdirectory. Time of recursive make through all subdirectories is
+ unacceptable.
+ - make system should enable to build out of sources tree
+ (else clean or working with CVS sandbox gets fussy and simultaneous
+ multiple targets gets problematic)
+ - it would be good, if there would be possibility to make from read-only
+ media sources
+ - make system should store results of build in some separate directory
+ structure to simple install and testing
+ - Makefiles in sources directories should be simple
+
+There is probably only one alternative fully supporting above requirements
+and it is GNU Autoheader...Automake...Autoconf... system.
+But it is complicated and requires big amount of support files.
+It would be acceptable if it could be easily used for OCERA framework.
+But there are important show stopper for that system:
+ - it would require deep revision of all OCERA CVS contents and agreement
+ on this would be problematic
+ - this system is not well prepared for dual compilation for Linux
+ and RT-Linux sub-targets. It would mean many changes in default
+ autoconf setup to support this. Probably simplest way would be
+ to rebuild GCC tool chain for something like i586-elf-rtlinux.
+ This would require even more space for OCERA development.
+
+The problem calls for same solution, which would have minimal impact
+on other components and would be elegant and would be maintainable
+and small, because our main goal is components development and not
+make systems development.
+
+There is result of our trial. It is OMK make system.
+The Makefile and Makefile.omk files should be in all source
+directories. Common Makefile.rules file is required in the toplevel
+sources directory. Alternatively this file could be moved
+to link tree pointing into readonly media or can be anywhere
+else if MAKERULES_DIR and SOURCES_DIR are specified.
+
+Syntax of Makefile.omk files is for usual cases compatible
+to Automake's Makefile.am descriptions. There are specific targets
+for RT-Linux and Linux kernel related stuff
+
+Makefile.omk user defined variables
+# SUBDIRS .. list of subdirectories intended for make from actual directory
+# lib_LIBRARIES .. list of the user-space libraries
+# shared_LIBRARIES .. list of the user-space shared libraries
+# kernel_LIBRARIES .. list of the kernel-space libraries
+# rtlinux_LIBRARIES.. list of the RT-Linux kernel-space libraries
+# include_HEADERS .. list of the user-space header files
+# nobase_include_HEADERS .. headers copied even with directory part
+# kernel_HEADERS .. list of the kernel-space header files
+# rtlinux_HEADERS .. list of the RT-Linux kernel-space header files
+# bin_PROGRAMS .. list of the require binary programs
+# utils_PROGRAMS .. list of the development utility programs
+# kernel_MODULES .. list of the kernel side modules/applications
+# rtlinux_MODULES .. list of RT-Linux the kernel side modules/applications
+# xxx_SOURCES .. list of specific target sources
+# INCLUDES .. additional include directories and defines for user-space
+# kernel_INCLUDES .. additional include directories and defines for kernel-space
+# rtlinux_INCLUDES .. additional include directories and defines for RT-Linux
+# default_CONFIG .. list of default config assignments CONFIG_XXX=y/n ...
+
+The Makefile is same for all sources directories and is only 14 lines long.
+It is there only for convenience reasons to enable call "make" from
+local directory. It contains code which locates Makefile.rules in actual
+or any parent directory. With standard BASH environment it works such way,
+that if you get into sources directory over symbolic links, it is able to
+unwind yours steps back => you can make links to readonly media component
+directories, copy Makefile.rules, Makefile and toplevel Makefile.omk,
+adjust Makefile.omk to contain only required components and then call
+make in top or even directories after crossing from your tree
+to readonly media.
+
+The system compiles all files out of source directories.
+The actual version of system is adapted even for OCERA tree mode
+if OCERA_DIR variable is defined in Makefile.rules
+
+There are next predefined directory name components,
+which can be adapted if required
+
+BUILD_DIR_NAME = _build
+ prefix of directory, where temporary build files are stored
+COMPILED_DIR_NAME = _compiled
+ prefix of directory, where final compilation results are stored
+GROUP_DIR_NAME = yyy
+ this is used for separation of build sub-trees in OCERA environment
+ where more Makefile.rules is spread in the tree
+
+Next directories are used:
+
+KERN_BUILD_DIR := $(MAKERULES_DIR)/$(BUILD_DIR_NAME)/kern
+ directory to store intermediate files for kernel-space targets
+USER_BUILD_DIR := $(MAKERULES_DIR)/$(BUILD_DIR_NAME)/user
+ directory to store intermediate files for user-space targets
+
+USER_INCLUDE_DIR := $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/include
+ directory to store exported include files which should be installed later
+ on user-space include path
+USER_LIB_DIR := $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/lib
+ same for user-pace libraries
+USER_UTILS_DIR := $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils
+ utilities for testing, which would not probably be installed
+USER_BIN_DIR := $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin
+ binaries, which should go into directory on standard system PATH
+ (/usr/local/bin, /usr/bin or $(prefix)/bin)
+
+KERN_INCLUDE_DIR := $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/include-kern
+ directory to store exported include files which should be installed later
+ on kernel-space include path
+KERN_LIB_DIR := $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/lib-kern
+ same for kernel-pace libraries
+KERN_MODULES_DIR := $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/modules
+ builded modules for Linux kernel or RT-Linux system
+
+There is more recursive passes through directories to enable
+mutual dependant libraries and binaries to compile.
+Next passes are defined
+
+default-config .. generates config.omk-default or xxx-default configuration file
+check-dir .. checks and creates required build directories
+include-pass .. copyes header files to USER_INCLUDE_DIR and KERN_INCLUDE_DIR
+library-pass .. builds objects in USER_BUILD_DIR/<relative path> and creates
+ libraries in USER_LIB_DIR
+binary-pass and utils-pass .. links respective binaries
+ in USER_{BIN,UTILS}_DIR directory. If some object file is missing
+ it compiles it in USER_BUILD_DIR/<relative path>
+kernel-lib-pass .. builds libraries for kernel space targets
+kernel-pass .. builds kernel modules
+
+The amount of passes is relatively high and consumes some time.
+But only other way to support all required features is to assemble
+one big toplevel Makefile, which would contain all components
+and targets cross-dependencies.
+
+Drawbacks of designed make system
+ - the system is not as fast as we would like
+ - it lacks Autoconf and configure extensive support for many systems
+ from UNIX to DOS and WINDOWS
+ - it does not contain support for checking existence of target libraries
+ and functionalities as GNU Autoconf
+ - it is heavily dependant on GNU MAKE program. But it would not be big
+ problem, because even many commercial applications distribute GNU
+ MAKE with them to be able to work in non-friendly systems
+ - the key drawback is dependence on recent MAKE version 3.80 and better
+ and even version 3.80 of MAKE has important bug, which has been
+ corrected in newer sources
+
+The last point is critical. I have not noticed it first, because
+I use Slackware-9.2 and it contains latest released version
+of MAKE (version 3.80).
+The problem appears when I have tried to build bigger libraries.
+There is bug in version 3.80, which results in misleading
+error "Virtual memory exhausted". It is known bug with ID 1517
+
+ * long prerequisite inside eval(call()) => vm exhausted, Paul D. Smith
+
+I have optimized some rules to not push memory to the edge,
+but there could be still issues with 3.80 version.
+
+I have downloaded latest MAKE CVS sources. The compilation required
+separate lookup and download for .po files and full Autoheader... cycle.
+I have put together package similar to release. Only ./configure --prefix=...
+and make is required. CVS sources contains version 3.81beta1.
+You can download prepared sources archive from
+ http://paulandlesley.org/make/make-3.81beta1.tar.bz2
+Or you can get our local copy from
+ http://cmp.felk.cvut.cz/~pisa/can/make-3.81beta1.tar.gz
+
+The archive contains even "make" binary build by me, which should work
+on other Linux distributions as well.
+Older version of MAKE (3.79.x released about year 2000) found
+on Mandrake and RedHat are not sufficient and do not support eval feature.
+I do not expect, that Debian would be more up-to-date or contain fixes
+to MAKE vm exhausted bug.
+
+The local CTU archive with our CAN components prepared for inclusion
+into OCERA SF CVS could be found in my "can" directory
+
+ http://cmp.felk.cvut.cz/~pisa/can/ocera-can-031212.tar.gz
+
+The code should build for user-space with new make on most of Linux distros
+when make is updated.
+
+If you want to test compile for RT-Linux targets, line
+
+#RTL_DIR := /home/cvs/ocera/ocera-build/kernel/rtlinux
+
+in "Makefile.rules" has to be activated and updated
+to point RT-Linux directory containing "rtl.mk".
+There is only one library ("ulutrtl") and test utility compiled for RT-Linux
+("can/utils/ulut/ul_rtlchk.c").
+
+The next line ,if enabled, controls compilation in OCERA project tree
+
+#OCERA_DIR := $(shell ( cd -L $(MAKERULES_DIR)/../../.. ; pwd -L ) )
+
+The LinCAN driver has been updated to compile out of source directories.
+
+Please, check, if you could compile CAN package and help us with integration
+into OCERA SF CVS. Send your comments and objections.
+
+The OMK system has been adapted to support actual OCERA configuration process.
+I am not happy with ocera.mk mix of defines and poor two or three rules,
+but OMK is able to overcome that.
+
+The OMK system has integrated rules (default-config) to build default configuration
+file. The file is named "config.omk-default" for the stand-alone compilation.
+The name corresponds to OCERA config + "-default" if OCERA_DIR is defined.
+This file contains statements from all default_CONFIG lines in all Makefile.omk.
+The file should be used for building of own "config.omk" file, or as list
+for all options if Kconfig is used.
+
--- /dev/null
+TOPDIR=..
+
+TARGET_ARCH = -ms
+#TARGET_ARCH = -bh8300-coff -ms
+#TARGET_ARCH = -bh8300-coff -ms -mrelax
+#TARGET_ARCH = -bm68k-coff -m68332
+#TARGET_ARCH = -bm68k-elf -m68332
+#TARGET_ARCH = -bi586-mingw32
+
+TOHIT=$(HOME)/h8300/tohit/tohit -d /dev/ttyS0
+
+BOARD_LAYOUT=id_cpu1
+#BOARD_LAYOUT=edk2638
+
+#CC = gcc
+CC = h8300-coff-gcc
+
+LINK = h8300-coff-ld
+
+OBJCOPY = h8300-coff-objcopy
+
+CFLAGS += $(TARGET_ARCH)
+CFLAGS += -g
+CFLAGS += -O2 -Wall
+
+CFLAGS += -I. -I$(TOPDIR)/include -I$(TOPDIR)/include/h8s -I$(TOPDIR)
+
+
+LDFLAGS += $(TARGET_ARCH)
+#LDFLAGS += -Xlinker -Ttext -Xlinker 0x0FFE400
+LDFLAGS += -nostartfiles
+#LDFLAGS += -nodefaultlibs
+#LDFLAGS += -Xlinker -T -Xlinker h8300s.x
+LDFLAGS += -Xlinker -Map -Xlinker test.map
+LDFLAGS += --relax
+LDFLAGS += -L. -L$(TOPDIR)/lib
+
+BOOT_FN_O = boot_fn.o
+CRT0_O = crt0.o
+
+LCSCRIPTB =
+
+HIT_BAUD = 19200
+#HIT_BAUD = 38400
+#CFLAGS += -DHIT_LOAD_BAUD=$(HIT_BAUD)
+
+#CFLAGS += -v
+#LDFLAGS += -v
+
+######################################################################
+# New rules
+
+.S.o:
+ $(CC) -D__ASSEMBLY__ $(AFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.c.s:
+ $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -S $< -o $@
+
+######################################################################
+
+all : test.bin
+
+dep:
+ $(CC) $(CFLAGS) $(CPPFLAGS) -w -E -M *.c $(MORE_C_FILES) > depend
+
+depend:
+ @touch depend
+
+cleanapps : clean
+
+clean :
+ rm -f *.o
+ rm -f *.bin *.srec
+ rm -f test test-boot test-ram test-flash
+
+boot_fn.o : $(TOPDIR)/lib/boot_fn.o
+ ln -s $< $@
+
+crt0.o : $(TOPDIR)/lib/crt0.o
+ ln -s $< $@
+
+#LDFORBOOT += -Xlinker -Ttext -Xlinker 0xffc000
+#LDFORBOOT += -Xlinker -Tdata -Xlinker 0xffc000
+#LDFORBOOT += -Xlinker -Tbss -Xlinker 0xffc000
+
+test :test.o $(BOOT_FN_O)
+ $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-bload $(LDFORBOOT) $^ -o $@
+
+test-flash :test.o $(BOOT_FN_O) $(CRT0_O)
+ $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-flash $^ -o $@
+
+test-ram :test.o $(BOOT_FN_O) $(CRT0_O)
+ $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-ram $^ -o $@
+
+test-boot :test.o $(BOOT_FN_O) $(CRT0_O)
+ $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-boot $^ -o $@
+
+test.bin : test
+ $(OBJCOPY) --output-target=binary -S test test.bin
+
+load : test.bin
+ $(TOHIT) -B4800 -cB -b128 test.bin /* boot program mode */
+# $(TOHIT) -cB test.bin
+ $(TOHIT) -B$(HIT_BAUD) -u -s0 -l0x400 test.rd
+# $(TOHIT) B 0 test.bin
+
+test1 :
+ ((cd ../boot ; rm *.o ; make ; ) ; rm *.o ; make test-ram; objdump --source test-ram ) 2>&1 | less
+
+load1 : test-ram
+ $(OBJCOPY) --output-target=binary -S test-ram test1.bin
+ $(OBJCOPY) --output-target=srec -S test-ram test1.srec
+ $(TOHIT) -B$(HIT_BAUD) -b32 -s0x200000 test1.bin
+ $(TOHIT) -B$(HIT_BAUD) -u -s0x200000 -l0x1A00 test1.rd
+ $(TOHIT) -B$(HIT_BAUD) -g0x200000
+
+load2 : test-boot
+ $(OBJCOPY) --output-target=binary -S test-boot test2.bin
+ $(TOHIT) -B$(HIT_BAUD) -e -s0x000000 -l0x1600
+ $(TOHIT) -B$(HIT_BAUD) -c1 -b32 -s0x000000 test2.bin
+ $(TOHIT) -B$(HIT_BAUD) -u -s0x000000 -l0x1600 -b32 test2.rd
+
+load3 : test.bin
+ $(TOHIT) -B$(HIT_BAUD) -s0xffc000 -b32 -g0xffc000 test.bin
+
+read_bb :
+ $(TOHIT) -B$(HIT_BAUD) -u -s0xffc000 -l0x400 test.rd
+
+read_st :
+ $(TOHIT) -B$(HIT_BAUD) -u -s0x280000 -l0x1000 -b32 test.rd
+
+read_flash :
+ $(TOHIT) -B$(HIT_BAUD) -u -s0x000000 -l0x2000 test2.rd
+ cmp -l test2.bin test2.rd
+
+flash_prg :
+ $(TOHIT) -B$(HIT_BAUD) -e -s0x010000 -l0x80
+ $(TOHIT) -B$(HIT_BAUD) -c1 -b32 -s0x010000 pat.bin
+ $(TOHIT) -B$(HIT_BAUD) -u -s0x010000 -l0x80 pat.rd
+ cmp -l pat.bin pat.rd
+
+flash_prg1 :
+ $(TOHIT) -B$(HIT_BAUD) -e -s0x007000 -l0x200
+ $(TOHIT) -B$(HIT_BAUD) -c1 -b32 -s0x007000 pat1.bin
+ $(TOHIT) -B$(HIT_BAUD) -u -s0x007000 -l0x200 pat1.rd
+ cmp -l pat1.bin pat1.rd
+
+ram_test :
+ $(TOHIT) -B$(HIT_BAUD) -w 1000 -b32 -s0x200000 pat.bin
+# $(TOHIT) -B$(HIT_BAUD) --break
+ sleep 1
+ $(TOHIT) -B$(HIT_BAUD) -w 1000 -u -s0x200000 -l0x0400 pat.rd
+ cmp -l pat.bin pat.rd
+
+reset :
+ $(TOHIT) -B$(HIT_BAUD) -r
+
+break :
+ $(TOHIT) -B$(HIT_BAUD) -k
+
+goto0 :
+ $(TOHIT) -B$(HIT_BAUD) -g0xffc000
+
+goto1 :
+ $(TOHIT) -B$(HIT_BAUD) -g0x200000
+
+goto2 :
+ $(TOHIT) -B$(HIT_BAUD) -g0x000500
+
+
+-include depend
--- /dev/null
+h8300-coff-gcc -ms -g -O2 -Wall -I. -I../include -I../include/h8s -I.. -ms -c -o test.o test.c
+ln -s ../lib/boot_fn.o boot_fn.o
+h8300-coff-gcc -ms -nostartfiles -Xlinker -Map -Xlinker test.map --relax -L. -L../lib -T id_cpu1.ld-bload test.o boot_fn.o -o test
+h8300-coff-objcopy --output-target=binary -S test test.bin
--- /dev/null
+poznamky
+seyon -modems /dev/ttyS1
+../tohit/tohit -d /dev/ttyS1 -w 10000 -B19200 -s 0x0000 -l 0x0100 -u rd.bin
+make flash_prg -n
+minicom
+make flash_prg
+nedit Makefile
--- /dev/null
+/* procesor H8S/2638 ver 1.1 */
+#include <types.h>
+#include <cpu_def.h>
+#include <h8s2638h.h>
+//#include <periph/chmod_lcd.h>
+//#include <periph/sgm_lcd.h>
+#include <system_def.h>
+#include <string.h>
+
+
+
+#ifdef XRAM_SUPPORT_ENABLED
+#define FULL_XRAM_ADRBUS
+#endif /*XRAM_SUPPORT_ENABLED*/
+#define SMALL_ADRBUS 8
+
+
+#define BOOT_TEST
+#define APPLICATION_START
+
+/*#define USE_FONT_6x8*/
+
+#ifndef HIT_LOAD_BAUD
+ #define HIT_LOAD_BAUD 0
+#endif
+
+/* hack for start of main, should use crt0.o instead */
+__asm__ /*__volatile__*/(
+ ".global _start_hack\n\t"
+ "_start_hack : \n\t"
+ "mov.l #0xffdffe,sp\n\t"
+ "jsr _main\n"
+ "0: bra 0b\n"
+ );
+
+void exit(int status)
+{
+ while(1);
+}
+
+void deb_wr_hex(long hex, short digs);
+
+char data_test[]={'D','A','T','A',0};
+
+ /*
+ *----------------------------------------------------------
+ */
+void deb_wr_hex(long hex, short digs)
+{
+ char c;
+ while(digs--){
+ c=((hex>>(4*digs))&0xf)+'0';
+ if(c>'9') c+='A'-'9'-1;
+ }
+}
+
+static void deb_led_out(char val)
+{
+ if (val&1)
+ *DIO_PJDR |=PJDR_PJ1DRm;
+ else
+ *DIO_PJDR &=~PJDR_PJ1DRm;
+
+ if (val&2)
+ *DIO_PJDR |=PJDR_PJ2DRm;
+ else
+ *DIO_PJDR &=~PJDR_PJ2DRm;
+
+ if (val&4)
+ *DIO_PJDR |=PJDR_PJ3DRm;
+ else
+ *DIO_PJDR &=~PJDR_PJ3DRm;
+}
+
+
+#ifdef BOOT_TEST
+
+#include <boot/boot_fn.h>
+
+char __boot_fn_start;
+char __boot_fn_end;
+
+void RelocatedProgMode(unsigned long where, unsigned baud)
+{
+ void (*ProgMode_ptr)(unsigned baud);
+ unsigned long reloc_offs=where-(unsigned long)&__boot_fn_start;
+ size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
+ ProgMode_ptr=&ProgMode;
+ (__u8*)ProgMode_ptr+=reloc_offs;
+ memcpy((char*)where,&__boot_fn_start,reloc_size);
+ /*deb_wr_hex((long)ProgMode_ptr,8);*/
+ (*ProgMode_ptr)(baud);
+}
+
+
+void boot_test()
+{
+ int i=0;
+
+ /*set power on for SCI0 and SCI1 module*/
+ *SYS_MSTPCRB&=~MSTPCRB_SCI0m;
+ *SYS_MSTPCRB&=~MSTPCRB_SCI1m;
+
+ #if 0
+ SCIInit(HIT_LOAD_BAUD);
+
+ SCISend('B');
+ SCISend('B');
+ SCISend(':');
+
+ #endif
+
+ /* switch off SCI2 module*/
+ *SYS_MSTPCRB|=MSTPCRB_SCI2m;
+
+ *DIO_PADR |= 0x0f;
+ *DIO_PADDR = 0x0f;
+
+ if(!HIT_LOAD_BAUD) {
+ long bauddet;
+ bauddet=SCIAutoBaud();
+ deb_wr_hex(bauddet,4);
+ }
+
+
+ if((__u8*)&__boot_fn_start<(__u8*)0xffb000)
+ RelocatedProgMode(0xffb000,HIT_LOAD_BAUD);
+ else
+ ProgMode(HIT_LOAD_BAUD);
+}
+
+#endif /* BOOT_TEST */
+
+inline int call_address(unsigned long addr)
+{
+ typedef int (*my_call_t)(void);
+ my_call_t my_call=(my_call_t)addr;
+ return my_call();
+}
+
+/*
+ *-----------------------------------------------------------
+ */
+
+
+/* Only for debuging */
+void deb_led_blink() {
+ while(1) {
+ deb_led_out(1);
+ FlWait(1*1000000);
+ deb_led_out(2);
+ FlWait(1*1000000);
+ };
+};
+
+
+int main()
+{
+ //int i, j;// POE-100
+ __u8 *p;
+
+ #if 1 /* registers setup */
+ /* Internal RAM enabled, advanced interrupt mode */
+ /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
+
+ /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
+ /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
+ /* Sideefect - sets Flash software protection */
+
+ /* Enables access to flash control registers */
+ *IIC_SCRX |= SCRX_FLSHEm;
+
+ /* set shaddow registers */
+ DIO_P1DDR_shaddow=0;
+ DIO_P3DDR_shaddow=0;
+
+ *DIO_PJDR=0x00;
+ SHADDOW_REG_SET(DIO_PJDDR,0xee); /* set PJ.1, PJ.2, PJ.3 LED output */
+
+ /* show something on debug leds */
+ deb_led_out(0);
+ FlWait(1*100000);
+
+ SHADDOW_REG_SET(DIO_P1DDR,0x03);
+ SHADDOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
+
+ /* Setup system clock oscilator */
+ /* PLL mode x4, */
+ /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
+ /* PLL mode x2, */
+ /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
+ { const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
+ *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
+ clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
+ }
+ deb_led_out(1);
+ FlWait(1*100000);
+
+ /* No clock disable, immediate change, busmaster high-speed */
+ *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
+// POE-100
+ #if 0
+ /* Setup chipselect outputs CS4 CS5 CS6 */
+ *DIO_P7DR |=1|2|4;
+ SHADDOW_REG_SET(DIO_P7DDR,1|2|4);
+ #else
+ // SHADDOW_REG_SET(DIO_P7DDR,0); not on 2638
+ #endif
+
+ /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
+ // *DIO_PGDR |=2|4|8|0x10; no on 2638
+ #if 0
+ SHADDOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
+ #else
+ // SHADDOW_REG_SET(DIO_PGDDR,2|4); no on 2638
+ #endif
+
+ #if 1
+ /* setup chipselect 0 - FLASH */
+ *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
+ *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
+ //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
+ *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
+
+ /* setup chipselect 1 - XRAM */
+ *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
+ *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
+ *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
+
+ /* setup chipselect 2 - USB */
+ *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
+ *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
+ *BUS_WCRL|=0*WCRL_W21m; /* 0/1 additional wait state */
+
+ /* setup chipselect 3 - KBD */
+ *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
+ *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
+ #endif
+
+ #if 0
+ /* setup chipselect 4 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
+
+ /* setup chipselect 5 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
+
+ /* setup chipselect 6 - KL41 */
+ *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
+ *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
+ #endif
+
+ deb_led_out(2);
+ FlWait(1*100000);
+
+#if 1
+ /* cross cs wait| rd/wr wait | no burst and DRAM */
+ *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
+ /* release | no DMAC buffer | no external wait */
+ *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
+ *DIO_PCDDR=0xff; /* A0-A7 are outputs */
+ #ifndef SMALL_ADRBUS
+ *DIO_PBDDR=0xff; /* A8-A15 are outputs */
+ #endif /*SMALL_ADRBUS*/
+ #ifndef FULL_XRAM_ADRBUS
+ #ifndef SMALL_ADRBUS
+ *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
+ #else /*SMALL_ADRBUS*/
+ *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
+ #endif /*SMALL_ADRBUS*/
+ #endif /* FULL_XRAM_ADRBUS */
+
+ #endif /* registers setup */
+
+ FlWait(1*100000);
+
+ #ifdef FULL_XRAM_ADRBUS
+ /* Setup full 22 address lines */
+ *DIO_PADR|=0x0f;
+ *DIO_PADDR=0x0f; /* A16-A19 are outputs */
+ /* number of address output signals */
+ *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
+ #endif /*FULL_XRAM_ADRBUS*/
+#endif
+
+ /* deb_wr_hex(*SYS_SYSCR,2); */
+
+ p=(__u8*)&deb_wr_hex;
+ if(p>=IRAM_START) p=" IRAM";
+ #ifdef SRAM_START
+ else if(p>=SRAM_START) p=" SRAM";
+ #endif
+ #ifdef XRAM_START
+ else if(p>=XRAM_START) p=" XRAM";
+ #endif
+ else if(p>(__u8*)0x4000l) p=" FLSHU";
+ else p=" FLSHB";
+
+
+ #if 0 /* FLASH timing test */
+ do{
+ deb_led_out(~0);
+ FlWait(1l);
+ deb_led_out(~1);
+ FlWait(2l);
+ deb_led_out(~2);
+ FlWait(10l);
+ deb_led_out(~3);
+ FlWait(20l);
+ }while(1);
+ #endif
+
+ #ifdef APPLICATION_START
+ if(((*FLM_FLMCR1) & FLMCR1_FWEm)==0){
+ if (*((unsigned long *)0x4000)!=0xffffffff){
+ call_address(0x4000);
+ }
+ #ifdef XRAM_SUPPORT_ENABLED
+ if (*((unsigned long *)0x200000)==0xff0055aa){
+ call_address(0x200004);
+ }
+ #endif /*XRAM_SUPPORT_ENABLED*/
+ }
+ #endif /* APPLICATION_START */
+
+ deb_led_out(3);
+ FlWait(1*100000);
+
+ #ifdef BOOT_TEST
+ boot_test();
+ #endif /* BOOT_TEST */
+
+ return 0;
+};
+
+
--- /dev/null
+Archive member included because of file (symbol)
+
+/usr/lib/gcc/h8300-coff/3.4.3/../../../../h8300-coff/lib/h8300s/libc.a(memcpy.o)
+ test.o (_memcpy)
+
+Allocating common symbols
+Common symbol size file
+
+__boot_fn_end 0x1 test.o
+__boot_fn_start 0x1 test.o
+DIO_PJDDR_shaddow 0x1 test.o
+cpu_ref_hz 0x4 test.o
+msec_time 0x4 test.o
+DIO_P3DDR_shaddow 0x1 test.o
+DIO_P1DDR_shaddow 0x1 test.o
+DIO_PFDDR_shaddow 0x1 test.o
+scch_pwrctrl_buf 0x2 test.o
+cpu_sys_hz 0x4 test.o
+PWRCTRL_OUT_shaddow
+ 0x1 test.o
+
+Memory Configuration
+
+Name Origin Length Attributes
+iramvec 0x0000000000000000 0x0000000000000400 w
+flashvec 0x0000000000000000 0x0000000000000400 xr
+iramdtc 0x0000000000000400 0x0000000000000100 w
+flashdtc 0x0000000000000400 0x0000000000000100 xr
+iramlow 0x0000000000000500 0x0000000000000b00 w
+flashbb 0x0000000000000500 0x0000000000001b00 xr
+flashpb1 0x0000000000002000 0x0000000000001000 xr
+flashpb2 0x0000000000003000 0x0000000000001000 xr
+flashusr 0x0000000000004000 0x000000000003c000 xr
+ram 0x0000000000200000 0x0000000000100000 w
+ramstby 0x0000000000610000 0x0000000000008000 w
+iram0 0x0000000000ffb000 0x0000000000002000 w
+bloader 0x0000000000ffc000 0x0000000000002000 w
+iram1 0x0000000000ffe000 0x0000000000000fc0 w
+eight 0x0000000000ffffc0 0x0000000000000040 w
+*default* 0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD test.o
+LOAD boot_fn.o
+LOAD /usr/lib/gcc/h8300-coff/3.4.3/h8300s/libgcc.a
+LOAD /usr/lib/gcc/h8300-coff/3.4.3/../../../../h8300-coff/lib/h8300s/libc.a
+LOAD /usr/lib/gcc/h8300-coff/3.4.3/h8300s/libgcc.a
+ 0x0000000000000000 __flash_base = 0x0
+ 0x0000000000040000 __flash_size = 0x40000
+ 0x0000000000002000 __flashbb_size = 0x2000
+ 0x0000000000001000 __flashpb_size = 0x1000
+ 0x0000000000200000 __ram_base = 0x200000
+ 0x00000000002fffff __ram_end = 0x2fffff
+ 0x0000000000ffb000 __iram0_base = 0xffb000
+ 0x0000000000ffcfff __iram0_end = 0xffcfff
+ 0x0000000000002000 __flashpb_base = (__flash_base + __flashbb_size)
+ 0x0000000000ffcff8 PROVIDE (___stack_top, ((__iram0_end & 0xfffffffffffffffc) - 0x4))
+
+.text 0x0000000000ffc000 0xf24
+ 0x0000000000ffc000 text_start = .
+ crt0*(.text)
+ *(EXCLUDE_FILE(*boot_fn.o) .text)
+ .text 0x0000000000ffc000 0x37e test.o
+ 0x0000000000ffc0c8 _boot_test
+ 0x0000000000ffc152 _deb_led_blink
+ 0x0000000000ffc014 _deb_wr_hex
+ 0x0000000000ffc000 _start_hack
+ 0x0000000000ffc144 _call_address
+ 0x0000000000ffc08a _RelocatedProgMode
+ 0x0000000000ffc00c _exit
+ 0x0000000000ffc17a _main
+ .text 0x0000000000ffc37e 0x2c /usr/lib/gcc/h8300-coff/3.4.3/../../../../h8300-coff/lib/h8300s/libc.a(memcpy.o)
+ 0x0000000000ffc37e _memcpy
+ *(EXCLUDE_FILE(*boot_fn.o) .rodata)
+ *(.strings)
+ 0x0000000000ffc3ac . = ALIGN (0x4)
+ *fill* 0x0000000000ffc3aa 0x2 00
+ 0x0000000000ffc3ac ___boot_fn_start = ALIGN (0x4)
+ *boot_fn.o(.text)
+ .text 0x0000000000ffc3ac 0xb76 boot_fn.o
+ 0x0000000000ffc4b2 _FlTest
+ 0x0000000000ffc720 _FlProgRow
+ 0x0000000000ffc3f8 _wdg_enable
+ 0x0000000000ffca7c _SCIReceive
+ 0x0000000000ffcaec _GetAdr
+ 0x0000000000ffc452 _FlAdr2Blk
+ 0x0000000000ffc6c0 _FlProgPulse
+ 0x0000000000ffc3ac _FlWait
+ 0x0000000000ffcc38 _Call
+ 0x0000000000ffc426 _wdg_disable
+ 0x0000000000ffc516 _FlErase
+ 0x0000000000ffc43c _wdg_clear
+ 0x0000000000ffc962 _FlPrepBlk
+ 0x0000000000ffc9c6 _SCIInit
+ 0x0000000000ffcb7e _SCIAutoBaud
+ 0x0000000000ffca3c _SCISend
+ 0x0000000000ffcc46 _ProgMode
+ *boot_fn.o(.rodata)
+ 0x0000000000ffcf24 . = ALIGN (0x4)
+ *fill* 0x0000000000ffcf22 0x2 00
+ 0x0000000000ffcf24 ___boot_fn_end = ALIGN (0x4)
+ 0x0000000000ffcf24 . = ALIGN (0x4)
+ 0x0000000000ffcf24 _etext = ALIGN (0x4)
+
+.tors 0x0000000000ffcf24 0x0
+ 0x0000000000ffcf24 ___ctors = .
+ *(.ctors)
+ 0x0000000000ffcf24 ___ctors_end = .
+ 0x0000000000ffcf24 ___dtors = .
+ *(.dtors)
+ 0x0000000000ffcf24 ___dtors_end = .
+ 0x0000000000ffcf24 . = ALIGN (0x4)
+
+.data 0x0000000000ffcf24 0x10
+ 0x0000000000ffcf24 ___data_lma = .
+ 0x0000000000ffcf24 _data_start = .
+ *(.data)
+ .data 0x0000000000ffcf24 0xe test.o
+ 0x0000000000ffcf24 _data_test
+ 0x0000000000ffcf34 . = ALIGN (0x4)
+ *fill* 0x0000000000ffcf32 0x2 00
+ 0x0000000000ffcf34 _edata = ALIGN (0x4)
+
+.bss 0x0000000000ffcf34 0x1c
+ 0x0000000000ffcf34 . = ALIGN (0x4)
+ 0x0000000000ffcf34 _bss_start = ALIGN (0x4)
+ *(.bss)
+ *(COMMON)
+ COMMON 0x0000000000ffcf34 0x19 test.o
+ 0x0 (size before relaxing)
+ 0x0000000000ffcf36 _DIO_PJDDR_shaddow
+ 0x0000000000ffcf38 _cpu_ref_hz
+ 0x0000000000ffcf3c _msec_time
+ 0x0000000000ffcf40 _DIO_P3DDR_shaddow
+ 0x0000000000ffcf41 _DIO_P1DDR_shaddow
+ 0x0000000000ffcf42 _DIO_PFDDR_shaddow
+ 0x0000000000ffcf44 _scch_pwrctrl_buf
+ 0x0000000000ffcf48 _cpu_sys_hz
+ 0x0000000000ffcf4c _PWRCTRL_OUT_shaddow
+ 0x0000000000ffcf50 . = ALIGN (0x4)
+ *fill* 0x0000000000ffcf4d 0x3 00
+ 0x0000000000ffcf50 _end = ALIGN (0x4)
+
+.stab
+ *(.stab)
+
+.stabstr
+ *(.stabstr)
+OUTPUT(test coff-h8300)
+
+.vectors 0x0000000000000000 0x0
--- /dev/null
+ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ
\ No newline at end of file
--- /dev/null
+S00D000074657374312E7372656326\r
+S2142000007A0700FFCFF87A0500200F7C7A060020BA\r
+S2142000100F7C1FD647167A0400200F8C1AE4470C54\r
+S2142000207BD4598F0D4446F81B5C4AF47A04002092\r
+S2142000300F907A0600200FAC1AE417B419551BF45B\r
+S2142000404B066DE51BF44AFA0FF65E200D4A6DF05E\r
+S2142000505E200BDC40FE00001030400A1B5146FCA0\r
+S2142000600000790100021B7046F254700000000068\r
+S21420007000001000000020000000300000004000BB\r
+S21420008000005000000060000000700000008000AB\r
+S2142000900001000000020000000300000004000031\r
+S2142000A00000000001006DF60FF679025A406BA2A0\r
+S2142000B000FFFF767A0300FFFF74796000070D02C9\r
+S2142000C07942A54069B27940A56069B001006D7695\r
+S2142000D0547001006DF60FF67902A5006BA200FFA2\r
+S2142000E0FF7401006D76547001006DF60FF67902EC\r
+S2142000F05A006BA200FFFF7401006D765470010059\r
+S2142001006DF60FF601006DF40F84190055000100FE\r
+S2142001106D717A11FFFFFF5E010069121FC2430452\r
+S2142001201B00403001006F12000447241AB31073DE\r
+S2142001300A9301006F3200041FC242180B000D0301\r
+S21420014017F30FB210720A9201006F22000446DEE7\r
+S2142001507900FFFF01006D7401006D765470010078\r
+S2142001606DF60FF601106DF4550001006D737A13CD\r
+S214200170FFFFFF027920000B4E040D004C0C790087\r
+S214200180FFFE40347900FFFF402E0D0217F210725A\r
+S2142001900AB201006D24010069251FD44418790293\r
+S2142001A0FFFF69C21A8088025C00FEAC69420B52CF\r
+S2142001B046D20B8440E4190001106D7501006D765F\r
+S2142001C0547001006DF60FF61B9701106DF40D05A7\r
+S2142001D0790200646FE2FFFE7920000B4F08790059\r
+S2142001E0FFFC5800017A0D004C087900FFFB5800F0\r
+S2142001F0016E5C00FF680D00587001646A2A00FFDB\r
+S214200200FFA84D087900FFFF58000154FA406AAA5B\r
+S21420021000FFFFA81A8088015C00FE3C79250007B5\r
+S2142002204E18790200010CDB4F0610128BFF46FA9F\r
+S2142002306AAA00FFFFAA18AA401E18AA6AAA00FFE8\r
+S214200240FFAA7915FFF8790200010CDB4F06101281\r
+S2142002508BFF46FA791500086AAA00FFFFAB6F628B\r
+S214200260FFFE1B026FE2FFFE6A2A00FFFFA958D09E\r
+S21420027000E2790000055C00FE2A6A2A00FFFFA83B\r
+S214200280CA206AAA00FFFFA81A8088645C00FDC8FE\r
+S2142002906A2A00FFFFA8CA026AAA00FFFFA87A00FF\r
+S2142002A0000013885C00FDB06A2A00FFFFA8EAFD64\r
+S2142002B06AAA00FFFFA81A80880A5C00FD9A6A2AAC\r
+S2142002C000FFFFA9EADF6AAA00FFFFA91A80880AB2\r
+S2142002D05C00FD845C00FDFA6A2A00FFFFA94D74CD\r
+S2142002E06A2A00FFFFA8CA086AAA00FFFFA81A8089\r
+S2142002F088065C00FD620D505C00FE620D044734EB\r
+S2142003006A2A00FFFFA8EA406AAA00FFFFA81A8010\r
+S21420031088045C00FD426F63FFFE58E0FF40192210\r
+S2142003206AAA00FFFFA81A8088645C00FD2A79006C\r
+S214200330FFFE402C6A2A00FFFFA8EA406AAA00FFB8\r
+S214200340FFA81A8088045C00FD0E6AAC00FFFFA898\r
+S2142003501900400C18AA6AAA00FFFFA87900FFFD22\r
+S21420036001106D750B9701006D76547001006DF6C7\r
+S2142003700FF601106DF40D05790000045C00FD24D5\r
+S2142003807A0400FFFFA8684ACA1068CA1A80883212\r
+S2142003905C00FCC4684ACA0168CA0D5017F05C00AD\r
+S2142003A0FCB6684AEAFE68CA1A8088055C00FCA883\r
+S2142003B0684AEA4068CA1A8088055C00FC9A5C0095\r
+S2142003C0FD1001106D7501006D76547001006DF6FC\r
+S2142003D00FF67A17FFFFFF6C01106DF401006FE037\r
+S2142003E0FF7C01006FE1FF780F82EA7F47087900E3\r
+S2142003F0FFFA580002086A2A00FFFFA84D08790075\r
+S214200400FFFB580001F801006F64FF7C7905007F30\r
+S214200410684AAAFF586001BE0B041B057925FFFF1A\r
+S21420042046EE01006F64FF787A03FFFFFF800AE341\r
+S2142004307905007F6C4A68BA0B031B050D554CF4F2\r
+S214200440FA406AAA00FFFFA81A8088015C00FC0810\r
+S21420045019006FE0FF746F62FF740B026FE2FF7487\r
+S21420046019336FE3FF7601006F64FF7C7A03FFFF8A\r
+S214200470FF800AE37905007F6C3A68CA1B050B04E7\r
+S2142004800D554CF46F60FF74792000064F067900F6\r
+S21420049000964004790000195C00FED06A2A00FF0E\r
+S2142004A0FFA8CA046AAA00FFFFA81A8088045C0076\r
+S2142004B0FBA601006F64FF7C7A02FFFFFF800AE242\r
+S2142004C001006FE2FF6C7905007E7902FFFF69C2AA\r
+S2142004D01A8088025C00FB806D4201006F63FF6C0F\r
+S2142004E069B20B8301006FE3FF6C1B850D554CDA58\r
+S2142004F06A2A00FFFFA8EA406AAA00FFFFA81A801F\r
+S21420050088025C00FB526F60FF74792000064E6202\r
+S21420051001006F64FF7C19550D5217F27A03FFFF16\r
+S214200520FF800AE30AA301006FE3FF70683B010027\r
+S2142005306F60FF780A8268280CB917090C9A168A09\r
+S214200540586000AE1C8B4708790200016FE2FF76E8\r
+S214200550148B68CB148901006F63FF7068B90B0594\r
+S2142005600B047925007F4FB0790000075C00FDFC66\r
+S214200570403C19550D5217F27A01FFFFFF800AE121\r
+S2142005800AA1681B01006F60FF780A8268281C8B0E\r
+S2142005904708790200016FE2FF76170B0CBA168A1D\r
+S2142005A04650148B689B0B057925007F4FC66F63DA\r
+S2142005B0FF7647286F60FF747920006358F0FE9618\r
+S2142005C018AA6AAA00FFFFA81A8088645C00FA8826\r
+S2142005D07900FFFF40287900FFFC40226E6AFF77F3\r
+S2142005E06AAA00FFFFA81A8088645C00FA6A1900CD\r
+S2142005F0400C18AA6AAA00FFFFA87900FFFD011088\r
+S2142006006D757A170000009401006D765470010015\r
+S2142006106DF60FF61B9701106DF40F8401006FE145\r
+S214200620FFFC5C00FAD80D0501006F62FFFC0AA4EF\r
+S2142006300FC01B005C00FAC60D040D554D040D00BE\r
+S2142006404C067900FFF8401E1D454E180D505C00E4\r
+S214200650FB0C0D00470A0D505C00FB660D004D0696\r
+S2142006600B0540E4190001106D750B9701006D769F\r
+S214200670547001006DF60FF618AA6AAA00FFFF82D2\r
+S21420068018BB0D02EA007922FF0047267A020013E3\r
+S21420069012D053020D20792001FF430A8B01AB03B1\r
+S2142006A0420A111040F00B00111040087900FFFF9D\r
+S2142006B04030E0000C8A8AFF6AAA00FFFF81EB0325\r
+S2142006C06AAB00FFFF8018AA6AAA00FFFF867A009E\r
+S2142006D000004E205C00F980FA306AAA00FFFF82F4\r
+S2142006E0190001006D76547001006DF60FF679033F\r
+S2142006F0C3506A2A00FFFF844D181B036A2A00FF96\r
+S214200700FF844D040D3346F20D3346067900FFFF75\r
+S21420071040106AA800FFFF83FA7F6AAA00FFFF84C2\r
+S214200720190001006D76547001006DF60FF60D115C\r
+S2142007304728400E1B017921FFFF47140D32EA306F\r
+S214200740460E6A2A00FFFF840CAB1753736B47E4F0\r
+S2142007500D11461A7900FFFF40386A2A00FFFF84F1\r
+S2142007600CAB1753736B46060D32EA3047EC6A2AF9\r
+S21420077000FFFF85688AFABE6AAA00FFFF84EB3076\r
+S214200780470EFACE6AAA00FFFF847900FFFE4002D9\r
+S214200790190001006D76547001006DF60FF61B9758\r
+S2142007A001006DF419110FE01B005C00FF7A6E6CDF\r
+S2142007B0FFFF0CC418CC0D4C194419110FE01B0078\r
+S2142007C05C00FF641AA26E6AFFFF642C19110FE00A\r
+S2142007D01B005C00FF526E6AFFFF14A419110FE085\r
+S2142007E01B005C00FF421AA26E6AFFFF01F0642421\r
+S2142007F00FC00D800C08175017705C00FEEA0FC063\r
+S2142008000D8017705C00FEE00FC011701170117023\r
+S21420081011705C00FED20CC85C00FECC0FC001003C\r
+S2142008206D740B9701006D76547001006DF60FF60F\r
+S21420083001006DF479025A406BA200FFFF76790220\r
+S214200840A5416BA200FFFF74FA616BA200FFFF7444\r
+S2142008506A2A00FFFFB2734A461479035A006BA334\r
+S21420086000FFFF746A2A00FFFFB2734A47F06A2A25\r
+S21420087000FFFFB2734A471479035A006BA300FFA8\r
+S214200880FF746A2A00FFFFB2734A46F019447900C3\r
+S2142008905A006A2B00FFFF75ABF0430A6BA000FFDF\r
+S2142008A0FF74791400F06A2A00FFFFB2734A47E209\r
+S2142008B00CBA175209247902A5006BA200FFFF7418\r
+S2142008C00D4010107910000717F07902000901D0AA\r
+S2142008D05320C0FF5C00FD9A0D4001006D7401009E\r
+S2142008E06D76547001006DF60FF65D0001006D7692\r
+S2142008F0547001006DF60FF67A17FFFFFF6C01109B\r
+S2142009006DF46FE0FF7C47045C00FD666F60FF7C43\r
+S21420091046045C00FF1419110FE07A10FFFFFF7FDA\r
+S2142009205C00FE046E6AFF7FAA55470818885C00A4\r
+S214200930FDB640E2F8AA5C00FDAE19110FE07A1071\r
+S214200940FFFFFF7E5C00FDE06E68FF7E0D0379638F\r
+S21420095000070C8A114A110A79620007DA071D235C\r
+S21420096058600260C8805C00FD7E6E6AFF7EEA07E3\r
+S2142009706EEAFF7EAA024306AA04586001FA5C00CB\r
+S214200980FE1601006FE0FF6C5C00FE0C01006FE0BD\r
+S214200990FF706E6AFF7E01006F63FF6C0CAA464EE6\r
+S2142009A0FA5A6EEAFF770FB51AC48C010F8058707A\r
+S2142009B001C019110FE07A10FFFFFF7F5C00FD6871\r
+S2142009C00D0058D001526E68FF7F68D85C00FD1875\r
+S2142009D00B050FC20B0401006F63FF701FB245D2D8\r
+S2142009E05800018EFAFD6EEAFF77580000BAAA0179\r
+S2142009F0586001061AC40CBCEC1FF85A6EE8FF7744\r
+S214200A001B040FC50B754716F8FF0FE27A12FFFF7F\r
+S214200A10FF8068A80B021B040FC10B7146F40FB5AC\r
+S214200A20ED801AD301006FE3FF781AC48C01010011\r
+S214200A306F62FF70477219110FE07A10FFFFFF7F79\r
+S214200A405C00FCE40D004D9C01006F63FF780AE318\r
+S214200A506E6AFF7F6EBAFF8001006F63FF780B031C\r
+S214200A6001006FE3FF78DB800FB346267A01FFFF95\r
+S214200A70FF800AE10FD05C00F9520D004706F8FF10\r
+S214200A806EE8FF777A15000000801AA201006FE258\r
+S214200A90FF786E68FF7F5C00FC4E0FC20B040100DF\r
+S214200AA06F63FF701FB2458E01006F60FF7858702D\r
+S214200AB000C07A200000007F4224FBFF0F820AE25B\r
+S214200AC07A12FFFFFF8068AB0B0201006F60FF7891\r
+S214200AD00B0001006FE0FF78E8800F8047E87A017E\r
+S214200AE0FFFFFF800AE10FD05C00F8E00D00587091\r
+S214200AF00080FAFF6EEAFF774078AA0446220100BB\r
+S214200B006F61FF700FB05C00FB046EE8FF774662F3\r
+S214200B10FB5A6EEBFF77405AF8FD6EE8FF7740529F\r
+S214200B20FA5A6EEAFF770FB51AC48C0101006F637C\r
+S214200B30FF70473E68586EE8FF765C00FBAA1911E6\r
+S214200B400FE07A10FFFFFF7F5C00FBDC0D004DC836\r
+S214200B506E6AFF7F6E6BFF761CBA4706F8FF6EE85C\r
+S214200B60FF770B050FC20B0401006F63FF701FB2E7\r
+S214200B7045C26E68FF77404EAA03462419110FE03F\r
+S214200B807A10FFFFFF7F5C00FB9E6E68FF7FA80B3E\r
+S214200B90423217505C00F62A0D004624F85A4026AA\r
+S214200BA0AA06460C5C00FBF05C00FD385800FD5C95\r
+S214200BB0AA07460C790000025C00F4E85800FD4CB9\r
+S214200BC0F8FF4002F8FE5C00FB1E5800FD3E0000C9\r
+S214200BD07A0700FFDFFE5E200D4A40FE01006DF61C\r
+S214200BE00FF640FE01006DF60FF61B017921FFFF80\r
+S214200BF046F801006D76547001006DF60FF617501A\r
+S214200C007308470A6A2A00FFFC25CA0240086A2A97\r
+S214200C1000FFFC25EAFD6AAA00FFFC257318470A98\r
+S214200C206A2A00FFFC25CA0440086A2A00FFFC2521\r
+S214200C30EAFB6AAA00FFFC257328470A6A2A00FFF7\r
+S214200C40FC25CA0840086A2A00FFFC25EAF76AAA9B\r
+S214200C5000FFFC2501006D76547001006DF60FF63E\r
+S214200C6001106DF40D150F847A34002000587A1484\r
+S214200C70002008F27A0200200BD07A32002000589A\r
+S214200C807A01002000585E200F4E0D505D40011066\r
+S214200C906D7501006D76547001006DF60FF66A2AA8\r
+S214200CA000FFFDE9EA7F6AAA00FFFDE96A2A00FF45\r
+S214200CB0FDE9EABF6AAA00FFFDE96A2A00FFFDE90E\r
+S214200CC0CA206AAA00FFFDE96A2A00FFFF09CA0FA8\r
+S214200CD06AAA00FFFF09FA0F6AAA00FFFE395E2003\r
+S214200CE0082A7901000417F05E200BE47A0200201F\r
+S214200CF000587A2200FFAFFF420E19117A0000FF3B\r
+S214200D00B0005E200C5A400619005E2008F2010052\r
+S214200D106D76547001006DF60FF65D0001006D765D\r
+S214200D20547001006DF60FF6F8015E200BF87A007D\r
+S214200D30000F42405E200058F8025E200BF87A0032\r
+S214200D40000F42405E20005840DE01006DF60FF690\r
+S214200D507A17FFFFFFF401106DF46A2A00FFFDB436\r
+S214200D60CA086AAA00FFFDB418CC6AAC00200F9D02\r
+S214200D706AAC00200F9C6AAC00FFFC256A2A002083\r
+S214200D800F92CAEE6AAA00200F926AAA00FFFC21E0\r
+S214200D9018885E200BF87A00000186A05E20005896\r
+S214200DA06A2A00200F9DCA036AAA00200F9D6AAAFD\r
+S214200DB000FFFE306A2A00200F9CCA096AAA00207B\r
+S214200DC00F9C6AAA00FFFE321AA28A097A01002026\r
+S214200DD00F810FE07A10FFFFFFF45E200F4EFD021A\r
+S214200DE06AAD00FFFDECF8015E200BF87A000001EA\r
+S214200DF086A05E200058FA086AAA00FFFDE66A2A46\r
+S214200E0000FFFED0EAFE6AAA00FFFED06A2A00FF94\r
+S214200E10FED1EAFE6AAA00FFFED16A2A00FFFED3B0\r
+S214200E20EAFC6AAA00FFFED36A2A00FFFED0EAFD8B\r
+S214200E306AAA00FFFED06A2A00FFFED1EAFD6AAA4F\r
+S214200E4000FFFED16A2A00FFFED3EAF36AAA00FF5B\r
+S214200E50FED36A2A00FFFED0CA046AAA00FFFED08C\r
+S214200E606A2A00FFFED1CA046AAA00FFFED16A2AB7\r
+S214200E7000FFFED3EACF6AAA00FFFED36A2A00FF4D\r
+S214200E80FED36AAA00FFFED36A2A00FFFED0CA0855\r
+S214200E906AAA00FFFED06A2A00FFFED1CA086AAA04\r
+S214200EA000FFFED16A2A00FFFED3CAC06AAA00FF4E\r
+S214200EB0FED30CD85E200BF87A00000186A05E20B8\r
+S214200EC000586AAC00FFFED46AAC00FFFED5FAFFDD\r
+S214200ED06AAA00FFFE3B7A00000186A05E2000582A\r
+S214200EE06A2A00FFFF09CA0F6AAA00FFFF09FA0F45\r
+S214200EF06AAA00FFFE398AFF6AAA00FFFDEB6A2A6B\r
+S214200F0000FFFFA84D2201006B0240000B72470431\r
+S214200F105E00400001006B22002000007A22FF00C5\r
+S214200F2055AA46045E200004F8035E200BF87A00DB\r
+S214200F30000186A05E2000585E200C981900011043\r
+S214200F406D757A170000000C01006D7654700F83C3\r
+S214200F500AA01F8347220AA1148A14BA149A730A75\r
+S214200F60460C1B8169126D821F8346F654701B0146\r
+S210200F70681A6C8A1F8346F65470000036\r
+S214200F7C4441544100000001010202020203000019\r
+S804200000DB\r
--- /dev/null
+
+/*
+ ********************************************** Upraveno pro H8S2638, ale nevim presne jak . . . ********************************************
+*/#include <types.h>
+#include <cpu_def.h>
+#include <h8s2638h.h>
+#include <periph/chmod_lcd.h>
+#include <periph/sgm_lcd.h>
+#include <system_def.h>
+#include <string.h>
+
+#define VYRADIT 0
+
+#ifdef XRAM_SUPPORT_ENABLED
+#define FULL_XRAM_ADRBUS
+#endif /*XRAM_SUPPORT_ENABLED*/
+#define SMALL_ADRBUS 8
+
+
+#define BOOT_TEST
+#define APPLICATION_START
+
+/*#define USE_FONT_6x8*/
+
+#ifndef HIT_LOAD_BAUD
+ #define HIT_LOAD_BAUD 0
+#endif
+/* My own comment
+ User led instaled on port1 pin 93(PO12,P14) and 94(PO13,P15), inverted in CU6
+*/
+
+/* hack for start of main, should use crt0.o instead */
+__asm__ /*__volatile__*/(
+ ".global _start_hack\n\t"
+ "_start_hack : \n\t"
+ "mov.l #0xffdffe,sp\n\t"
+ "jsr _main\n"
+ "0: bra 0b\n"
+ );
+
+void exit(int status)
+{
+ while(1);
+}
+
+void deb_wr_hex(long hex, short digs);
+
+char data_test[]={'D','A','T','A',0};
+
+/*
+ *-----------------------------------------------------------
+ */
+
+//#ifdef KL41_SUPPORT_ENABLED
+#if VYRADIT
+/* Character display on KL41 keyboard */
+
+
+short kl41_lcd_init_ok=0;
+
+void kl41_lcd_wait()
+{
+ long i;
+ for(i=0;i<30000;i++)
+ __memory_barrier();
+}
+
+void kl41_lcd_nbusy()
+{ int i;
+ /* for(i=0;i<100;i++)
+ __memory_barrier(); */
+ i=10000;
+ while(*KL41_LCD_STAT&CHMOD_LCD_BF)
+ if(!i--) {kl41_lcd_init_ok=-1; break;};
+}
+
+void kl41_lcd_wrcmd(short cmd)
+{
+ if(!kl41_lcd_init_ok) return;
+ kl41_lcd_nbusy();
+ *KL41_LCD_INST=cmd;
+}
+
+void kl41_lcd_wrchr(short chr)
+{
+ if(!kl41_lcd_init_ok) return;
+ kl41_lcABW1md_nbusy();
+ *KL41_LCD_WDATA=chr;
+}
+
+void kl41_lcd_wrstr(char *s)
+{
+ if(!kl41_lcd_init_ok) return;
+ while(*s)
+ {
+ kl41_lcd_nbusy();
+ *KL41_LCD_WDATA=*(s++);
+ }
+}
+
+int kl41_lcd_init()
+{
+ kl41_lcd_init_ok=0;
+ *KL41_LCD_INST=CHMOD_LCD_MOD;
+ kl41_lcd_wait();
+ *KL41_LCD_INST=CHMOD_LCD_MOD;
+ kl41_lcd_wait();
+ *KL41_LCD_INST=CHMOD_LCD_CLR;
+ kl41_lcd_wait();
+ if(*KL41_LCD_STAT!=0) return -1;
+ kl41_lcd_wait();
+ *KL41_LCD_WDATA=0x55;
+ kl41_lcd_wait();
+ *KL41_LCD_WDATA=0xAA;
+ kl41_lcd_wait();
+ *KL41_LCD_INST=CHMOD_LCD_HOME;
+ kl41_lcd_wait();
+ if(*KL41_LCD_RDATA!=0x55) return -2;
+ kl41_lcd_waiABW1mt();
+ if(*KL41_LCD_RDATA!=0xAA) return -3;
+ kl41_lcd_init_ok=1;
+ kl41_lcd_wrcmd(CHMOD_LCD_CLR);
+ kl41_lcd_wrcmd(CHMOD_LCD_NROL);
+ kl41_lcd_wrcmd(CHMOD_LCD_DON|CHMOD_LCD_CON);
+ kl41_lcd_wrcmd(CHMOD_LCD_NSH);
+ kl41_lcd_wrcmd(CHMOD_LCD_CLR);
+ if(kl41_lcd_init_ok!=1)
+ { kl41_lcd_init_ok=0; return -4;}
+ return 0;
+}
+
+#endif /*KL41_SUPPORT_ENABLED*/
+
+/*
+ *-----------------------------------------------------------
+ */
+
+//#ifdef SGM_SUPPORT_ENABLED
+#if VYRADIT
+/* Small graphic module */
+
+__u32 sgm_lcd_delaycnt=0;
+__u16 sgm_lcd_text_hadr=0x800;
+__u16 sgm_lcd_graph_cols=8*30;
+#ifdef USE_FONT_6x8
+__u16 sgm_lcd_text_cols=40;
+#else /* USE_FONT_6x8 */
+__u16 sgm_lcd_text_cols=30;
+#endif /* USE_FONT_6x8 */
+
+
+short sgm_lcd_init_ok=0;
+
+void sgm_lcd_wait()
+{
+ long i;
+ for(i=0;i<40000;i++)
+ __memory_barrier();
+}
+
+void sgm_lcd_rf_cmd()
+{ int i;
+ i=10000;
+ while(~(*SGM_LCD_STAT)&(SGM_LCD_RF_CMD|SGM_LCD_RF_DATA))
+ if(!i--) {sgm_lcd_init_ok=-1; break;};
+}
+
+void sgm_lcd_rf_x(int mask)
+{ int i;
+ i=10000;
+ while(~(*SGM_LCD_STAT)&mask)
+ if(!i--) {sgm_lcd_init_ok=-1; break;};
+}
+Documents/
+void sgm_lcd_cmd_d0(int cmd)
+{
+ if(!sgm_lcd_init_ok) return;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_CMD=cmd;
+}
+
+void sgm_lcd_cmd_d1(int cmd, int data1)
+{
+ if(!sgm_lcd_init_ok) return;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_DATA=data1;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_CMD=cmd;
+}
+
+void sgm_lcd_cmd_d2(int cmd, int data1, int data2)
+{
+ if(!sgm_lcd_init_ok) return;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_DATA=data1;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_DATA=data2;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_CMD=cmd;
+}
+
+int sgm_lcd_cmd_rd(int cmd)
+{
+ if(!sgm_lcd_init_ok) return -1;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_CMD=cmd;
+ sgm_lcd_rf_cmd();
+ return (__u8)*SGM_LCD_DATA;
+}
+
+void sgm_lcd_cmd_adr(int cmd, int data)
+{
+ if(!sgm_lcd_init_ok) return;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_DATA=data;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_DATA=data>>8;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_CMD=cmd;
+}
+
+void sgm_lcd_wrchr(short chr)
+{
+ if(!sgm_lcd_init_ok) return;
+ sgm_lcd_cmd_d1(SGM_LCD_WR_INC,chr-0x20);
+}
+
+void sgm_lcd_wrstr(char *s)
+{
+ if(!sgm_lcd_init_ok) return;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_CMD=SGM_LCD_A_WR;
+ while(1)
+ {
+ sgm_lcd_rf_x(SGM_LCD_RF_AWR);
+ if(!*s){
+ *SGM_LCD_CMD=SGM_LCD_A_RES;
+ break;
+ }
+ *SGM_LCD_DATA=*(s++)-0x20;
+ }
+}
+
+void sgm_lcd_fill_chr(int dup, char chr)
+{
+ if(!sgm_lcd_init_ok) return;
+ sgm_lcd_rf_cmd();
+ *SGM_LCD_CMD=SGM_LCD_A_WR;
+ while(1)
+ {
+ #if 0
+ sgm_lcd_rf_x(SGM_LCD_RF_AWR);
+ #else
+ { int i=1000;
+ while((~(*SGM_LCD_STAT)&SGM_LCD_RF_AWR)&&i--);
+ sgm_lcd_delaycnt+=1000-i;
+ }
+ #endif
+ if(!dup--){
+ *SGM_LCD_CMD=SGM_LCD_A_RES;
+ break;
+ }
+ *SGM_LCD_DATA=chr;
+ }
+}
+
+void sgm_lcd_gotoxy(short x, short y)
+{
+ short adr;
+ adr=sgm_lcd_text_hadr+y*sgm_lcd_text_cols+x;
+ sgm_lcd_cmd_adr(SGM_LCD_S_ADP,adr);
+}
+
+int sgm_lcd_init()
+{
+ __u8 c1,c2;
+ sgm_lcd_init_ok=1;
+
+ sgm_lcd_cmd_adr(SGM_LCD_C_THADR,sgm_lcd_text_hadr);
+ sgm_lcd_cmd_d2(SGM_LCD_C_TCOL,sgm_lcd_text_cols,0);
+ sgm_lcd_cmd_adr(SGM_LCD_C_GHADR,0);
+ sgm_lcd_cmd_d2(SGM_LCD_C_GCOL,sgm_lcd_graph_cols>>3,0);
+
+ sgm_lcd_cmd_d0(SGM_LCD_M_ICG|SGM_LCD_M_OR);
+ sgm_lcd_cmd_d0(SGM_LCD_CPAT|3);
+ sgm_lcd_cmd_d0(SGM_LCD_D_CONB|SGM_LCD_D_BOTH);
+
+ sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
+ sgm_lcd_cmd_d1(SGM_LCD_WR_INC,0x5F);
+ sgm_lcd_cmd_d1(SGM_LCD_WR_INC,0xAA);
+ sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
+ c1=sgm_lcd_cmd_rd(SGM_LCD_RD_INC);
+ c2=sgm_lcd_cmd_rd(SGM_LCD_RD_INC);
+ /*deb_wr_hex(c1,2);*/
+ /*deb_wr_hex(c2,2);*/
+ if((c1!=0x5F)||(c2!=0xAA)) {sgm_lcd_init_ok=0;return -1;}
+ sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
+
+ sgm_lcd_init_ok=1;
+ return 0;
+}
+#endif /*SGM_SUPPORT_ENABLED*/
+
+/*
+ *-----------------------------------------------------------
+ */
+
+
+void deb_wr_hex(long hex, short digs)
+{
+ char c;
+ while(digs--){
+ c=((hex>>(4*digs))&0xf)+'0';
+ if(c>'9') c+='A'-'9'-1;
+ //#ifdef SGM_SUPPORT_ENABLED
+ #if VYRADIT
+ sgm_lcd_wrchr(c);
+ #elif VYRADIT
+ //defined(KL41_SUPPORT_ENABLED)
+ kl41_lcd_wrchr(c);
+ #endif
+ }
+}
+
+static void deb_led_out(char val)
+{
+ #if 0
+ *DIO_P1DR &= ~0xf;
+ *DIO_P1DR |= ~val & 0xf;
+ #else
+ /*2,6,7*/
+ *DIO_P3DR &= ~0xc4;
+ *DIO_P3DR |= ~(val<<5) & 0xc0;
+ if(!(val&1))
+ *DIO_P3DR |= 4;
+ #endif
+}
+
+
+
+#ifdef BOOT_TEST
+
+#include <boot/boot_fn.h>
+
+char __boot_fn_start;
+char __boot_fn_end;
+
+void RelocatedProgMode(unsigned long where, unsigned baud)
+{
+ void (*ProgMode_ptr)(unsigned baud);
+ unsigned long reloc_offs=where-(unsigned long)&__boot_fn_start;
+ size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
+ ProgMode_ptr=&ProgMode;
+ (__u8*)ProgMode_ptr+=reloc_offs;
+ memcpy((char*)where,&__boot_fn_start,reloc_size);
+ /*deb_wr_hex((long)ProgMode_ptr,8);*/
+ (*ProgMode_ptr)(baud);
+}
+
+void boot_test()
+{
+ int i=0;
+
+ /* Disable SCI 2 */
+ /* Off TxD2 on Port PA.1 */
+ /* Off RxD2 on Port PA.2 */
+ *SCI_SCR2=0;
+ #ifndef FULL_XRAM_ADRBUS
+ *DIO_PADR|=0x06;
+ *DIO_PADDR=0x01;
+ #endif /* FULL_XRAM_ADRBUS */
+
+ #if 0
+ /*set power on for SCI4 module*/
+ *SYS_MSTPCRC&=~MSTPCRC_SCI4m;
+
+ /* Output TxD4 on Port P3.7, TxD0 on P3.0 */
+ /* RTS4 on Port P3.2 */
+ /* Input RxD4 on Port P3.6, RxD0 on P3.1 */
+ /* CTS4 on Port P3.3 */
+ *DIO_P3DR|=0xc5;
+ SHADDOW_REG_SET(DIO_P3DDR,0x85);
+
+ #ifdef KL41_SUPPORT_ENABLED
+ kl41_lcd_wrstr("BB:");
+ #endif /*KL41_SUPPORT_ENABLED*/
+
+ SCIInit(HIT_LOAD_BAUD);
+
+ SCISend('B');
+ SCISend('B');
+ SCISend(':');
+
+ #else
+ /*set power on for SCI2 module*/
+ *SYS_MSTPCRB&=~MSTPCRB_SCI2m;
+
+ /* Output TxD2 on Port PA.1 */
+ /* Input RxD2 on Port PA.2 */
+ *DIO_PADR |= 0x6;
+ *DIO_PADDR = 0x2;
+ #endif
+
+ //#ifdef SGM_SUPPORT_ENABLED
+ #if VYRADIT
+ while(i<160-2){
+ /* SCISend('A'); */
+ sgm_lcd_gotoxy(0,7);
+ deb_wr_hex(i++,4);
+ deb_wr_hex(sgm_lcd_delaycnt,8);
+ sgm_lcd_delaycnt=0;
+ /*FlWait(1000000);*/
+ kl41_lcd_wrstr(".");
+ /*SGM clr test*/
+ sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
+ sgm_lcd_fill_chr(240/8*64,1<<(i&7));
+ }
+ #endif /*SGM_SUPPORT_ENABLED*/
+
+ if(!HIT_LOAD_BAUD) {
+ long bauddet;
+ //#ifdef SGM_SUPPORT_ENABLED
+ #if VYRADIT
+ sgm_lcd_gotoxy(0,2);
+ sgm_lcd_wrstr("AB:");
+ #endif /*SGM_SUPPORT_ENABLED*/
+ bauddet=SCIAutoBaud();
+ deb_wr_hex(bauddet,4);
+ }
+
+ //#ifdef SGM_SUPPORT_ENABLED
+ #if VYRADIT
+ sgm_lcd_gotoxy(0,4);
+ sgm_lcd_wrstr("BB:");
+ sgm_lcd_wrstr(" BRR=");deb_wr_hex(*SCI_BRR4,2);
+ sgm_lcd_wrstr(" SMR=");deb_wr_hex(*SCI_SMR4,2);
+
+ sgm_lcd_gotoxy(0,0);
+ #endif /*SGM_SUPPORT_ENABLED*/
+
+ if((__u8*)&__boot_fn_start<(__u8*)0xffb000)
+ RelocatedProgMode(0xffb000,HIT_LOAD_BAUD);
+ else
+ ProgMode(HIT_LOAD_BAUD);
+}
+
+#endif /* BOOT_TEST */
+
+inline int call_address(unsigned long addr)
+{
+ typedef int (*my_call_t)(void);
+ my_call_t my_call=(my_call_t)addr;
+ return my_call();
+}
+
+/*
+ *-----------------------------------------------------------
+ */
+
+
+int main()
+{
+ int i, j;
+ __u8 *p;
+
+ #if 1 /* registers setup */
+ /* Internal RAM enabled, advanced interrupt mode */
+ /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
+
+ /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
+ /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
+ /* Sideefect - sets Flash software protection */
+
+ /* Enables access to flash control registers */
+ *IIC_SCRX |= SCRX_FLSHEm;
+
+ /* set shaddow registers */
+ // DIO_P1DDR_shaddow=0; not used
+ DIO_P3DDR_shaddow=0;
+
+ /* show something on debug leds */
+ deb_led_out(1);
+ #if 0
+ SHADDOW_REG_SET(DIO_P1DDR,0x0f);
+ #else
+ SHADDOW_REG_SET(DIO_P3DDR,0xc4);
+ #endif
+
+ /* Setup system clock oscilator */
+ /* PLL mode x4, */
+ /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
+ /* PLL mode x2, */
+ /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
+ { const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
+ *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
+ clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
+ }
+ /* No clock disable, immediate change, busmaster high-speed */
+ *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
+
+ #if 0
+ /* Setup chipselect outputs CS4 CS5 CS6 */
+ *DIO_P7DR |=1|2|4;
+ SHADDOW_REG_SET(DIO_P7DDR,1|2|4);
+ #else
+ //SHADDOW_REG_SET(DIO_P7DDR,0);
+ #endif
+
+ /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
+ //*DIO_PGDR |=2|4|8|0x10;
+ #if 0
+ SHADDOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
+ #else
+ //SHADDOW_REG_SET(DIO_PGDDR,2|4);
+ #endif
+
+ #if 0
+ /* setup chipselect 0 - FLASH */
+ *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
+ *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
+ *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
+
+ /* setup chipselect 1 - XRAM */
+ *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
+ *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
+ *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
+ #endif
+
+ /* setup chipselect 2 - SGM_LCD */
+ *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
+ *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
+ *BUS_WCRL|=0*WCRL_W21m; /* 0/1 additional wait state */
+
+ /* setup chipselect 3 - SRAM */
+ *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
+ *BUS_WCRL&=~(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
+
+ #if 0
+ /* setup chipselect 4 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
+
+ /* setup chipselect 5 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
+
+ /* setup chipselect 6 - KL41 */
+ *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
+ *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
+ #endif
+
+ /* cross cs wait| rd/wr wait | no burst and DRAM */
+ *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
+ /* release | no DMAC buffer | no external wait */
+ *BUS_BCRL=0*BCRL_WDBEm;
+ *DIO_PCDDR=0xff; /* A0-A7 are outputs */
+ #ifndef SMALL_ADRBUS
+ *DIO_PBDDR=0xff; /* A8-A15 are outputs */
+ #endif /*SMALL_ADRBUS*/
+ #ifndef FULL_XRAM_ADRBUS
+ #ifndef SMALL_ADRBUS
+ *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
+ #else /*SMALL_ADRBUS*/
+ *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
+ #endif /*SMALL_ADRBUS*/
+ #endif /* FULL_XRAM_ADRBUS */
+
+ #endif /* registers setup */
+
+ //#ifdef KL41_SUPPORT_ENABLED
+ #if VYRADIT
+ {
+ *KL41_LED_WR=0x55;
+
+ #if 1
+ if(kl41_lcd_init()<0)
+ deb_led_out(2);
+ else
+ deb_led_out(3);
+ #endif
+
+ kl41_lcd_wrstr("Hello ");
+ kl41_lcd_wrstr(data_test);
+ }
+ #endif /*KL41_SUPPORT_ENABLED*/
+
+ FlWait(1*1000000);
+
+ #ifdef FULL_XRAM_ADRBUS
+ /* Setup full 20 address lines */
+ *DIO_PADR|=0x0f;
+ *DIO_PADDR=0x0f; /* A16-A19 are outputs */
+ /* number of address output signals */
+ *SYS_PFCR=__val2mfld(PFCR_AExm,20-8);
+ #endif /*FULL_XRAM_ADRBUS*/
+
+ /* deb_wr_hex(*SYS_SYSCR,2); */
+
+ //#ifdef SGM_SUPPORT_ENABLED
+ #if VYRADIT
+ sgm_lcd_init();
+ sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
+ sgm_lcd_fill_chr(0x1000,0);
+ sgm_lcd_cmd_adr(SGM_LCD_S_ADP,0);
+ sgm_lcd_fill_chr(60,0xff);
+
+ sgm_lcd_gotoxy(0,1);
+ sgm_lcd_wrstr("Hello SGM ");
+ sgm_lcd_wrstr(data_test);
+ sgm_lcd_gotoxy(10,3);
+ sgm_lcd_wrstr("I'am alive");
+
+ //#ifdef KL41_SUPPORT_ENABLED
+ #if VYRADIT
+ if(sgm_lcd_init_ok<0) kl41_lcd_wrstr(" SGM-Error");
+ else{
+ if(sgm_lcd_init_ok==0) kl41_lcd_wrstr(" SGM-None");
+ else kl41_lcd_wrstr(" SGM-OK");
+ }
+ #endif /*KL41_SUPPORT_ENABLED*/
+ #endif /*SGM_SUPPORT_ENABLED*/
+
+ p=(__u8*)&deb_wr_hex;
+ if(p>=IRAM_START) p=" IRAM";
+ #ifdef SRAM_START
+ else if(p>=SRAM_START) p=" SRAM";
+ #endif
+ #ifdef XRAM_START
+ else if(p>=XRAM_START) p=" XRAM";
+ #endif
+ else if(p>(__u8*)0x4000l) p=" FLSHU";
+ else p=" FLSHB";
+
+ //#ifdef KL41_SUPPORT_ENABLED
+ #if VYRADIT
+ kl41_lcd_wrstr(p);
+ #endif /*KL41_SUPPORT_ENABLED*/
+ //#ifdef SGM_SUPPORT_ENABLED
+ #if VYRADIT
+ sgm_lcd_wrstr(p);
+ #endif /*SGM_SUPPORT_ENABLED*/
+
+ #if 0 /* FLASH timing test */
+ do{
+ deb_led_out(~0);
+ FlWait(1l);
+ deb_led_out(~1);
+ FlWait(2l);
+ deb_led_out(~2);
+ FlWait(10l);
+ deb_led_out(~3);
+ FlWait(20l);
+ }while(1);
+ #endif /* APPLICATION_START */
+
+ #ifdef APPLICATION_START
+ if(((*FLM_FLMCR1) & FLMCR1_FWEm)==0){
+ if (*((unsigned long *)0x4000)!=0xffffffff){
+ call_address(0x4000);
+ }
+ #ifdef XRAM_SUPPORT_ENABLED
+ if (*((unsigned long *)0x200000)==0xff0055aa){
+ call_address(0x200004);
+ }
+ #endif /*XRAM_SUPPORT_ENABLED*/
+ }
+ #endif /* APPLICATION_START */
+
+ #ifdef BOOT_TEST
+ boot_test();
+ #endif /* BOOT_TEST */
+
+ //#ifdef KL41_SUPPORT_ENABLED
+ #if VYRADIT
+ {
+ for(j=0xffff;j--;){
+ for(i=0xffff;i--;){
+ *KL41_LED_WR=0xcccc>>((j>>3)&7);
+ }
+ }
+ }
+
+ *KL41_LED_WR=0xAA;
+ #endif /*KL41_SUPPORT_ENABLED*/
+
+ return 0;
+};
+
+
--- /dev/null
+all: tohit rs232_lt
+
+#all: tohit hiterm
+
+CFLAGS=-O2 -Wall
+
+tohit: tohit.o tohit_fn.o
+
+hiterm: hiterm.o tohit_fn.o
+
+rs232_lt: rs232_lt.o tohit_fn.o
+ $(CC) $(LDFLAGS) $(CFLAGS) -lncurses -o $@ $^
+
+clean:
+ rm -f *.o
--- /dev/null
+
+TOHIT
+=====
+
+Program uploader for Hitachi H8S/263x processor.
--- /dev/null
+/* Copyright (C) 1992, 1993, 1996, 1997, 1998 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Library General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Library General Public License for more details.
+
+ You should have received a copy of the GNU Library General Public
+ License along with the GNU C Library; see the file COPYING.LIB. If not,
+ write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#include <termios.h>
+#include <errno.h>
+#include <stddef.h>
+
+struct speed_struct
+{
+ speed_t value;
+ speed_t internal;
+};
+
+static const struct speed_struct speeds[] =
+ {
+#ifdef B0
+ { 0, B0 },
+#endif
+#ifdef B50
+ { 50, B50 },
+#endif
+#ifdef B75
+ { 75, B75 },
+#endif
+#ifdef B110
+ { 110, B110 },
+#endif
+#ifdef B134
+ { 134, B134 },
+#endif
+#ifdef B150
+ { 150, B150 },
+#endif
+#ifdef B200
+ { 200, B200 },
+#endif
+#ifdef B300
+ { 300, B300 },
+#endif
+#ifdef B600
+ { 600, B600 },
+#endif
+#ifdef B1200
+ { 1200, B1200 },
+#endif
+#ifdef B1200
+ { 1200, B1200 },
+#endif
+#ifdef B1800
+ { 1800, B1800 },
+#endif
+#ifdef B2400
+ { 2400, B2400 },
+#endif
+#ifdef B4800
+ { 4800, B4800 },
+#endif
+#ifdef B9600
+ { 9600, B9600 },
+#endif
+#ifdef B19200
+ { 19200, B19200 },
+#endif
+#ifdef B38400
+ { 38400, B38400 },
+#endif
+#ifdef B57600
+ { 57600, B57600 },
+#endif
+#ifdef B76800
+ { 76800, B76800 },
+#endif
+#ifdef B115200
+ { 115200, B115200 },
+#endif
+#ifdef B153600
+ { 153600, B153600 },
+#endif
+#ifdef B230400
+ { 230400, B230400 },
+#endif
+#ifdef B307200
+ { 307200, B307200 },
+#endif
+#ifdef B460800
+ { 460800, B460800 },
+#endif
+ };
+
+
+/* Set both the input and output baud rates stored in *TERMIOS_P to SPEED. */
+int
+cfsetspeed (struct termios *termios_p, speed_t speed)
+{
+ size_t cnt;
+
+ for (cnt = 0; cnt < sizeof (speeds) / sizeof (speeds[0]); ++cnt)
+ if (speed == speeds[cnt].internal)
+ {
+ cfsetispeed (termios_p, speed);
+ cfsetospeed (termios_p, speed);
+ return 0;
+ }
+ else if (speed == speeds[cnt].value)
+ {
+ cfsetispeed (termios_p, speeds[cnt].internal);
+ cfsetospeed (termios_p, speeds[cnt].internal);
+ return 0;
+ }
+
+ __set_errno (EINVAL);
+
+ return -1;
+}
--- /dev/null
+#include <stdio.h>
+#include <string.h>
+#include <termios.h>
+#include <stdlib.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <asm/types.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <sys/stat.h>
+
+
+#define DEBUG 0
+
+int cnt;
+char * arg[10];
+
+unsigned char * bbuf=NULL;
+long Len=0;
+
+int tohit(int argc, char **argv);
+
+void SaveBB(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+ int fd1;
+
+ if (!bbuf){
+ printf("Error bufer empty\n");
+ return;
+ }
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+ i=0;
+ while(*buf && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ if ((fd1 = open(str, O_CREAT | O_WRONLY, 0644)) == -1) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ i=write(fd1,bbuf,Len);
+ if(i<0){
+ printf("%s\n",strerror(errno));
+ }
+ else if(i!=Len){
+ printf("Error writing %s\n",str);
+ }
+ close(fd1);
+ printf("Write %d bytes\n",i);
+}
+
+void SaveBA(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+ FILE * F;
+ __s16 * x;
+
+ if (!bbuf){
+ printf("Error bufer empty\n");
+ return;
+ }
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+ i=0;
+ while(*buf && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ F=fopen(str,"w");
+ if (F==0) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ x=(__s16 *)bbuf;
+ for(i=0;i<(Len/2);i++){
+ fprintf(F,"%07d\n",*x);
+ x++;
+ }
+ fclose(F);
+ printf("Write %d num\n",i);
+}
+
+
+void Load(int fd,char *buf,int len,int fl)
+{
+ int i;
+ int j;
+ char str[100];
+ char a1[]="7";
+ char * a[3];
+
+ a[0]=NULL;
+ a[1]=a1;
+ a[2]=a1;
+
+ buf[len]=' ';
+ buf[len+1]=0;
+ buf+=5;
+ if(*buf!=' ') buf++;
+ i=1;
+ arg[0]=NULL;
+ j=0;
+ while(*buf){
+ if(j>0 && *buf==' '){
+ str[j]=0;
+ j++;
+ if(i<cnt) free(arg[i]);
+ arg[i]=(char *)malloc(j);
+ do {
+ j--;
+ arg[i][j]=str[j];
+ }while(j);
+ i++;
+ if(i==10) i--;
+ }
+ else{
+ if(*buf!=' ' && *buf!=10 && *buf!=13) str[j++]=*buf;
+ if (j==100) j--;
+ }
+ buf++;
+ }
+ if(i>1){
+ cnt=i;
+ }
+ for (i=0;i<cnt;i++){
+ printf(" A%d : %s\n",i,arg[i]);
+ }
+ if(cnt){
+ if(fl==0){
+ write(fd,"LOAD\n",5);
+ usleep(100000);
+ read(fd,str,100);
+ }
+ tohit(cnt,arg);
+ tohit(3,a);
+ usleep(200000);
+ read(fd,str,100);
+ }
+ else{
+ printf("Bad Parametr\n");
+ }
+}
+
+char GName[100];
+char GStart[20];
+char GLen[20];
+int GChan;
+int GSt=0;
+int Cb=0;
+
+void Get(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+ GChan=strtol(str,NULL,10);
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GStart[i++]=*buf++;
+ GStart[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GLen[i++]=*buf++;
+ GLen[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GName[i++]=*buf++;
+ GName[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ Cb=1;
+ GSt=0;
+ sprintf(str,"GET 0,%s,%s\n",GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void GetM(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+ GChan=strtol(str,NULL,10);
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GStart[i++]=*buf++;
+ GStart[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GLen[i++]=*buf++;
+ GLen[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GName[i++]=*buf++;
+ GName[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ Cb=2;
+ GSt=0;
+ sprintf(str,"GET 0,%s,%s\n",GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void GetCB(int fd)
+{
+ char str[100];
+ int i;
+ FILE * F;
+ __s16 * x;
+
+ sprintf(str,"%s.%03d",GName,GSt);
+
+ F=fopen(str,"w");
+ if (F==0) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ x=(__s16 *)bbuf;
+ for(i=0;i<(Len/2);i++){
+ fprintf(F,"%07d\n",*x);
+ x++;
+ }
+ fclose(F);
+ printf("Write %d num\n",i);
+ GSt++;
+ if(GSt>GChan-1){
+ Cb=0;
+ GSt=0;
+ return;
+ }
+ sprintf(str,"GET %d,%s,%s\n",GSt,GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void GetMCB(int fd)
+{
+ char str[100];
+ int i;
+ FILE * F;
+ __s16 * x;
+
+ sprintf(str,"%s.dat",GName);
+ if(GSt==0)F=fopen(str,"w");
+ else F=fopen(str,"a");
+ if (F==0) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ x=(__s16 *)bbuf;
+ for(i=0;i<(Len/2);i++){
+ if(i==(Len/2)-1) fprintf(F,"%07d\n",*x);
+ else fprintf(F,"%07d ",*x);
+ x++;
+ }
+ fclose(F);
+// printf("Write %d num\n",i);
+ GSt++;
+ if(GSt>GChan-1){
+ printf("Write %d chanels\n",GSt);
+ Cb=0;
+ GSt=0;
+ return;
+ }
+ sprintf(str,"GET %d,%s,%s\n",GSt,GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void LCmd(int fd,char* buf,int len)
+{
+ buf[len]=0;
+ if((strstr(buf,"!loadb")==buf) || (strstr(buf,"!LOADB")==buf))
+ Load(fd,buf,len,1);
+ else if((strstr(buf,"!load")==buf) || (strstr(buf,"!LOAD")==buf))
+ Load(fd,buf,len,0);
+ else if((strstr(buf,"!savebuf")==buf) || (strstr(buf,"!SAVEBUF")==buf))
+ SaveBB(fd,buf,len);
+ else if((strstr(buf,"!saveasc")==buf) || (strstr(buf,"!SAVEASC")==buf))
+ SaveBA(fd,buf,len);
+ else if((strstr(buf,"!getm")==buf) || (strstr(buf,"!GETM")==buf))
+ Get(fd,buf,len);
+ else if((strstr(buf,"!get")==buf) || (strstr(buf,"!GET")==buf))
+ GetM(fd,buf,len);
+ else printf ("Unknown comand : %s\n",buf);
+}
+
+void CB(int fd)
+{
+ if(Cb==1) GetCB(fd);
+ if(Cb==2) GetMCB(fd);
+}
+
+
+int main(int argc, char **argv)
+{
+ int ii;
+ int oi;
+ int i;
+ unsigned char ibuf[500];
+ unsigned char obuf[500];
+ unsigned char * sdev="/dev/ttyS1";
+ int fd=-1;
+ long len=0;
+ long dlen=0;
+ unsigned char *x;
+
+ unsigned char * bb;
+
+ cnt=0;
+
+ if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
+ printf("Error openning %s\n",sdev);
+ exit(-1);
+ }
+ rs232_setmode(fd,38800,0,0);
+
+
+ ii=0;
+ oi=0;
+ while(1){
+ if(rs232_test(fd,10000)==1){
+ oi+=read(fd, obuf+oi, 500-oi);
+ if(obuf[oi-1]==0xa || obuf[oi-1]==0xd || oi>400){
+ obuf[oi]=0;
+ if(dlen){
+ if(oi<=dlen){
+ memcpy(bb,obuf,oi);
+ bb+=oi;
+ dlen-=oi;
+ oi=0;
+ }
+ else{
+ memcpy(bb,obuf,dlen);
+ bb+=dlen;
+ x=obuf+dlen;
+ dlen=0;
+ i=0;
+ while(x-obuf<oi){
+ obuf[i++]=*x++;
+ }
+ oi=i;
+ obuf[oi]=0;
+ }
+ if(!dlen) CB(fd);
+ }
+ else {
+ x=strstr(obuf,"061:");
+ if(x){
+ x+=4;
+ sscanf(x,"%ld",&Len);
+ printf("len=%ld\n",Len);
+ len=Len;
+ if(bbuf) free(bbuf);
+ bbuf=(unsigned char *)malloc(len);
+ bb=bbuf;
+ while(*x!=0xa && *x!=0xd && *x) x++;
+ if(*x==0xd || *x==0xa) x++;
+ i=0;
+ while(x-obuf<oi){
+ obuf[i++]=*x++;
+ }
+ oi=i;
+ obuf[oi]=0;
+ }
+ x=strstr(obuf,"062:");
+ if(x){
+ dlen=len;
+ len=0;
+ x+=4;
+ if(oi-(x-obuf)>=dlen){
+ memcpy(bb,x,dlen);
+ bb+=dlen;
+ x+=dlen;
+ dlen=0;
+ i=0;
+ while(x-obuf<oi){
+ obuf[i++]=*x++;
+ }
+ oi=i;
+ obuf[oi]=0;
+ }
+ else{
+ memcpy(bb,x,oi-(x-obuf));
+ bb+=oi-(x-obuf);
+ dlen-=oi-(x-obuf);
+ oi=0;
+ }
+ if(!dlen) CB(fd);
+ }
+ }
+ write(0, obuf, oi);
+ oi=0;
+ }
+ }
+ if(rs232_test(1,10000)==1){
+ ii+=read(1, ibuf+ii, 500-ii);
+ if(ibuf[ii-1]==0xa || ibuf[ii-1]==0xd || ii>400){
+ if(ibuf[0]=='!'){
+ LCmd(fd,ibuf,ii);
+ }
+ else{
+ write(fd, ibuf, ii);
+ }
+ ii=0;
+ }
+ }
+ }
+}
+
--- /dev/null
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <termios.h>
+#include <ncurses.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include "tohit_fn.h"
+
+#define DEBUG 0
+#define HAS_GETOPT_LONG 1
+
+#define MEM_BUF_LEN 0x40000
+
+unsigned char mem_buf[MEM_BUF_LEN];
+
+int rs232_loop_test(char *sdev, int baud, int flowc);
+
+struct termios init_saved_termios;
+
+
+int flowc;
+
+static void
+usage(void)
+{
+ printf("usage: tohit <parameters> <send_file>\n");
+ printf(" -d, --sdev <name> name of RS232 device [%s]\n",tohit_sdev);
+ printf(" -B, --baud <num> RS232 baudrate [%d]\n",tohit_baud);
+ printf(" -f, --flowc-rts flow control\n");
+ printf(" -V, --version show version\n");
+ printf(" -h, --help this usage screen\n");
+}
+
+int main(int argc, char **argv)
+{
+ /* FILE *F; */
+
+ static struct option long_opts[] = {
+ { "sdev", 1, 0, 'd' },
+ { "baud", 1, 0, 'B' },
+ { "flowc-rts",0, 0, 'f' },
+ { "version",0,0, 'V' },
+ { "help", 0, 0, 'h' },
+ { 0, 0, 0, 0}
+ };
+ int opt;
+ int ret;
+
+ tohit_baud=9600;
+
+ #ifndef HAS_GETOPT_LONG
+ while ((opt = getopt(argc, argv, "d:B:fVh")) != EOF)
+ #else
+ while ((opt = getopt_long(argc, argv, "d:B:fVh",
+ &long_opts[0], NULL)) != EOF)
+ #endif
+ switch (opt) {
+ case 'd':
+ tohit_sdev=optarg;
+ break;
+ case 'B':
+ tohit_baud = strtol(optarg,NULL,0);
+ break;
+ case 'f':
+ flowc=1;
+ break;
+ case 'V':
+ fputs("tohit pre alpha\n", stdout);
+ exit(0);
+ case 'h':
+ default:
+ usage();
+ exit(opt == 'h' ? 0 : 1);
+ }
+
+ def_shell_mode();
+ savetty();
+ /*tcgetattr(0, &init_saved_termios);*/
+ initscr(); cbreak(); noecho();
+ nonl(); intrflush(stdscr, FALSE); keypad(stdscr, TRUE);
+ nodelay(stdscr, TRUE);
+
+ ret=rs232_loop_test(tohit_sdev,tohit_baud,flowc);
+
+ endwin();
+
+ return ret;
+}
+
+
+int rs232_loop_test(char *sdev, int baud, int flowc)
+{
+ int fd;
+ int c;
+ unsigned char *pout=NULL, *pin=NULL, uc;
+ int cntout=0,cntin=0, cnt;
+ int i, test_loop_fl=0;
+ int errorcnt=0;
+ int idle;
+ int stopin=0;
+ /* int stopout=0; */
+
+ /* Open RS232 device */
+ if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
+ printf("Error openning %s\n",sdev);
+ return -1;
+ }
+
+ /* Set RS232 device mode and speed */
+ if(rs232_setmode(fd,baud,0,flowc)<0){
+ printf("Error in rs232_setmode\n");
+ return -1;
+ }
+
+/*
+ rs232_sendch(int fd,unsigned char c);
+ rs232_recch(int fd);
+ rs232_test(int fd,int time);
+*/
+
+ mvprintw(/*y*/2,/*x*/2,"Test of RS-232 transfers");
+
+ do{
+ c=getch();
+ idle=(c==ERR);
+
+ switch(c) {
+ case 't' :
+ cnt=20000;
+ if(cnt>MEM_BUF_LEN) cnt=MEM_BUF_LEN;
+ for(i=0;i<cnt;i++)
+ mem_buf[i]=i^(i>>7);
+ test_loop_fl=1;
+ cntout=cntin=cnt;
+ pout=pin=mem_buf;
+ errorcnt=0;
+ mvprintw(/*y*/11,/*x*/0,"Loop test : %s",
+ "Running");
+ mvprintw(/*y*/9,/*x*/0," ");
+ mvprintw(/*y*/10,/*x*/0," ");
+ break;
+ case 's' :
+ stopin=!stopin;
+ break;
+ }
+
+ if(test_loop_fl) {
+ if(cntout)
+ if(write(fd, pout, 1) == 1) {
+ pout++;
+ cntout--;
+ idle=0;
+ }
+ if(cntin&&!stopin)
+ if(read(fd, &uc, 1) == 1) {
+ if(*pin!=uc) {
+ errorcnt++;
+ mvprintw(/*y*/9,/*x*/0,"Diff : %02X != %02X",uc,*pin);
+ mvprintw(/*y*/10,/*x*/0,"Errors : %4d",errorcnt);
+ }
+ pin++;
+ cntin--;
+ idle=0;
+ }
+ if(!cntin&&!cntout) {
+ mvprintw(/*y*/11,/*x*/0,"Loop test : %s",
+ errorcnt?"Failed ":"Passed ");
+ test_loop_fl=0;
+ }
+ }
+
+ if(idle) {
+ mvprintw(/*y*/8,/*x*/0,"Cnt Out: %6d In : %6d %s",
+ cntout,cntin,stopin?"Stop":" ");
+ }
+ } while(c!=KEY_F(10));
+
+ return 0;
+}
+
--- /dev/null
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <termios.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include "tohit_fn.h"
+
+#define DEBUG 0
+#define HAS_GETOPT_LONG 1
+
+int go_flg=0;
+int reset_flg=0;
+int break_flg=0;
+int upload_flg=0;
+int blockerase_flg=0;
+int regerase_flg=0;
+
+int command=TOHIT_WRITE;
+int blockmode=0;
+int erase_block=-1;
+unsigned long mem_start=0;
+unsigned long mem_length=0;
+unsigned long go_addr=0;
+
+#define MEM_BUF_LEN 0x40000
+
+unsigned char mem_buf[MEM_BUF_LEN];
+
+static void
+usage(void)
+{
+ printf("usage: tohit <parameters> <send_file>\n");
+ printf(" -d, --sdev <name> name of RS232 device [%s]\n",tohit_sdev);
+ printf(" -B, --baud <num> RS232 baudrate [%d]\n",tohit_baud);
+ printf(" -c, --command <num> numeric command value\n");
+ printf(" -b, --blockmode <num> block size\n");
+ printf(" -w, --wait-reply <num> time to wait for reply in ms\n");
+ printf(" -e, --erase erase region defined by -s -l\n");
+ printf(" -E, --blockerase <block> erase block\n");
+ printf(" -s, --start <addr> start address of transfer\n");
+ printf(" -l, --length <num> length of upload block\n");
+ printf(" -g, --go <addr> start program from address\n");
+ printf(" -r, --reset reset before download\n");
+ printf(" -b, --break send communication break character\n");
+ printf(" -u, --upload upload memory block [download]\n");
+ printf(" -f, --format <format> format of data file [intelhex]\n");
+ printf(" -V, --version show version\n");
+ printf(" -h, --help this usage screen\n");
+}
+
+int main(int argc, char **argv)
+{
+ int i;
+ FILE *F;
+
+ static struct option long_opts[] = {
+ { "sdev", 1, 0, 'd' },
+ { "baud", 1, 0, 'B' },
+ { "command",1,0, 'c' },
+ { "blockmode",1,0,'b' },
+ { "wait-reply",1,0,'w' },
+ { "blockerase", 1, 0, 'E' },
+ { "erase", 0, 0, 'e' },
+ { "start", 1, 0, 's' },
+ { "length",1, 0, 'l' },
+ { "go", 1, 0, 'g' },
+ { "reset", 0, 0, 'r' },
+ { "break", 0, 0, 'k' },
+ { "upload",0, 0, 'u' },
+ { "format",1, 0, 'f' },
+ { "version",0,0, 'V' },
+ { "help", 0, 0, 'h' },
+ { 0, 0, 0, 0}
+ };
+ int opt;
+
+ #ifndef HAS_GETOPT_LONG
+ while ((opt = getopt(argc, argv, "d:B:c:b:w:E:es:l:g:rkuf:VhD:")) != EOF)
+ #else
+ while ((opt = getopt_long(argc, argv, "d:B:c:b:w:E:es:l:g:rkuf:VhD:",
+ &long_opts[0], NULL)) != EOF)
+ #endif
+ switch (opt) {
+ case 'd':
+ tohit_sdev=optarg;
+ break;
+ case 'B':
+ tohit_baud = strtol(optarg,NULL,0);
+ break;
+ case 'c':
+ if(optarg[0]=='B'){
+ command=TOHIT_WRITEBB;
+ break;
+ }
+ command = strtol(optarg,NULL,0);
+ break;
+ case 'b':
+ blockmode = strtol(optarg,NULL,0);
+ break;
+ case 'w':
+ tohit_waitrep = strtol(optarg,NULL,0)*1000;
+ break;
+ case 'E':
+ erase_block = strtol(optarg,NULL,0);
+ blockerase_flg=1;
+ break;
+ case 'e':
+ regerase_flg=1;
+ break;
+ case 's':
+ mem_start = strtol(optarg,NULL,0);
+ break;
+ case 'l':
+ mem_length = strtol(optarg,NULL,0);
+ break;
+ case 'g':
+ go_addr = strtol(optarg,NULL,0);
+ go_flg = 1;
+ break;
+ case 'r':
+ reset_flg = 1;
+ break;
+ case 'k':
+ break_flg = 1;
+ break;
+ case 'u':
+ upload_flg = 1;
+ break;
+ case 'f':
+ break;
+ case 'V':
+ fputs("tohit pre alpha\n", stdout);
+ exit(0);
+ case 'h':
+ default:
+ usage();
+ exit(opt == 'h' ? 0 : 1);
+ }
+
+ if(break_flg){
+ if(tohit_break()<0){
+ fprintf(stderr,"Error in tohit_break\n");
+ exit(1);
+ }
+ }
+
+ if(reset_flg){
+ if(tohit_reset()<0){
+ fprintf(stderr,"Error in tohit_reset\n");
+ exit(1);
+ }
+ }
+
+ if(blockerase_flg){
+ if(tohit_blockerase(erase_block)<0){
+ fprintf(stderr,"Error in tohit_blockerase\n");
+ exit(1);
+ }
+ }
+
+ if(regerase_flg){
+ if(tohit_regerase(mem_start,mem_length)<0){
+ fprintf(stderr,"Error in tohit_regerase\n");
+ exit(1);
+ }
+ }
+
+ if(!upload_flg&&(optind<argc)){
+ F=fopen(argv[optind++],"r");
+ if(F==NULL){
+ fprintf(stderr,"Error to open file for reading\n");
+ exit(1);
+ }
+ mem_length=fread(mem_buf,1,MEM_BUF_LEN,F);
+ if(mem_length<0){
+ fprintf(stderr,"Error to read mem contents\n");
+ fclose(F);
+ exit(1);
+ }
+ fclose(F);
+
+ if(blockmode){
+ for(i=1;(i<blockmode)&&(i<128);i<<=1);
+ blockmode=i;
+ }
+ if(tohit_writemem(command,mem_buf,mem_start,mem_length,blockmode)<0){
+ fprintf(stderr,"Error in tohit_writemem\n");
+ exit(1);
+ }
+
+ }else
+ if(upload_flg&&(optind<argc)){
+ if(command==0) command=TOHIT_READ;
+ if(mem_length>MEM_BUF_LEN) mem_length=MEM_BUF_LEN;
+ if(tohit_readmem(command,mem_buf,mem_start,mem_length,blockmode)<0){
+ fprintf(stderr,"Error in tohit_readmem\n");
+ exit(1);
+ }
+ F=fopen(argv[optind++],"w");
+ if(F==NULL){
+ fprintf(stderr,"Error to open file for writting\n");
+ exit(1);
+ }
+ if(mem_length!=fwrite(mem_buf,1,mem_length,F)){
+ fprintf(stderr,"Error to write mem contents to file\n");
+ fclose(F);
+ exit(1);
+ }
+ fclose(F);
+ }
+
+ if(go_flg){
+ if(tohit_goto(go_addr)<0){
+ fprintf(stderr,"Error in tohit_goto\n");
+ exit(1);
+ }
+ }
+
+ return 0;
+}
--- /dev/null
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <termios.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include "tohit_fn.h"
+
+#define DEBUG 0
+#define DEBUG_COUNT 0
+
+//#define WITHOUT_CFSETSPEED
+
+#ifdef WITHOUT_CFSETSPEED
+
+struct rs232_speed_struct
+{
+ speed_t value;
+ speed_t internal;
+};
+
+static const struct rs232_speed_struct rs232_speeds[] =
+ {
+#ifdef B0
+ { 0, B0 },
+#endif
+#ifdef B50
+ { 50, B50 },
+#endif
+#ifdef B75
+ { 75, B75 },
+#endif
+#ifdef B110
+ { 110, B110 },
+#endif
+#ifdef B134
+ { 134, B134 },
+#endif
+#ifdef B150
+ { 150, B150 },
+#endif
+#ifdef B200
+ { 200, B200 },
+#endif
+#ifdef B300
+ { 300, B300 },
+#endif
+#ifdef B600
+ { 600, B600 },
+#endif
+#ifdef B1200
+ { 1200, B1200 },
+#endif
+#ifdef B1200
+ { 1200, B1200 },
+#endif
+#ifdef B1800
+ { 1800, B1800 },
+#endif
+#ifdef B2400
+ { 2400, B2400 },
+#endif
+#ifdef B4800
+ { 4800, B4800 },
+#endif
+#ifdef B9600
+ { 9600, B9600 },
+#endif
+#ifdef B19200
+ { 19200, B19200 },
+#endif
+#ifdef B38400
+ { 38400, B38400 },
+#endif
+#ifdef B57600
+ { 57600, B57600 },
+#endif
+#ifdef B76800
+ { 76800, B76800 },
+#endif
+#ifdef B115200
+ { 115200, B115200 },
+#endif
+#ifdef B153600
+ { 153600, B153600 },
+#endif
+#ifdef B230400
+ { 230400, B230400 },
+#endif
+#ifdef B307200
+ { 307200, B307200 },
+#endif
+#ifdef B460800
+ { 460800, B460800 },
+#endif
+ };
+
+/* Set both the input and output baud rates stored in *TERMIOS_P to SPEED. */
+int
+rs232_cfsetspeed (struct termios *termios_p, speed_t speed)
+{
+ size_t cnt;
+
+ for (cnt = 0; cnt < sizeof (rs232_speeds) / sizeof (rs232_speeds[0]); ++cnt)
+ if (speed == rs232_speeds[cnt].internal)
+ {
+ cfsetispeed (termios_p, speed);
+ cfsetospeed (termios_p, speed);
+ return 0;
+ }
+ else if (speed == rs232_speeds[cnt].value)
+ {
+ cfsetispeed (termios_p, rs232_speeds[cnt].internal);
+ cfsetospeed (termios_p, rs232_speeds[cnt].internal);
+ return 0;
+ }
+ /*__set_errno (EINVAL);*/
+
+ return -1;
+}
+
+#endif /* WITHOUT_CFSETSPEED */
+
+/* Set right mode and speed for RS232 interface */
+/* baud can be either speed in character per second or special Bxxxx constant */
+int rs232_setmode(int fd, int baud, int mode, int flowc)
+{
+ struct termios ts;
+
+ /* Flush input and output queues. */
+ if (tcflush(fd, TCIOFLUSH) != 0) {
+ fprintf(stderr,"Error in tcflush\n");
+ return -1;
+ }
+
+ /* Fetch the current terminal parameters. */
+ if (tcgetattr(fd, &ts) != 0) {
+ fprintf(stderr,"Error in tcgetattr\n");
+ return -1;
+ }
+
+ /* Sets hardware control flags: */
+ /* 8 data bits */
+ /* Enable receiver */
+ /* Ignore CD (local connection) */
+ ts.c_cflag = CS8 | CREAD | CLOCAL;
+ if(flowc&1){
+ /* Use RTS/CTS flow control */
+ ts.c_cflag |= CRTSCTS; /* CCTS_OFLOW | CRTS_IFLOW */
+ }
+ ts.c_iflag = 0;
+ ts.c_oflag = NL0 | CR0 | TAB0 | BS0 | VT0 | FF0;
+ ts.c_lflag = 0;
+
+ /* set right ispeed and ospeed */
+ #ifdef WITHOUT_CFSETSPEED
+ if(rs232_cfsetspeed(&ts,baud)<0){
+ fprintf(stderr,"Error in rs232_cfsetspeed\n");
+ return -1;
+ }
+ #else /* WITHOUT_CFSETSPEED */
+ if(cfsetspeed(&ts,baud)<0){
+ fprintf(stderr,"Error in cfsetspeed\n");
+ return -1;
+ }
+ #endif /* WITHOUT_CFSETSPEED */
+
+ ts.c_cc[VINTR] = '\0';
+ ts.c_cc[VQUIT] = '\0';
+ ts.c_cc[VERASE] = '\0';
+ ts.c_cc[VKILL] = '\0';
+ ts.c_cc[VEOF] = '\0';
+ ts.c_cc[VTIME] = '\0';
+ ts.c_cc[VMIN] = 1;
+ ts.c_cc[VSWTC] = '\0';
+ ts.c_cc[VSTART] = '\0';
+ ts.c_cc[VSTOP] = '\0';
+ ts.c_cc[VSUSP] = '\0';
+ ts.c_cc[VEOL] = '\0';
+ ts.c_cc[VREPRINT] = '\0';
+ ts.c_cc[VDISCARD] = '\0';
+ ts.c_cc[VWERASE] = '\0';
+ ts.c_cc[VLNEXT] = '\0';
+ ts.c_cc[VEOL2] = '\0';
+
+ /* Sets the new terminal parameters. */
+ if (tcsetattr(fd, TCSANOW, &ts) != 0) {
+ fprintf(stderr,"Error in tcsetattr\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int rs232_sendch(int fd,unsigned char c)
+{
+ if(write(fd, &c, 1) != 1){
+ fprintf(stderr,"Error in rs232_sendch\n");
+ return -1;
+ }
+ #if DEBUG
+ printf("rs232_sendch 0x%02X \n ",c);
+ #endif
+ return c;
+}
+
+int rs232_recch(int fd)
+{
+ unsigned char c;
+ if (read(fd, &c, 1) != 1){
+ fprintf(stderr,"Error in rs232_recch\n");
+ return -1;
+ }
+ #if DEBUG
+ printf("Read 0x%02X \n",c);
+ #endif
+ return c;
+}
+
+int rs232_test(int fd,int time)
+{
+ struct timeval tv;
+ fd_set rfds;
+ int x;
+
+ if(time<tohit_waitrep)
+ time=tohit_waitrep;
+ tv.tv_sec = 0;
+ tv.tv_usec = time;
+ FD_ZERO(&rfds);
+ FD_SET(fd, &rfds);
+ x=select(fd + 1, &rfds, NULL, NULL, &tv);
+ #if DEBUG
+ printf("rs232_test %d ",x);
+ #endif
+ return x;
+}
+
+void tohit_sendi(int fd,long a, int bytes)
+{
+ while(bytes--){
+ rs232_sendch(fd,(a>>(8*bytes)) & 0xFF);
+ }
+}
+
+long tohit_reci(int fd, int bytes)
+{
+ unsigned long x=0;
+ unsigned long c;
+ while(bytes--){
+ c=rs232_recch(fd);
+ if(c==-1) return -1;
+ x|=c<<(8*bytes);
+ }
+ return x;
+}
+
+int tohit_sendichk(int fd,long a, int bytes)
+{
+ tohit_sendi(fd,a,bytes);
+ rs232_test(fd,500000);
+ if(tohit_reci(fd,bytes)!=a)
+ return -1;
+ return 0;
+}
+
+/* Synchronize with target */
+int tohit_synchronize(int fd)
+{
+ int i;
+ unsigned char c;
+ i=10;
+ do{
+ c=0;
+ rs232_sendch(fd,c);
+
+ if(rs232_test(fd,500000)>0){
+ c=rs232_recch(fd);
+ if(c==0) break;
+ }
+ i--;
+ #if DEBUG
+ printf("\n");
+ #endif
+ }while (i>0);
+
+ if (i==0){
+ printf("Error timeout\n");
+ return -3;
+ }
+
+ /* Run 55=>AA synchronization */
+ #if DEBUG
+ printf("\n");
+ #endif
+ rs232_sendch(fd,0x55);
+ rs232_test(fd,500000);
+ c=rs232_recch(fd);
+ #if DEBUG
+ printf("\n");
+ #endif
+ if (c!=0xAA) {
+ printf("Error in AA reply\n");
+ return -4;
+ }
+ return 0;
+}
+
+
+int tohit_open4cmd(char *sdev, int baud, int cmd)
+{
+ int fd;
+ int c;
+
+ /* Open RS232 device */
+ if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
+ printf("Error openning %s\n",sdev);
+ return -1;
+ }
+
+ /* Set RS232 device mode and speed */
+ if(rs232_setmode(fd,baud,0,0)<0){
+ printf("Error in rs232_setmode\n");
+ return -1;
+ }
+
+ /* Synchronize with target */
+ if(tohit_synchronize(fd)<0){
+ printf("Error in tohit_synchronize\n");
+ return -1;
+ }
+
+ if(cmd!=-1){
+ /* send cmd */
+ c=cmd | ((cmd ^ 7) << 3);
+ rs232_sendch(fd,c);
+ rs232_test(fd,500000);
+ if ((c | 0x80)!=rs232_recch(fd)) {
+ printf("Error in cmd reply\n");
+ return -4;
+ }
+ }
+ return fd;
+}
+
+int tohit_cmdrepchk(int fd)
+{
+ int res;
+ rs232_test(fd,2000000);
+ res=rs232_recch(fd);
+ if(res<0){
+ printf("Error no end reply\n");
+ return -6;
+ }
+ if (res!=0xAA && res!=0x5a) {
+ printf("Error in end reply (0x%02X)\n",res);
+ return -6;
+ }
+ return 0;
+}
+
+#define BLEN 0x40000
+
+unsigned char *tohit_sdev="/dev/ttyS1";
+int tohit_baud=4800;
+
+
+int tohit_goto(unsigned long adr)
+{
+ int fd;
+ if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_GOTO))<0)
+ {
+ printf("Error in tohit_open4cmd\n");
+ close(fd);
+ return -1;
+ }
+ if (tohit_sendichk(fd,adr,4)<0) {
+ printf("Error in goto adr send and reply\n");
+ close(fd);
+ return -4;
+ }
+
+ close(fd);
+ return 1;
+}
+
+int tohit_writemem(int cmd, const unsigned char *buf,
+ unsigned long adr, unsigned long size, int blockmode)
+{
+ int fd;
+ int count;
+ unsigned long i;
+ int j, k;
+ int c;
+ unsigned char rbuf[128];
+
+ if((blockmode==1)||(blockmode>128)) blockmode=128;
+
+ if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, cmd))<0)
+ {
+ printf("Error in tohit_open4cmd\n");
+ close(fd);
+ return -1;
+ }
+ if(cmd==TOHIT_WRITEBB){
+ if (tohit_sendichk(fd,size,2)<0) {
+ printf("Error in start adr send and reply\n");
+ close(fd);
+ return -4;
+ }
+ }else{
+ if (tohit_sendichk(fd,adr,4)<0) {
+ printf("Error in start adr send and reply\n");
+ close(fd);
+ return -4;
+ }
+ if (tohit_sendichk(fd,size,4)<0) {
+ printf("Error in size send and reply\n");
+ close(fd);
+ return -4;
+ }
+ }
+
+ #if DEBUG
+ printf("Data send\n");
+ #endif /* DEBUG */
+ if(!blockmode){
+ for(i=0;i<size;i++){
+ rs232_sendch(fd,buf[i]);
+ rs232_test(fd,500000);
+ c=rs232_recch(fd);
+ if (c!=buf[i]) {
+ printf("Error in data reply\n");
+ close(fd);
+ return -5;
+ }
+ if((i%128)==0){
+ printf(".");
+ fflush(stdout);
+ }
+ #if DEBUG
+ printf("\n");
+ #endif
+ }
+ }else{ /*TOHIT_WRITEFL*/
+ i=0;
+ count=blockmode-(adr&(blockmode-1));
+ while(i<size){
+ if(count>(size-i)) count=size-i;
+
+ #if DEBUG_COUNT
+ printf("count %d\n",count);
+ #endif
+ j=0;
+ while(j<count){
+ k=write(fd, buf+i+j, count-j);
+ j+=k;
+ if((k<=0)||(j>count)){
+ printf("Error in blk write (%d,%d)\n",j,k);
+ close(fd);
+ return -2;
+ }
+ }
+ #if DEBUG
+ printf("Write %d chars \n",count);
+ #endif
+ j=0;
+ do{
+ rs232_test(fd,500000);
+ k=read(fd, rbuf+j, count-j);
+ if(k>=0) j+=k;
+ if(k<0)
+ {
+ printf("Error in blk write - no reply (%d,%d)\n",j,k);
+ close(fd);
+ return -2;
+ }
+ #if DEBUG
+ printf("Read %d chars ",k);
+ #endif
+ }while(j<count);
+ printf(".");
+ fflush(stdout);
+ for(j=0;j<count;j++){
+ if (rbuf[j]!=buf[i+j]) {
+ printf("Error in data reply %02x %02x %ld\n",rbuf[j],buf[i+j],i+j);
+ close(fd);
+ return -5;
+ }
+ }
+ i+=count;
+ count=blockmode;
+ }
+ printf("\n");
+ }
+
+ if(tohit_cmdrepchk(fd)<0){
+ printf("Error no end reply\n");
+ close(fd);
+ return -4;
+ }
+ close(fd);
+ return 1;
+}
+
+int tohit_readmem(int cmd, unsigned char *buf,
+ unsigned long adr, unsigned long size, int blockmode)
+{
+ int fd;
+ unsigned long i;
+ int c,k,ret;
+
+ if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, cmd))<0)
+ {
+ printf("Error in tohit_open4cmd\n");
+ close(fd);
+ return -1;
+ }
+ if (tohit_sendichk(fd,adr,4)<0) {
+ printf("Error in start adr send and reply\n");
+ close(fd);
+ return -4;
+ }
+ if (tohit_sendichk(fd,size,4)<0) {
+ printf("Error in size send and reply\n");
+ close(fd);
+ return -4;
+ }
+ if(!blockmode){
+ /* Read memory by single byte */
+ for(i=0;i<size;i++){
+ rs232_test(fd,500000);
+ if((c=rs232_recch(fd))<0){
+ printf("Error in receive char\n");
+ close(fd);
+ return -4;
+ }
+ buf[i]=c;
+ rs232_sendch(fd,c);
+ if((i%128)==0){
+ printf(".");
+ fflush(stdout);
+ }
+ #if DEBUG
+ printf("\n");
+ #endif
+ }
+ printf("\n");
+
+ if(tohit_cmdrepchk(fd)<0){
+ printf("Error no end reply\n");
+ close(fd);
+ return -4;
+ }
+ }else{
+ /* Read memory by blocks */
+ for(i=0;i<size;){
+ if(size-i>blockmode) c=blockmode;
+ else c=size-i;
+ for(k=0;k<c;k++)
+ while(rs232_sendch(fd,0)<0);
+ for(k=0;k<c;){
+ rs232_test(fd,500000);
+ ret=read(fd,buf+i+k,c-k);
+ if(ret<0){
+ printf("Error in block receive\n");
+ close(fd);
+ return -4;
+ }
+ k+=ret;
+ }
+ printf(".");
+ fflush(stdout);
+ i+=c;
+ }
+ if(rs232_recch(fd)!=0xff){
+ printf("Error no end reply\n");
+ close(fd);
+ return -4;
+ }
+ }
+ close(fd);
+ return 1;
+}
+
+int tohit_blockerase(int block)
+{
+ int fd;
+
+ if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_ERASEBL))<0)
+ {
+ printf("Error in tohit_open4cmd\n");
+ close(fd);
+ return -1;
+ }
+
+ rs232_sendch(fd,block);
+ rs232_test(fd,2000000);
+ rs232_test(fd,2000000);
+
+ if(tohit_cmdrepchk(fd)<0){
+ printf("Error no end reply\n");
+ close(fd);
+ return -4;
+ }
+ close(fd);
+ return 1;
+}
+
+int tohit_regerase(unsigned long adr, unsigned long size)
+{
+ int fd;
+
+ if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_ERASEREG))<0)
+ {
+ printf("Error in tohit_open4cmd\n");
+ close(fd);
+ return -1;
+ }
+ if (tohit_sendichk(fd,adr,4)<0) {
+ printf("Error in start adr send and reply\n");
+ close(fd);
+ return -4;
+ }
+ if (tohit_sendichk(fd,size,4)<0) {
+ printf("Error in size send and reply\n");
+ close(fd);
+ return -4;
+ }
+
+ printf("\n");
+
+ if(tohit_cmdrepchk(fd)<0){
+ printf("Error no end reply\n");
+ close(fd);
+ return -4;
+ }
+ close(fd);
+ return 1;
+}
+
+int tohit_reset(void)
+{
+ int fd;
+ if((fd=tohit_open4cmd(tohit_sdev, tohit_baud, TOHIT_RESET))<0)
+ {
+ printf("Error in tohit_open4cmd\n");
+ close(fd);
+ return -1;
+ }
+ close(fd);
+ return 1;
+}
+
+int tohit_break(void)
+{
+ int fd;
+ int i;
+ char c=0;
+
+ /* Open RS232 device */
+ if ((fd = open(tohit_sdev, O_RDWR | O_NONBLOCK)) == -1) {
+ printf("Error openning %s\n",tohit_sdev);
+ return -1;
+ }
+
+ if(rs232_setmode(fd,tohit_baud/2,0,0)<0)
+ {
+ close(fd);
+ return -1;
+ }
+
+ #if DEBUG
+ printf("Sending break chars \n");
+ #endif
+ for(i=100;i--;)
+ write(fd,&c,1);
+
+ close(fd);
+ return 1;
+}
+
--- /dev/null
+#ifndef _TOHIT_FN_H
+#define _TOHIT_FN_H
+
+/* cmd -1 write memory using ROM boot loader */
+/* cmd 0 write memory */
+/* cmd 1 write memory */
+/* cmd 2 read memory */
+/* cmd 3 erase flash block */
+/* cmd 4 erase region*/
+/* cmd 6 call address */
+/* cmd 7 reset */
+
+#define TOHIT_WRITEBB (-1)
+#define TOHIT_WRITE 0
+#define TOHIT_WRITEFL 1
+#define TOHIT_READ 2
+#define TOHIT_ERASEBL 3
+#define TOHIT_ERASEREG 4
+#define TOHIT_GOTO 6
+#define TOHIT_RESET 7
+
+int rs232_setmode(int fd, int baud, int mode, int flowc);
+
+int rs232_sendch(int fd,unsigned char c);
+
+int rs232_recch(int fd);
+
+int rs232_test(int fd,int time);
+
+void tohit_sendi(int fd,long a, int bytes);
+
+long tohit_reci(int fd, int bytes);
+
+int tohit_sendichk(int fd,long a, int bytes);
+
+int tohit_synchronize(int fd);
+
+int tohit_open4cmd(char *sdev, int baud, int cmd);
+
+int tohit_cmdrepchk(int fd);
+
+int tohit_goto(unsigned long adr);
+
+int tohit_writemem(int cmd, const unsigned char *buf,
+ unsigned long adr, unsigned long size, int blockmode);
+
+int tohit_readmem(int cmd, unsigned char *buf,
+ unsigned long adr, unsigned long size, int blockmode);
+
+int tohit_blockerase(int block);
+
+int tohit_regerase(unsigned long adr, unsigned long size);
+
+
+unsigned char *tohit_sdev;
+int tohit_baud;
+long tohit_waitrep;
+
+int tohit_reset(void);
+
+int tohit_break(void);
+
+#endif /* _TOHIT_FN_H */
+
+
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+SUBDIRS = generic $(ARCH)
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+SUBDIRS = defines
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+#ifndef _BYTESWAP_H
+#define _BYTESWAP_H 1
+
+#define __bswap_16(x) ({unsigned short __x=(x); \
+ (((__x>>8)&0xff)|((__x&0xff)<<8)); })
+
+#define __bswap_32(x) ({unsigned long __y=(x); \
+ (__bswap_16(__y>>16)|__bswap_16(__y)<<16); })
+
+#define bswap_16(x) __bswap_16 (x)
+
+#define bswap_32(x) __bswap_32 (x)
+
+#endif /* byteswap.h */
--- /dev/null
+#ifndef _ENDIAN_H
+#define _ENDIAN_H 1
+
+#define __LITTLE_ENDIAN 1234
+#define __BIG_ENDIAN 4321
+#define __PDP_ENDIAN 3412
+
+#if defined(__i386__) || defined(SDCC)
+#define __BYTE_ORDER __LITTLE_ENDIAN
+#endif
+
+#if defined(__H8300__) || defined(__H8500__) || defined (__H8300H__) || defined(__W65__) || defined (__H8300S__) || defined (__m68k__)
+#define __BYTE_ORDER __BIG_ENDIAN
+#endif
+
+#endif /* endian.h */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+SUBDIRS = generic mach-$(MACH)
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = defines libs
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ cpu_def.h - low level CPU support for C programs
+ atomic bit operations, interrupts and exceptions
+
+ Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ Functions names and concept inspired by Linux kernel
+
+ *******************************************************************/
+
+#ifndef _H8S_CPU_DEF_H
+#define _H8S_CPU_DEF_H
+
+/* atomic access routines */
+
+#define __xcase_xop_bit(nr,v,__aln,__aconaddr,__acondata) \
+ ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
+ unsigned short __nr=(nr); \
+ char *__pb=(char*)__pv; \
+ __pb+=sizeof(*__pv)-1-(__nr)/8; \
+ __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
+ "=U" (*__pb) : __acondata ((nr)&7), "0" (*__pb)); })
+
+#define __constant_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,%0\n","i","i")
+
+#define __constantdata_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,%0\n","r","i")
+
+#define __generic_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1l,%0\n","r","r")
+
+#define set_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __builtin_constant_p(v) ?\
+ __constant_set_bit(nr, v) : \
+ __constantdata_set_bit(nr, v) : \
+ __generic_set_bit(nr, v))
+
+#define __constant_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,%0\n","i","i")
+
+#define __constantdata_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,%0\n","r","i")
+
+#define __generic_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1l,%0\n","r","r")
+
+#define clear_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __builtin_constant_p(v) ?\
+ __constant_clear_bit(nr, v) : \
+ __constantdata_clear_bit(nr, v) : \
+ __generic_clear_bit(nr, v))
+
+
+#define __xcase_xop_mask_b1(mask,v,__aln,__aconaddr,__acondata) \
+ ({ volatile char *__pv=(char*)(v); \
+ unsigned __mask=(mask); \
+ if(__mask&0x0001) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (0), "0" (*__pv)); \
+ if(__mask&0x0002) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (1), "0" (*__pv)); \
+ if(__mask&0x0004) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (2), "0" (*__pv)); \
+ if(__mask&0x0008) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (3), "0" (*__pv)); \
+ if(__mask&0x0010) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (4), "0" (*__pv)); \
+ if(__mask&0x0020) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (5), "0" (*__pv)); \
+ if(__mask&0x0040) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (6), "0" (*__pv)); \
+ if(__mask&0x0080) __asm__ __volatile__(__aln " /*mymask b1*/\n": "=U" (*__pv) : __acondata (7), "0" (*__pv)); \
+ })
+
+
+#define __constant_atomic_clear_mask_b1(mask, v) \
+ __xcase_xop_mask_b1(mask,v,"bclr %1,%0\n","i","n")
+
+#define __generic_atomic_clear_mask_b1(mask, v) \
+ __xcase_xop_mask_b1(mask,v,"bclr %1,%0\n","r","n")
+
+
+#define atomic_clear_mask_b1(mask, v) \
+ ( __builtin_constant_p(v) ? \
+ __constant_atomic_clear_mask_b1(mask, v) : \
+ __generic_atomic_clear_mask_b1(mask, v))
+
+#define __constant_atomic_set_mask_b1(mask, v) \
+ __xcase_xop_mask_b1(mask,v,"bset %1,%0\n","i","n")
+
+#define __generic_atomic_set_mask_b1(mask, v) \
+ __xcase_xop_mask_b1(mask,v,"bset %1,%0\n","r","n")
+
+#define atomic_set_mask_b1(mask, v) \
+ ( __builtin_constant_p(v) ?\
+ __constant_atomic_set_mask_b1(mask, v) : \
+ __generic_atomic_set_mask_b1(mask, v))
+
+
+#define __xcase_xop_mask_w1(mask,v,__aln,__aconaddr,__acondata) \
+ ({ volatile char *__pv; \
+ unsigned __mask=(mask); \
+ if(__mask&0x0001) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (0), "0" (*__pv)); } \
+ if(__mask&0x0002) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (1), "0" (*__pv)); } \
+ if(__mask&0x0004) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (2), "0" (*__pv)); } \
+ if(__mask&0x0008) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (3), "0" (*__pv)); } \
+ if(__mask&0x0010) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (4), "0" (*__pv)); } \
+ if(__mask&0x0020) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (5), "0" (*__pv)); } \
+ if(__mask&0x0040) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (6), "0" (*__pv)); } \
+ if(__mask&0x0080) { __pv=(char*)(v)+1; __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (7), "0" (*__pv)); } \
+ if(__mask&0x0100) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (0), "0" (*__pv)); } \
+ if(__mask&0x0200) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (1), "0" (*__pv)); } \
+ if(__mask&0x0400) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (2), "0" (*__pv)); } \
+ if(__mask&0x0800) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (3), "0" (*__pv)); } \
+ if(__mask&0x1000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (4), "0" (*__pv)); } \
+ if(__mask&0x2000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (5), "0" (*__pv)); } \
+ if(__mask&0x4000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (6), "0" (*__pv)); } \
+ if(__mask&0x8000) { __pv=(char*)(v); __asm__ __volatile__(__aln " /*mymask w1*/\n": "=U" (*__pv) : __acondata (7), "0" (*__pv)); } \
+ })
+
+#define __constant_atomic_clear_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bclr %1,%0\n","i","n")
+
+#define __generic_atomic_clear_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bclr %1,%0\n","r","n")
+
+
+#define atomic_clear_mask_w1(mask, v) \
+ ( __builtin_constant_p(v) ? \
+ __constant_atomic_clear_mask_w1(mask, v) : \
+ __generic_atomic_clear_mask_w1(mask, v))
+
+#define __constant_atomic_set_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bset %1,%0\n","i","n")
+
+#define __generic_atomic_set_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bset %1,%0\n","r","nP")
+
+#define atomic_set_mask_w1(mask, v) \
+ ( __builtin_constant_p(v) ?\
+ __constant_atomic_set_mask_w1(mask, v) : \
+ __generic_atomic_set_mask_w1(mask, v))
+
+/*
+
+#define atomic_clear_mask(mask, v) \
+ __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask(mask, v) \
+ __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_w(mask, v) \
+ __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_w(mask, v) \
+ __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_b(mask, v) \
+ __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_b(mask, v) \
+ __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+*/
+
+
+/* Port access routines */
+
+#define readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+/* Arithmetic functions */
+
+#define sat_add_slsl(__x,__y) \
+ __asm__ (" add.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define sat_sub_slsl(__x,__y) \
+ __asm__ (" sub.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define div_us_ulus(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxu.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define div_ss_slss(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxs.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define muldiv_us(__x,__y,__z) \
+ div_ss_slss((long)(__x)*(__y),__z)
+
+#define muldiv_ss(__x,__y,__z) \
+ div_us_ulus((unsigned long)(__x)*(__y),__z)
+
+/* Power down modes support */
+
+#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
+
+/* IRQ handling code */
+
+//#define _USE_EXR_LEVELS 1
+
+#ifdef _USE_EXR_LEVELS
+
+#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __exr; \
+ __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
+ (x)=__exr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __exr=(x); \
+ __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
+ }while(0)
+
+
+#else /* _USE_EXR_LEVELS */
+
+#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __ccr; \
+ __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
+ (x)=__ccr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __ccr=(x); \
+ __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
+ }while(0)
+
+#endif /* _USE_EXR_LEVELS */
+
+#define __get_vbr(x) 0
+
+#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
+
+#define __memory_barrier() \
+__asm__ __volatile__("": : : "memory")
+
+#define cli() __cli()
+#define sti() __sti()
+
+#define save_flags(x) __save_flags(x)
+#define restore_flags(x) __restore_flags(x)
+#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
+
+#define NR_IRQS 256
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+/*
+
+#if 0
+struct pt_regs {
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long a0;
+ long a1;
+ long a2;
+ long d0;
+ long orig_d0;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#else
+struct pt_regs {
+ long d0;
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long d6;
+ long d7;
+ long a0;
+ long a1;
+ long a2;
+ long a3;
+ long a4;
+ long a5;
+ long a6;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#endif
+
+typedef struct irq_handler {
+ void (*handler)(int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+ struct irq_handler *next;
+} irq_handler_t;
+
+irq_handler_t *irq_array[NR_IRQS];
+void *irq_vec[NR_IRQS];
+
+int add_irq_handler(int vectno,irq_handler_t *handler);
+*/
+
+void *excptvec_get(int vectnum);
+
+void *excptvec_set(int vectnum,void *vect);
+
+int excptvec_initfill(void *fill_vect, int force_all);
+
+#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
+#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
+
+#endif /* _H8S_CPU_DEF_H */
--- /dev/null
+#ifndef _H8S_CPU_DEF_H
+#define _H8S_CPU_DEF_H
+
+/* atomic access routines */
+
+#define __xcase_xop_bit(nr,v,__aln,__acon) \
+ ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
+ unsigned short __nr=(nr); \
+ char *__pb=(char*)__pv; \
+ __pb+=sizeof(*__pv)-1-(__nr)/8; \
+ __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
+ "=U" (*__pb) : __acon ((nr)&7), "0" (*__pb)); })
+
+#define __constant_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,%0\n","i")
+
+#define __generic_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1l,%0\n","r")
+
+#define set_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __constant_set_bit(nr, v) : \
+ __generic_set_bit(nr, v))
+
+#define __constant_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,%0\n","i")
+
+#define __generic_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,%0\n","r")
+
+#define clear_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __constant_clear_bit(nr, v) : \
+ __generic_clear_bit(nr, v))
+
+#define atomic_clear_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ __asm__ __volatile__("bclr %V1,%0\n" : "=U" (*__pv) : "P" (mask),"0"(*__pv)); \
+ })
+
+#define atomic_set_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ __asm__ __volatile__("bset %V1,%0\n" : "=U" (*__pv) : "P" (mask),"0"(*__pv)); \
+ })
+
+#define atomic_clear_mask_w1(mask, v) \
+ ({ char *__pv=(char*)(v); \
+ unsigned __mask=(mask); \
+ if((__mask)&0xff) __pv++; else __mask>>=8; \
+ __asm__ __volatile__("bclr %V1,%0\n" : "=U" (*__pv) : "P" (__mask),"0"(*__pv)); \
+ })
+
+#define atomic_set_mask_w1(mask, v) \
+ ({ char *__pv=(char*)(v); \
+ unsigned __mask=(mask); \
+ if((__mask)&0xff) __pv++; else __mask>>=8; \
+ __asm__ __volatile__("bset %V1,%0\n" : "=U" (*__pv) : "P" (__mask),"0"(*__pv)); \
+ })
+
+/*
+
+#define atomic_clear_mask(mask, v) \
+ __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask(mask, v) \
+ __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_w(mask, v) \
+ __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_w(mask, v) \
+ __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_b(mask, v) \
+ __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_b(mask, v) \
+ __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+*/
+
+
+/* Port access routines */
+
+#define readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+/* Arithmetic functions */
+
+#define sat_add_slsl(__x,__y) \
+ __asm__ (" add.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define sat_sub_slsl(__x,__y) \
+ __asm__ (" sub.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define div_us_ulus(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxu.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define div_ss_slss(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxs.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define muldiv_us(__x,__y,__z) \
+ div_ss_slss((long)(__x)*(__y),__z)
+
+#define muldiv_ss(__x,__y,__z) \
+ div_us_ulus((unsigned long)(__x)*(__y),__z)
+
+/* Power down modes support */
+
+#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
+
+/* IRQ handling code */
+
+//#define _USE_EXR_LEVELS 1
+
+#ifdef _USE_EXR_LEVELS
+
+#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __exr; \
+ __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
+ (x)=__exr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __exr=(x); \
+ __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
+ }while(0)
+
+
+#else /* _USE_EXR_LEVELS */
+
+#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __ccr; \
+ __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
+ (x)=__ccr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __ccr=(x); \
+ __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
+ }while(0)
+
+#endif /* _USE_EXR_LEVELS */
+
+#define __get_vbr(x) 0
+
+#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
+
+#define __memory_barrier() \
+__asm__ __volatile__("": : : "memory")
+
+#define cli() __cli()
+#define sti() __sti()
+
+#define save_flags(x) __save_flags(x)
+#define restore_flags(x) __restore_flags(x)
+#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
+
+#define NR_IRQS 256
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+/*
+
+#if 0
+struct pt_regs {
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long a0;
+ long a1;
+ long a2;
+ long d0;
+ long orig_d0;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#else
+struct pt_regs {
+ long d0;
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long d6;
+ long d7;
+ long a0;
+ long a1;
+ long a2;
+ long a3;
+ long a4;
+ long a5;
+ long a6;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#endif
+
+typedef struct irq_handler {
+ void (*handler)(int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+ struct irq_handler *next;
+} irq_handler_t;
+
+irq_handler_t *irq_array[NR_IRQS];
+void *irq_vec[NR_IRQS];
+
+int add_irq_handler(int vectno,irq_handler_t *handler);
+*/
+
+void *excptvec_get(int vectnum);
+
+void *excptvec_set(int vectnum,void *vect);
+
+int excptvec_initfill(void *fill_vect, int force_all);
+
+#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
+#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
+
+#endif /* _H8S_CPU_DEF_H */
--- /dev/null
+#ifndef _H8S_CPU_DEF_H
+#define _H8S_CPU_DEF_H
+
+/* atomic access routines */
+
+#define __xcase_xop_bit(nr,v,__aln,__acon) \
+ ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
+ unsigned short __nr=(nr); \
+ char *__pb=(char*)__pv; \
+ __pb+=sizeof(*__pv)-1-(__nr)/8; \
+ __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
+ "=r" (__pb) : __acon ((nr)&7), "0" (__pb)); })
+
+#define __constant_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,@%0\n","i")
+
+#define __generic_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1l,@%0\n","r")
+
+#define set_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __constant_set_bit(nr, v) : \
+ __generic_set_bit(nr, v))
+
+#define __constant_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,@%0\n","i")
+
+#define __generic_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,@%0\n","r")
+
+#define clear_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __constant_clear_bit(nr, v) : \
+ __generic_clear_bit(nr, v))
+
+#define atomic_clear_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ __asm__ __volatile__("bclr %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (mask),"0"(__pv)); \
+ })
+
+#define atomic_set_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ __asm__ __volatile__("bset %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (mask),"0"(__pv)); \
+ })
+
+#define atomic_clear_mask_w1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ unsigned __mask=(mask); \
+ if((__mask)&0xff) __pv++; else __mask>>=8; \
+ __asm__ __volatile__("bclr %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (__mask),"0"(__pv)); \
+ })
+
+#define atomic_set_mask_w1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ unsigned __mask=(mask); \
+ if((__mask)&0xff) __pv++; else __mask>>=8; \
+ __asm__ __volatile__("bset %V1,@%0 /*mymask*/\n" : "=r" (__pv) : "P" (__mask),"0"(__pv)); \
+ })
+
+/*
+
+#define atomic_clear_mask(mask, v) \
+ __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask(mask, v) \
+ __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_w(mask, v) \
+ __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_w(mask, v) \
+ __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_b(mask, v) \
+ __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_b(mask, v) \
+ __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+*/
+
+
+/* Port access routines */
+
+#define readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+/* Arithmetic functions */
+
+#define sat_add_slsl(__x,__y) \
+ __asm__ (" add.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define sat_sub_slsl(__x,__y) \
+ __asm__ (" sub.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define div_us_ulus(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxu.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define div_ss_slss(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxs.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define muldiv_us(__x,__y,__z) \
+ div_ss_slss((long)(__x)*(__y),__z)
+
+#define muldiv_ss(__x,__y,__z) \
+ div_us_ulus((unsigned long)(__x)*(__y),__z)
+
+/* Power down modes support */
+
+#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
+
+/* IRQ handling code */
+
+//#define _USE_EXR_LEVELS 1
+
+#ifdef _USE_EXR_LEVELS
+
+#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __exr; \
+ __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
+ (x)=__exr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __exr=(x); \
+ __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
+ }while(0)
+
+
+#else /* _USE_EXR_LEVELS */
+
+#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __ccr; \
+ __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
+ (x)=__ccr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __ccr=(x); \
+ __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
+ }while(0)
+
+#endif /* _USE_EXR_LEVELS */
+
+#define __get_vbr(x) 0
+
+#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
+
+#define __memory_barrier() \
+__asm__ __volatile__("": : : "memory")
+
+#define cli() __cli()
+#define sti() __sti()
+
+#define save_flags(x) __save_flags(x)
+#define restore_flags(x) __restore_flags(x)
+#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
+
+#define NR_IRQS 256
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+/*
+
+#if 0
+struct pt_regs {
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long a0;
+ long a1;
+ long a2;
+ long d0;
+ long orig_d0;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#else
+struct pt_regs {
+ long d0;
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long d6;
+ long d7;
+ long a0;
+ long a1;
+ long a2;
+ long a3;
+ long a4;
+ long a5;
+ long a6;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#endif
+
+typedef struct irq_handler {
+ void (*handler)(int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+ struct irq_handler *next;
+} irq_handler_t;
+
+irq_handler_t *irq_array[NR_IRQS];
+void *irq_vec[NR_IRQS];
+
+int add_irq_handler(int vectno,irq_handler_t *handler);
+*/
+
+void *excptvec_get(int vectnum);
+
+void *excptvec_set(int vectnum,void *vect);
+
+int excptvec_initfill(void *fill_vect, int force_all);
+
+#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
+#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
+
+#endif /* _H8S_CPU_DEF_H */
--- /dev/null
+#ifndef _H8S_CPU_DEF_H
+#define _H8S_CPU_DEF_H
+
+/* atomic access routines */
+
+#define __xcase_xop_bit(nr,v,__aln,__aconaddr,__acondata) \
+ ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
+ unsigned short __nr=(nr); \
+ char *__pb=(char*)__pv; \
+ __pb+=sizeof(*__pv)-1-(__nr)/8; \
+ __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
+ "=m" (*__pb) : __acondata ((nr)&7), __aconaddr (__pb)); })
+
+#define __constant_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,@%u2\n","i","i")
+
+#define __constantdata_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,@%2\n","r","i")
+
+#define __generic_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1l,@%2\n","r","r")
+
+#define set_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __builtin_constant_p(v) ?\
+ __constant_set_bit(nr, v) : \
+ __constantdata_set_bit(nr, v) : \
+ __generic_set_bit(nr, v))
+
+#define __constant_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,@%u2\n","i","i")
+
+#define __constantdata_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,@%2\n","r","i")
+
+#define __generic_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1l,@%2\n","r","r")
+
+#define clear_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __builtin_constant_p(v) ?\
+ __constant_clear_bit(nr, v) : \
+ __constantdata_clear_bit(nr, v) : \
+ __generic_clear_bit(nr, v))
+
+#define atomic_clear_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ if(__builtin_constant_p(v)) \
+ __asm__ __volatile__("bclr %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
+ else \
+ __asm__ __volatile__("bclr %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
+ })
+
+#define atomic_set_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ if(__builtin_constant_p(v)) \
+ __asm__ __volatile__("bset %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
+ else \
+ __asm__ __volatile__("bset %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
+ })
+
+#define __xcase_xop_mask_w1(mask,v,__aln,__aconaddr,__acondata) \
+ ({ volatile char *__pv=(char*)(v); \
+ unsigned __mask=(mask); \
+ if((__mask)&0xff) __pv++; else __mask>>=8; \
+ __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (__mask), __aconaddr (__pv)); \
+ })
+
+
+#define __constant_atomic_clear_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bclr %V1,@%u2\n","i","P")
+
+#define __generic_atomic_clear_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bclr %V1,@%2\n","r","P")
+
+#define atomic_clear_mask_w1(mask, v) \
+ (__builtin_constant_p(mask) ? \
+ __builtin_constant_p(v) ?\
+ __constant_atomic_clear_mask_w1(mask, v) : \
+ __generic_atomic_clear_mask_w1(mask, v) : \
+ error_to_use_for_nonconstant_mask())
+
+#define __constant_atomic_set_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bset %V1,@%u2\n","i","P")
+
+#define __generic_atomic_set_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bset %V1,@%2\n","r","P")
+
+#define atomic_set_mask_w1(mask, v) \
+ (__builtin_constant_p(mask) ? \
+ __builtin_constant_p(v) ?\
+ __constant_atomic_set_mask_w1(mask, v) : \
+ __generic_atomic_set_mask_w1(mask, v) : \
+ error_to_use_for_nonconstant_mask())
+
+/*
+
+#define atomic_clear_mask(mask, v) \
+ __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask(mask, v) \
+ __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_w(mask, v) \
+ __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_w(mask, v) \
+ __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_b(mask, v) \
+ __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_b(mask, v) \
+ __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+*/
+
+
+/* Port access routines */
+
+#define readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+/* Arithmetic functions */
+
+#define sat_add_slsl(__x,__y) \
+ __asm__ (" add.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define sat_sub_slsl(__x,__y) \
+ __asm__ (" sub.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define div_us_ulus(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxu.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define div_ss_slss(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxs.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define muldiv_us(__x,__y,__z) \
+ div_ss_slss((long)(__x)*(__y),__z)
+
+#define muldiv_ss(__x,__y,__z) \
+ div_us_ulus((unsigned long)(__x)*(__y),__z)
+
+/* Power down modes support */
+
+#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
+
+/* IRQ handling code */
+
+//#define _USE_EXR_LEVELS 1
+
+#ifdef _USE_EXR_LEVELS
+
+#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __exr; \
+ __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
+ (x)=__exr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __exr=(x); \
+ __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
+ }while(0)
+
+
+#else /* _USE_EXR_LEVELS */
+
+#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __ccr; \
+ __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
+ (x)=__ccr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __ccr=(x); \
+ __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
+ }while(0)
+
+#endif /* _USE_EXR_LEVELS */
+
+#define __get_vbr(x) 0
+
+#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
+
+#define __memory_barrier() \
+__asm__ __volatile__("": : : "memory")
+
+#define cli() __cli()
+#define sti() __sti()
+
+#define save_flags(x) __save_flags(x)
+#define restore_flags(x) __restore_flags(x)
+#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
+
+#define NR_IRQS 256
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+/*
+
+#if 0
+struct pt_regs {
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long a0;
+ long a1;
+ long a2;
+ long d0;
+ long orig_d0;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#else
+struct pt_regs {
+ long d0;
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long d6;
+ long d7;
+ long a0;
+ long a1;
+ long a2;
+ long a3;
+ long a4;
+ long a5;
+ long a6;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#endif
+
+typedef struct irq_handler {
+ void (*handler)(int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+ struct irq_handler *next;
+} irq_handler_t;
+
+irq_handler_t *irq_array[NR_IRQS];
+void *irq_vec[NR_IRQS];
+
+int add_irq_handler(int vectno,irq_handler_t *handler);
+*/
+
+void *excptvec_get(int vectnum);
+
+void *excptvec_set(int vectnum,void *vect);
+
+int excptvec_initfill(void *fill_vect, int force_all);
+
+#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
+#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
+
+#endif /* _H8S_CPU_DEF_H */
--- /dev/null
+#ifndef _H8S_CPU_DEF_H
+#define _H8S_CPU_DEF_H
+
+/* atomic access routines */
+
+#define __xcase_xop_bit(nr,v,__aln,__aconaddr,__acondata) \
+ ({ volatile __typeof(*v) *__pv =(__typeof(*v) *)(v); \
+ unsigned short __nr=(nr); \
+ char *__pb=(char*)__pv; \
+ __pb+=sizeof(*__pv)-1-(__nr)/8; \
+ __asm__ __volatile__ ( __aln " /*mybit*/\n" : \
+ "=m" (*__pb) : __acondata ((nr)&7), __aconaddr (__pb)); })
+
+#define __constant_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,@%u2\n","i","i")
+
+#define __constantdata_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1,@%2\n","r","i")
+
+#define __generic_set_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bset %1l,@%2\n","r","r")
+
+#define set_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __builtin_constant_p(v) ?\
+ __constant_set_bit(nr, v) : \
+ __constantdata_set_bit(nr, v) : \
+ __generic_set_bit(nr, v))
+
+#define __constant_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,@%u2\n","i","i")
+
+#define __constantdata_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1,@%2\n","r","i")
+
+#define __generic_clear_bit(nr,v) \
+ __xcase_xop_bit(nr,v," bclr %1l,@%2\n","r","r")
+
+#define clear_bit(nr,v) \
+ (__builtin_constant_p(nr) ? \
+ __builtin_constant_p(v) ?\
+ __constant_clear_bit(nr, v) : \
+ __constantdata_clear_bit(nr, v) : \
+ __generic_clear_bit(nr, v))
+
+#define atomic_clear_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ if(__builtin_constant_p(v)) \
+ __asm__ __volatile__("bclr %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
+ else \
+ __asm__ __volatile__("bclr %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
+ })
+
+#define atomic_set_mask_b1(mask, v) \
+ ({ volatile char *__pv=(char*)(v); \
+ if(__builtin_constant_p(v)) \
+ __asm__ __volatile__("bset %V1,@%u2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"i"(v)); \
+ else \
+ __asm__ __volatile__("bset %V1,@%2 /*mymask*/\n" : "=m" (*__pv) : "P" (mask),"r"(__pv)); \
+ })
+
+#define __xcase_xop_mask_w1(mask,v,__aln,__aconaddr,__acondata) \
+ ({ volatile char *__pv=(char*)(v); \
+ switch(mask){ \
+ case 0x0001: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (0), __aconaddr (__pv+1)); break; \
+ case 0x0002: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (1), __aconaddr (__pv+1)); break; \
+ case 0x0004: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (2), __aconaddr (__pv+1)); break; \
+ case 0x0008: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (3), __aconaddr (__pv+1)); break; \
+ case 0x0010: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (4), __aconaddr (__pv+1)); break; \
+ case 0x0020: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (5), __aconaddr (__pv+1)); break; \
+ case 0x0040: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (6), __aconaddr (__pv+1)); break; \
+ case 0x0080: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (7), __aconaddr (__pv+1)); break; \
+ case 0x0100: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (0), __aconaddr (__pv)); break; \
+ case 0x0200: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (1), __aconaddr (__pv)); break; \
+ case 0x0400: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (2), __aconaddr (__pv)); break; \
+ case 0x0800: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (3), __aconaddr (__pv)); break; \
+ case 0x1000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (4), __aconaddr (__pv)); break; \
+ case 0x2000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (5), __aconaddr (__pv)); break; \
+ case 0x4000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (6), __aconaddr (__pv)); break; \
+ case 0x8000: __asm__ __volatile__(__aln " /*mymask*/\n": "=m" (*__pv) : __acondata (7), __aconaddr (__pv)); break; \
+ } \
+ })
+
+#define __constant_atomic_clear_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bclr %1,@%u2\n","i","n")
+
+#define __generic_atomic_clear_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bclr %1,@%2\n","r","n")
+
+
+#define atomic_clear_mask_w1(mask, v) \
+ ( __builtin_constant_p(v) ? \
+ __constant_atomic_clear_mask_w1(mask, v) : \
+ __generic_atomic_clear_mask_w1(mask, v))
+
+#define __constant_atomic_set_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bset %1,@%u2\n","i","n")
+
+#define __generic_atomic_set_mask_w1(mask, v) \
+ __xcase_xop_mask_w1(mask,v,"bset %1,@%2\n","r","nP")
+
+#define atomic_set_mask_w1(mask, v) \
+ ( __builtin_constant_p(v) ?\
+ __constant_atomic_set_mask_w1(mask, v) : \
+ __generic_atomic_set_mask_w1(mask, v))
+
+/*
+
+#define atomic_clear_mask(mask, v) \
+ __asm__ __volatile__("and.l %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask(mask, v) \
+ __asm__ __volatile__("or.l %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_w(mask, v) \
+ __asm__ __volatile__("and.w %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_w(mask, v) \
+ __asm__ __volatile__("or.w %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+
+#define atomic_clear_mask_b(mask, v) \
+ __asm__ __volatile__("and.b %1,%0" : "=m" (*(v)) : "id" (~(mask)),"0"(*(v)))
+
+#define atomic_set_mask_b(mask, v) \
+ __asm__ __volatile__("or.b %1,%0" : "=m" (*(v)) : "id" (mask),"0"(*(v)))
+*/
+
+
+/* Port access routines */
+
+#define readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+/* Arithmetic functions */
+
+#define sat_add_slsl(__x,__y) \
+ __asm__ (" add.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define sat_sub_slsl(__x,__y) \
+ __asm__ (" sub.l %2,%0\n" \
+ " bvc 2f:8\n" \
+ " bpl 1f:8\n" \
+ " mov.l #0x7fffffff:32,%0\n" \
+ " bt 2f:8\n" \
+ "1: mov.l #0x80000000:32,%0\n" \
+ "2:\n" \
+ : "=r"(__x) \
+ : "0" ((long)__x), "r" ((long)__y) : "cc"); \
+
+#define div_us_ulus(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxu.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define div_ss_slss(__x,__y) \
+ ({ \
+ unsigned long __z=(__x); \
+ __asm__ ("divxs.w %2,%0": "=r"(__z) \
+ : "0" (__z), "r" ((unsigned short)(__y)) : "cc"); \
+ (unsigned short)__z; \
+ })
+
+#define muldiv_us(__x,__y,__z) \
+ div_ss_slss((long)(__x)*(__y),__z)
+
+#define muldiv_ss(__x,__y,__z) \
+ div_us_ulus((unsigned long)(__x)*(__y),__z)
+
+/* Power down modes support */
+
+#define __cpu_sleep() __asm__ __volatile__ ("sleep": : : "memory")
+
+/* IRQ handling code */
+
+//#define _USE_EXR_LEVELS 1
+
+#ifdef _USE_EXR_LEVELS
+
+#define __sti() __asm__ __volatile__ ("andc #0xf8,exr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x07,exr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __exr; \
+ __asm__ __volatile__("stc exr,%0":"=m" (__exr) : :"memory"); \
+ (x)=__exr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __exr=(x); \
+ __asm__ __volatile__("ldc %0,exr": :"m" (__exr) :"memory"); \
+ }while(0)
+
+
+#else /* _USE_EXR_LEVELS */
+
+#define __sti() __asm__ __volatile__ ("andc #0x7f,ccr": : : "memory")
+
+#define __cli() __asm__ __volatile__ ("orc #0x80,ccr": : : "memory")
+
+#define __save_flags(x) \
+ do{ \
+ unsigned short __ccr; \
+ __asm__ __volatile__("stc ccr,%0":"=m" (__ccr) : :"memory"); \
+ (x)=__ccr; \
+ }while(0)
+
+#define __restore_flags(x) \
+ do{ \
+ unsigned short __ccr=(x); \
+ __asm__ __volatile__("ldc %0,ccr": :"m" (__ccr) :"cc","memory"); \
+ }while(0)
+
+#endif /* _USE_EXR_LEVELS */
+
+#define __get_vbr(x) 0
+
+#define __get_sp(x) __asm__ __volatile__("mov.l sp,%0":"=r" (x) : :"cc")
+
+#define __memory_barrier() \
+__asm__ __volatile__("": : : "memory")
+
+#define cli() __cli()
+#define sti() __sti()
+
+#define save_flags(x) __save_flags(x)
+#define restore_flags(x) __restore_flags(x)
+#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
+
+#define NR_IRQS 256
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+/*
+
+#if 0
+struct pt_regs {
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long a0;
+ long a1;
+ long a2;
+ long d0;
+ long orig_d0;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#else
+struct pt_regs {
+ long d0;
+ long d1;
+ long d2;
+ long d3;
+ long d4;
+ long d5;
+ long d6;
+ long d7;
+ long a0;
+ long a1;
+ long a2;
+ long a3;
+ long a4;
+ long a5;
+ long a6;
+ unsigned short sr;
+ unsigned long pc;
+ unsigned format : 4;
+ unsigned vector : 12;
+};
+#endif
+
+typedef struct irq_handler {
+ void (*handler)(int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+ struct irq_handler *next;
+} irq_handler_t;
+
+irq_handler_t *irq_array[NR_IRQS];
+void *irq_vec[NR_IRQS];
+
+int add_irq_handler(int vectno,irq_handler_t *handler);
+*/
+
+void *excptvec_get(int vectnum);
+
+void *excptvec_set(int vectnum,void *vect);
+
+int excptvec_initfill(void *fill_vect, int force_all);
+
+#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
+#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
+
+#endif /* _H8S_CPU_DEF_H */
--- /dev/null
+#ifndef _H8S_TYPES_H
+#define _H8S_TYPES_H
+
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+#if __INT_MAX__ == 32767
+typedef __signed__ long __s32;
+typedef unsigned long __u32;
+#else
+typedef int __s32;
+typedef unsigned int __u32;
+#endif
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#ifndef __BIT_TYPES_DEFINED__
+#define __BIT_TYPES_DEFINED__
+
+typedef __u8 uint8_t;
+typedef __s8 int8_t;
+typedef __u16 uint16_t;
+typedef __s16 int16_t;
+typedef __u32 uint32_t;
+typedef __s32 int32_t;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __s64 int64_t;
+typedef __u64 uint64_t;
+#endif
+
+#endif /* !(__BIT_TYPES_DEFINED__) */
+
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef __s8 s8;
+typedef __u8 u8;
+
+typedef __s16 s16;
+typedef __u16 u16;
+
+typedef __s32 s32;
+typedef __u32 u32;
+
+typedef __s64 s64;
+typedef __s64 u64;
+
+#define BITS_PER_LONG 32
+
+#endif /* __KERNEL__ */
+
+#endif /* _H8S_TYPES_H */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = boot
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = boot
+
+boot_SOURCES = boot.c boot_fn.o crt0.S
+
+default_CONFIG = CONFIG_PIC_BOOT_FN=y
+
+INCLUDES = -g
+
+lib_obj_SOURCES = crt0.S
+
+ifeq ($(CONFIG_PIC_BOOT_FN),y)
+
+# FIXME: This doesn't not work. The template is not defined when this
+# files is beeing included. It'is necessary to have a possibility to
+# specify different extension for the output file and diferent
+# cflags. Maybe, we can split Makefile.rules.h8300-boot to two parts,
+# where one would contain definitions only and the second one
+# remaining parts. Then, the Makefile.omk file would be included after
+# the first part and before the second part.
+
+$(warning This feature of special compilation does not work yet.)
+$(eval $(call COMPILE_c_o_template,$(SOURCES_DIR)/boot_fn.c,boot_fn.s1,-f pic -S))
+
+boot_fn.s : boot_fn.s1
+ @$(QUIET_CMD_ECHO) " SED $@"
+ $(Q) sed 's/jsr[^0-z]*@_\([0-9_A-Za-z]*\)\([^0-9_A-Za-z]*\)/bsr _\1:16\2/g' <$< >$@
+
+$(eval $(call COMPILE_S_o_template,$(SOURCES_DIR)/boot_fn.s,boot_fn.o,-f pic -c))
+
+else
+USER_SOURCES += boot_fn.c
+endif # CONFIG_PIC_BOOT_FN
--- /dev/null
+TARGET_ARCH = -ms
+#TARGET_ARCH = -bh8300-coff -ms
+#TARGET_ARCH = -bh8300-coff -ms -mrelax
+#TARGET_ARCH = -bm68k-coff -m68332
+#TARGET_ARCH = -bm68k-elf -m68332
+#TARGET_ARCH = -bi586-mingw32
+
+PIC_BOOT_FN = 1
+
+TOHIT=$(HOME)/h8300/tohit/tohit
+
+BOARD_LAYOUT=id_cpu1
+#BOARD_LAYOUT=edk2638
+
+#CC = gcc
+CC = h8300-coff-gcc
+
+LINK = h8300-coff-ld
+
+CFLAGS += $(TARGET_ARCH)
+CFLAGS += -g
+CFLAGS += -O2 -Wall
+
+CFLAGS += -I. -I../include -I../include/h8s
+
+LDFLAGS += $(TARGET_ARCH)
+LDFLAGS += -nostartfiles
+#LDFLAGS += -nodefaultlibs
+LDFLAGS += --relax
+LDFLAGS += -L../lib
+
+#CFLAGS += -v
+#LDFLAGS += -v
+
+######################################################################
+# New rules
+
+.S.o:
+ $(CC) -D__ASSEMBLY__ $(AFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.c.s:
+ $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -S $< -o $@
+
+######################################################################
+
+all : libfiles boot
+
+dep:
+ $(CC) $(CFLAGS) $(CPPFLAGS) -w -E -M *.c $(MORE_C_FILES) > depend
+
+depend:
+ @touch depend
+
+libfiles : crt0.o ../lib/crt0.o boot_fn.o ../lib/boot_fn.o
+
+crt0.o : crt0.S
+
+../lib/crt0.o : crt0.o
+ cp $< $@
+
+../lib/boot_fn.o : boot_fn.o
+ cp $< $@
+
+ifndef PIC_BOOT_FN
+
+boot_fn.o : boot_fn.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+boot_fn.s : boot_fn.c
+ $(CC) $(CFLAGS) -S -o $@ $<
+
+else
+
+boot_fn.s1 : boot_fn.c
+ $(CC) $(CFLAGS) -fpic -S -o $@ $<
+
+boot_fn.s : boot_fn.s1
+ sed 's/jsr[^0-z]*@_\([0-9_A-Za-z]*\)\([^0-9_A-Za-z]*\)/bsr _\1:16\2/g' <$< >$@
+
+boot_fn.o : boot_fn.s
+ $(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+endif
+
+boot : boot.o boot_fn.o crt0.o
+ $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-boot $^ -o $@
+
+bloader :loader.o boot_fn.o
+ $(CC) $(LDFLAGS) -T $(BOARD_LAYOUT).ld-bload $^ -o $@
+
+boot.bin: boot
+ objcopy --output-target=binary -S boot boot.bin
+
+bloader.bin: bloader
+ objcopy --output-target=binary -S bloader bloader.bin
+
+clean :
+ rm -f *.o
+ rm -f *.bin
+ rm -f boot
+ rm -f bloader
+
--- /dev/null
+#include <types.h>
+#include <cpu_def.h>
+#include <h8s2638h.h>
+#include <system_def.h>
+#include <string.h>
+#include "boot_fn.h"
+
+/*#define USE_FONT_6x8*/
+
+#ifndef HIT_LOAD_BAUD
+ #define HIT_LOAD_BAUD 0
+#endif
+
+void exit(int status)
+{
+ while(1);
+}
+
+extern char __boot_fn_start;
+extern char __boot_fn_end;
+
+void RelocatedProgMode(unsigned long where, unsigned baud)
+{
+ void (*ProgMode_ptr)(unsigned baud);
+ unsigned long reloc_offs=where-(unsigned long)&__boot_fn_start;
+ size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
+ ProgMode_ptr=&ProgMode;
+ (__u8*)ProgMode_ptr+=reloc_offs;
+ memcpy((char*)where,&__boot_fn_start,reloc_size);
+ (*ProgMode_ptr)(baud);
+}
+
+void flash_loader(void)
+{
+ SCIInit(HIT_LOAD_BAUD);
+
+ if((__u8*)&__boot_fn_start<(__u8*)0xff0000)
+ RelocatedProgMode(0xffb000,HIT_LOAD_BAUD);
+ else
+ ProgMode(HIT_LOAD_BAUD);
+}
+
+inline int call_address(unsigned long addr)
+{
+ typedef int (*my_call_t)(void);
+ my_call_t my_call=(my_call_t)addr;
+ return my_call();
+}
+
+int main()
+{
+ /* Internal RAM enabled, advanced interrupt mode */
+ /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
+
+ /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
+ /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
+ /* Sideefect - sets Flash software protection */
+
+ /* Enables access to flash control registers */
+ *IIC_SCRX |= SCRX_FLSHEm;
+
+ /* set shaddow registers */
+ DIO_P1DDR_shaddow=0;
+ DIO_P3DDR_shaddow=0;
+
+ /* deactivate motor and power outputs */
+ #if HW_VER_CODE<VER_CODE(0,2,0)
+ *STPM_OUT=0;
+ *PWRCTRL_OUT=PWRCTRL_BACKLm;
+ #endif /* >=VER_CODE(0,2,0) */
+
+ /* Setup system clock oscilator */
+ /* PLL mode x4, */
+ /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
+ /* PLL mode x2, */
+ /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
+ { const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
+ *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
+ clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
+ }
+ /* No clock disable, immediate change, busmaster high-speed */
+ *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
+
+ #ifdef USE_FONT_6x8
+ /* set 6x8 pixel font */
+ //*DIO_P7DR |=0x10;
+ #else /* USE_FONT_6x8 */
+ /* set 8x8 pixel font */
+ //*DIO_P7DR &=~0x10;
+ #endif /* USE_FONT_6x8 */
+ //SHADDOW_REG_SET(DIO_P7DDR,0x10);
+
+ /* Setup chipselect outputs CS4 CS5 CS6 */
+ //*DIO_P7DR |=1|2|4;
+ //SHADDOW_REG_SET(DIO_P7DDR,1|2|4);
+
+ /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
+ //*DIO_PGDR |=2|4|8|0x10;
+ //SHADDOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
+
+ /* setup chipselect 1 - XRAM */
+ *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
+ *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
+ *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
+
+ /* setup chipselect 2 - SGM_LCD */
+ *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
+ *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
+ *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
+
+ /* setup chipselect 3 - SRAM */
+ *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
+ *BUS_WCRL&=~(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
+
+ /* setup chipselect 4 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
+
+ /* setup chipselect 5 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
+
+ /* setup chipselect 6 - KL41 */
+ *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
+ *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
+
+ /* crross cs wait| rd/wr wait | no burst and DRAM */
+ *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
+ /* release | no DMAC buffer | no external wait */
+ /* **************************************************** */ //*BUS_BCRL=0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm;
+ *DIO_PCDDR=0xff; /* A0-A7 are outputs */
+ *DIO_PBDDR=0xff; /* A8-A15 are outputs */
+ /* Setup full 20 address lines */
+ *DIO_PADR|=0x0f;
+ *DIO_PADDR=0x0f; /* A16-A19 are outputs */
+ /* number of address output signals */
+ *SYS_PFCR=__val2mfld(PFCR_AExm,20-8);
+
+ /* Stop all modules */
+ *SYS_MSTPCRA=0xff;
+ *SYS_MSTPCRB=0xff;
+ *SYS_MSTPCRC=0xff;
+
+ /*set power on for SCI4 module*/
+ *SYS_MSTPCRC&=~MSTPCRC_SCI4m;
+
+ /* show something on debug leds */
+ *DIO_P1DR=0xf-1;
+ SHADDOW_REG_SET(DIO_P1DDR,0x0f);
+
+ /* Disable SCI 2 */
+ /* Off TxD2 on Port PA.1 */
+ /* Off RxD2 on Port PA.2 */
+ *SCI_SCR2=0;
+ *DIO_PADR|=0x06;
+ *DIO_PADDR=0x01;
+ *SCI_SMR2=0;
+
+ /* Stop SCI4 communication */
+ // SCI4 is not aviable
+ //*SCI_SCR4=0;
+ //*SCI_SMR4=0;
+
+ /* Output TxD4 on Port P3.7, TxD0 on P3.0 */
+ /* RTS4 on Port P3.2 */
+ /* Input RxD4 on Port P3.6, RxD0 on P3.1 */
+ /* CTS4 on Port P3.3 */
+ *DIO_P3DR|=0xc5;
+ SHADDOW_REG_SET(DIO_P3DDR,0x85);
+
+ /* Enables access to flash control registers */
+ *IIC_SCRX |= SCRX_FLSHEm;
+
+ if(((*FLM_FLMCR1) & FLMCR1_FWEm)!=0){
+ flash_loader();
+ }
+
+ if (*((unsigned long *)0x4000)!=0xffffffff){
+ call_address(0x4000);
+ }
+
+ if (*((unsigned long *)0x200000)==0xff0055aa){
+ call_address(0x200004);
+ }
+
+ flash_loader();
+ return 0;
+};
--- /dev/null
+#include <types.h>
+#include <cpu_def.h>
+#include <system_def.h>
+//#include <h8s2633h.h>
+#include <h8s2638h.h>
+#include "boot_fn.h"
+
+#undef WITH_EXTERNAL_FLASH
+
+#if 1
+ #define DEB_WR_HEX(...)
+#else
+ #define DEB_WR_HEX(_hex,_digs) deb_wr_hex(_hex,_digs);
+ void deb_wr_hex(long hex, short digs);
+#endif
+
+#if 1
+ #define DEB_BLOG_INIT
+ #define DEB_BLOG(...)
+#else
+ #define DEB_BLOG_INIT do{ *(long*)0x280000=0x280000+4; } while(0)
+ #define DEB_BLOG(_val) do{ *((*(long**)0x280000)++)=_val; } while(0)
+#endif
+
+#ifdef WITH_EXTERNAL_FLASH
+ #define EXTERNAL_FLASH_START 0x40000
+ #define EXTERNAL_FLASH_END (0x40000+0xfffff)
+ int ExtFlProgRow(__u8 *addr, __u8 *data);
+ int ExtFlErase(__u8 *addr);
+#endif /*WITH_EXTERNAL_FLASH*/
+
+
+/* Enable watchdog with selected system clock prescaller */
+/* 2, 64, 128, 512, 2048, 8192, 32768, 131072 */
+void wdg_enable(int psel)
+{
+ /* Enable power-on reset of WDT owerflow */
+ *WDT_WRSTCSRw=(0x5a00 | 1*WRSTCSR_RSTEm | 0*WRSTCSR_RSTSm);
+ /* Select watchdog function and input clocks */
+ *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm |(psel & WTCSR0_CKSxm));
+ *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm | 1*WTCSR0_TMEm | (psel & WTCSR0_CKSxm));
+}
+
+/* Disable watchdog */
+void wdg_disable()
+{
+ *WDT_WTCSR0w=(0xa500);
+}
+
+/* Clear watchdog */
+void wdg_clear()
+{
+ *WDT_WTCNT0w=(0x5a00);
+}
+
+#define TO_TEXT __attribute__ ((section (".text")))
+
+#define PIC_ADR(_ptr,_var) \
+ { \
+ __asm__ ( \
+ "bsr 1f\n" \
+ "1:\tmov.l @sp+,%0\n" \
+ "\tadd.l %1-1b,%0\n" \
+ : "=r" (_ptr) : "i" (&(_var)) : "cc" \
+ ); \
+ }
+
+static const unsigned long
+ flash_blocks[] TO_TEXT =
+ {0x00000,0x01000,0x02000,0x03000,0x04000,0x05000,0x06000,0x07000,
+ 0x08000,0x10000,0x20000,0x30000,0x40000,0};
+
+static const int
+ flash_block_count TO_TEXT =
+ sizeof(flash_blocks)/sizeof(unsigned long)-2;
+
+#if 0
+volatile void FlWait(long n)
+{
+ long i=0;
+ volatile long x;
+ while (i<n*6){
+ i++;
+ x+=i;
+ }
+}
+#else
+volatile void FlWait(long n);
+
+__asm__ (
+".global _FlWait\n"
+"_FlWait:\n"
+#if (CPU_SYS_HZ>16000000)
+" shll.l er0"
+#endif
+" mov.w #1,r1\n"
+" bra 2f:8\n"
+"1: dec.w #1,r1\n"
+" bne 1b:8\n"
+" nop\n"
+" mov.w #2,r1\n"
+"2: dec.l #1,er0\n"
+" bne 1b:8\n"
+" rts\n"
+);
+
+#endif
+
+int FlAdr2Blk(unsigned long adr)
+{
+ int bl=0;
+ unsigned long *blocks;
+ PIC_ADR(blocks,flash_blocks[0]);
+
+ if(adr<blocks[0]) return -1;
+ while(blocks[bl+1]){
+ if(adr<blocks[bl+1]) return bl;
+ bl++;
+ }
+ return -1;
+}
+
+/* Check if block number is blank */
+int FlTest(int bl)
+{
+ __u16 *p, *pe;
+ unsigned long *blocks;
+ PIC_ADR(blocks,flash_blocks[0]);
+
+ if(bl>=flash_block_count) return -2;
+ if(bl<0) return -2;
+
+ /* No software control over Flash/External select */
+ /* *BCRL=(*BCRL & (EAE ^ 0x0ff)); */
+
+ p=(__u16*)blocks[bl];
+ pe=(__u16*)blocks[bl+1];
+ while(p<pe){
+ *p=0xffff;
+ FlWait(2);
+ if (*p!=0xffff) return -1;
+ p++;
+ }
+ return 0;
+}
+
+/* Erase block number */
+int FlErase(int bl)
+{
+ int n=100; /*N*/
+ if(bl>=flash_block_count) return -4;
+ if(bl<0) return -5;
+
+ if(FlTest(bl)==0) return 0;
+
+ if((*FLM_FLMCR1 & FLMCR1_FWEm)==0) return -1;
+
+ *FLM_FLMCR1=FLMCR1_SWE1m;
+ FlWait(1); /*x*/
+ if(bl<8){
+ *FLM_EBR1=(1 << bl);
+ *FLM_EBR2=0;
+ }else{
+ *FLM_EBR1=0;
+ *FLM_EBR2=(1 << (bl-8));
+ }
+ while(n>0){
+ n--;
+ if(*FLM_FLMCR2 & FLMCR2_FLERm) goto fls_error;
+ wdg_enable(4+1);
+ *FLM_FLMCR1|=FLMCR1_ESU1m;
+ FlWait(100); /*y*/
+ *FLM_FLMCR1|=FLMCR1_E1m;
+ FlWait(5000); /*z=max10000*/
+ *FLM_FLMCR1&=~FLMCR1_E1m;
+ FlWait(10); /*alpha*/
+ *FLM_FLMCR2&=~FLMCR1_ESU1m;
+ FlWait(10); /*betha*/
+ wdg_disable();
+ if(*FLM_FLMCR2 & FLMCR2_FLERm) goto fls_error;
+ *FLM_FLMCR1|=FLMCR1_EV1m;
+ FlWait(6); /*gamma*/
+ if(FlTest(bl)==0){
+ *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear EV1*/
+ FlWait(4); /*ny*/
+ *FLM_FLMCR1=0;
+ return 0;
+ }
+ *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear EV1*/
+ FlWait(4); /*ny*/
+ }
+ *FLM_FLMCR1=0;
+ FlWait(100); /*x1*/
+ return -2;
+
+ fls_error:
+ *FLM_FLMCR1=0;
+ return -3;
+}
+
+void FlProgPulse(int time_zx)
+{
+ wdg_enable(3+1);
+ *FLM_FLMCR1|=FLMCR1_PSU1m;
+ FlWait(50); /*y*/
+ *FLM_FLMCR1|=FLMCR1_P1m;
+ FlWait(time_zx); /*z0,z1 or z2*/
+ *FLM_FLMCR1&=~FLMCR1_P1m;
+ FlWait(5); /*alpha*/
+ *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear PSU1*/
+ FlWait(5); /*betha*/
+ wdg_disable();
+}
+
+/* Program data to address */
+int FlProgRow(__u8 *adr, __u8 *data)
+{
+ __u8 prog_data[FLASH_ROW];
+ int i;
+ int m;
+ int n;
+ __u8 *x;
+ __u8 c,d;
+ if((unsigned long)adr & (FLASH_ROW-1)) return -6;
+ if((*FLM_FLMCR1 & FLMCR1_FWEm)==0 ) return -5;
+ #ifdef WITH_EXTERNAL_FLASH
+ if(((__u32)adr>=EXTERNAL_FLASH_START)&&
+ ((__u32)adr<=EXTERNAL_FLASH_END)){
+ return ExtFlProgRow(adr,data);
+ }
+ #endif /*WITH_EXTERNAL_FLASH*/
+
+ x=adr;
+ for(i=FLASH_ROW;i--;x++){
+ if(*x!=0xff) return -4;
+ }
+ x=data;
+ for(i=0;i<FLASH_ROW;i++,x++) prog_data[i]=*x;
+
+ *FLM_FLMCR1=FLMCR1_SWE1m;
+ FlWait(1); /*x0*/
+
+ n=0;
+ while(n<100){ /*N1+N2<1000*/
+ n++;
+ m=0;
+ i=0;
+ x=adr;
+ for(i=0;i<FLASH_ROW;i++,x++) *x=prog_data[i];
+
+ FlProgPulse(n>6?150:25); /*z0<30 or z2<200 if n>N1*/
+
+ *FLM_FLMCR1|=FLMCR1_PV1m;
+ FlWait(4); /*gamma*/
+ i=0;
+ x=adr;
+ for(i=0;i<FLASH_ROW;i+=2,x+=2){
+ *(__u16*)x=0xffff;
+ FlWait(2); /*epsilon*/
+ *(__u16*)(prog_data+i)=*(__u16*)x;
+ }
+ *FLM_FLMCR1&=FLMCR1_SWE1m; /*clear PV1*/
+ FlWait(2); /*ny*/
+ if(n<=6){ /*N1*/
+ x=adr;
+ for(i=0;i<FLASH_ROW;i++,x++){
+ c=prog_data[i];
+ d=data[i];
+ if((~c&d)&0xff) goto fls_error;
+ if(c!=d) {
+ m=1;
+ /* DEB_BLOG(0xEE000000+(long)x); */
+ /* DEB_BLOG(0xEF000000+(__u16)(c<<8)+(__u8)d); */
+ }
+ *x=d|c;
+ prog_data[i]=d|~c;
+ }
+
+ FlProgPulse(7); /*z1<10*/
+
+ }else{
+ for(i=0;i<FLASH_ROW;i++){
+ c=prog_data[i];
+ d=data[i];
+ if(c!=d) m=1;
+ if((~c&d)&0xff) goto fls_error;
+ prog_data[i]=d|~c;
+ }
+ }
+ if(m==0){
+ *FLM_FLMCR1=0;
+ FlWait(100); /*x1*/
+ DEB_BLOG(0xED000000+n);
+ return 0;
+ }
+ }
+ *FLM_FLMCR1=0;
+ FlWait(100); /*x1*/
+ return -1;
+
+ fls_error:
+ *FLM_FLMCR1=0;
+ return -3;
+}
+
+int FlPrepBlk(unsigned long badr, unsigned long len)
+{
+ int bl, blend, res;
+ bl=FlAdr2Blk(badr);
+ blend=FlAdr2Blk(badr+len-1);
+ if((bl<0)||(blend<0)) return -8;
+ for(;bl<=blend;bl++){
+ if(FlTest(bl)){
+ res=FlErase(bl);
+ if(res<0) return res;
+ }
+ }
+ return 0;
+}
+
+
+#if 0
+#define RS232_TDR SCI_TDR4
+#define RS232_RDR SCI_RDR4
+#define RS232_SMR SCI_SMR4
+#define RS232_SCMR SCI_SCMR4
+#define RS232_SCR SCI_SCR4
+#define RS232_SSR SCI_SSR4
+#define RS232_BRR SCI_BRR4
+#define RS232_RXD_PIN ((*DIO_PORT3)&(1<<6))
+
+#elif 0
+#define RS232_TDR SCI_TDR2
+#define RS232_RDR SCI_RDR2
+#define RS232_SMR SCI_SMR2
+#define RS232_SCMR SCI_SCMR2
+#define RS232_SCR SCI_SCR2
+#define RS232_SSR SCI_SSR2
+#define RS232_BRR SCI_BRR2
+#define RS232_RXD_PIN ((*DIO_PORTA)&(1<<2))
+
+#else
+#define RS232_TDR SCI_TDR1
+#define RS232_RDR SCI_RDR1
+#define RS232_SMR SCI_SMR1
+#define RS232_SCMR SCI_SCMR1
+#define RS232_SCR SCI_SCR1
+#define RS232_SSR SCI_SSR1
+#define RS232_BRR SCI_BRR1
+#define RS232_RXD_PIN ((*DIO_PORT3)&(1<<4))
+#endif
+
+#define RS232_BAUD_RAW 0xff00
+
+int SCIInit(unsigned baud)
+{
+ unsigned divisor;
+ char cks;
+
+ /*disable SCI interrupts and Rx/Tx machine*/
+ *RS232_SCR=0;
+
+ cks=0;
+ if((baud&RS232_BAUD_RAW)!=RS232_BAUD_RAW){
+ divisor=div_us_ulus((CPU_SYS_HZ/16),baud);
+ while(divisor>=512){
+ if(++cks>=4) return -1;
+ divisor>>=1;
+ }
+ divisor=(divisor+1)>>1;
+ }else{
+ divisor=baud&0xff;
+ }
+ *RS232_BRR=divisor-1;
+
+ *RS232_SMR=(SMR_CKSxm&cks);
+ *RS232_SCMR=0;
+ FlWait(20000);
+ *RS232_SCR=SCR_TEm|SCR_REm;
+ return 0;
+}
+
+volatile int SCISend(unsigned char c)
+{
+ unsigned int i=50000;
+ while((*RS232_SSR & SSR_TDREm)==0 && i>0) i--;
+ if (i==0) return -1;
+ *RS232_TDR=c;
+ *RS232_SSR=~SSR_TDREm&0xff;
+ return 0;
+}
+
+volatile int SCIReceive(unsigned char *c,unsigned int time)
+{
+ unsigned char ssr;
+ if(time){
+ while(!((ssr=*RS232_SSR) & SSR_RDRFm) && ((time--)>0))
+ if(ssr&(SSR_ORERm|SSR_FERm)) break;
+ if (time==0) return -1;
+ }
+ else{
+ while(!((ssr=*RS232_SSR) & SSR_RDRFm))
+ if(ssr&(SSR_ORERm|SSR_FERm)) break;
+ }
+ *c=*RS232_RDR;
+ *RS232_SSR=~(SSR_RDRFm|SSR_MPBTm);
+ if(ssr & (SSR_ORERm|SSR_FERm)){
+ *RS232_SSR=~(SSR_ORERm|SSR_FERm|SSR_MPBTm);
+ return -2;
+ }
+ return 0;
+}
+
+unsigned long GetAdr()
+{
+ unsigned char c;
+ unsigned long a;
+ SCIReceive(&c,0);
+ a=((unsigned long)c << 24);
+ SCIReceive(&c,0);
+ a=a | (((unsigned long)c << 16) & 0xff0000);
+ SCIReceive(&c,0);
+ a=a | (((unsigned long)c << 8) & 0xff00);
+ SCIReceive(&c,0);
+ a=a | ((unsigned long)c & 0xff);
+ SCISend((a >> 24) & 0xFF);
+ SCISend((a >> 16) & 0xFF);
+ SCISend((a >> 8) & 0xFF);
+ SCISend(a & 0xFF);
+ return a;
+}
+
+int SCIAutoBaud(void)
+{
+ int t;
+ unsigned char wtn;
+
+ /* Disable power-on reset of WDT owerflow */
+ *WDT_WRSTCSRw=(0x5a00 | 1*WRSTCSR_RSTEm | 0*WRSTCSR_RSTSm);
+ /* Select watchdog function and input clocks */
+ *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm |(1 & WTCSR0_CKSxm));
+ *WDT_WTCSR0w=(0xa500 | 1*WTCSR0_WTITm | 1*WTCSR0_TMEm | (1 & WTCSR0_CKSxm));
+
+ while(!RS232_RXD_PIN) *WDT_WTCNT0w=(0x5a00);
+ while(RS232_RXD_PIN) *WDT_WTCNT0w=(0x5a00);
+
+ t=0;
+ while(1){
+ wtn=*WDT_WTCNT0r;
+ if(wtn>0xf0){
+ *WDT_WTCNT0w=(0x5a00);
+ t+=0xf0;
+ }
+ if(RS232_RXD_PIN){
+ t+=wtn;
+ break;
+ }
+ };
+
+ /* Disable watchdog */
+ *WDT_WTCSR0w=(0xa500);
+
+ SCIInit(((t*2+7)/9)|RS232_BAUD_RAW);
+
+ return t;
+}
+
+#ifdef WITH_EXTERNAL_FLASH
+
+#define EXTFL_addr_mask 0x0ffffl
+#define EXTFL_reg1_addr (0x555*2l)
+#define EXTFL_reg2_addr (0x2aa*2l)
+#define EXTFL_sec_size 0x10000
+#define EXTFL_width8 0
+#define EXTFL_cmd_unlock1 0xaaaa /* reg1 */
+#define EXTFL_cmd_unlock2 0x5555 /* reg2 */
+#define EXTFL_cmd_rdid 0x9090 /* reg1 */
+#define EXTFL_cmd_prog 0xa0a0 /* reg1 */
+#define EXTFL_cmd_erase 0x8080 /* reg1 */
+#define EXTFL_cmd_reset 0xf0f0 /* any */
+#define EXTFL_erase_all 0x1010 /* reg1 */
+#define EXTFL_erase_sec 0x3030 /* sector */
+#define EXTFL_fault_bit 0x2020
+#define EXTFL_manid 1
+#define EXTFL_devid 0x2258
+
+#define FLASH_WR16(addr,val) (*(volatile __u16*)(addr)=(val))
+#define FLASH_RD16(addr) (*(volatile __u16*)(addr))
+
+/* Program data to address */
+int ExtFlProgRow(__u8 *addr, __u8 *data)
+{
+ /*FLASH_ROW*/;
+ int ret=0;
+ int cnt=FLASH_ROW/2;
+ __u16 old,new,val;
+ __u32 a=(__u32)addr&~EXTFL_addr_mask;
+ while(cnt--){
+ val=*((__u16*)data)++;
+ /* security sequence */
+ FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_unlock1);
+ FlWait(2);
+ FLASH_WR16(a+EXTFL_reg2_addr,EXTFL_cmd_unlock2);
+ FlWait(2);
+ /* program command */
+ FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_prog);
+ FlWait(2);
+ FLASH_WR16(addr,val);
+ FlWait(2);
+ /* wait for result */
+ old=FLASH_RD16(addr);
+ FlWait(2);
+ while((new=FLASH_RD16(addr))!=old){
+ FlWait(2);
+ if((old&EXTFL_fault_bit)&&(new&EXTFL_fault_bit)){
+ if((FLASH_RD16(addr))!=new) ret=-2;
+ break;
+ }
+ old=new;
+ }
+ /* reset */
+ FLASH_WR16(a,EXTFL_cmd_reset);
+ FlWait(2);
+ if(FLASH_RD16(addr)!=val) return -3;
+ ((__u16*)addr)++;
+ }
+ return 0;
+}
+
+int ExtFlErase(__u8 *addr)
+{
+ __u16 old,new;
+ int ret=0;
+ __u32 a=(__u32)addr&~EXTFL_addr_mask;
+ /* security sequence */
+ FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_unlock1);
+ FlWait(2);
+ FLASH_WR16(a+EXTFL_reg2_addr,EXTFL_cmd_unlock2);
+ FlWait(2);
+ /* erase command */
+ FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_erase);
+ FlWait(2);
+ /* security sequence */
+ FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_cmd_unlock1);
+ FlWait(2);
+ FLASH_WR16(a+EXTFL_reg2_addr,EXTFL_cmd_unlock2);
+ FlWait(2);
+ /* select erase range */
+ a=(__u32)addr;
+ FLASH_WR16(a+EXTFL_reg1_addr,EXTFL_erase_all);
+ FlWait(2);
+ old=FLASH_RD16(addr);
+ FlWait(2);
+ while((new=FLASH_RD16(addr))!=old){
+ FlWait(2);
+ if((old&EXTFL_fault_bit)&&(new&EXTFL_fault_bit)){
+ if((FLASH_RD16(addr))!=new) ret=-2;
+ break;
+ }
+ old=new;
+ }
+ /* reset */
+ FLASH_WR16(a,EXTFL_cmd_reset);
+ FlWait(2);
+ if(FLASH_RD16(addr)!=0xffff) ret--;
+ return ret;
+}
+
+#endif /*WITH_EXTERNAL_FLASH*/
+
+void Call(unsigned long adr)
+{
+ __asm__ /*__volatile__*/(
+ "jsr @%0\n\t"
+ :
+ :"g" (adr)
+ :"memory","cc");
+}
+
+void ProgMode(unsigned baud)
+{
+ char buf[FLASH_ROW];
+ unsigned long i;
+ unsigned long j;
+ unsigned char e;
+ unsigned char c;
+ unsigned char d;
+ unsigned char cmd;
+ unsigned long badr;
+ unsigned long len;
+ unsigned char *adr;
+
+ DEB_BLOG_INIT;
+ if(baud) SCIInit(baud);
+ while(1){
+ if(!baud) SCIAutoBaud();
+ SCIReceive(&c,0);
+ while(c!=0x55){
+ SCISend(0); /*c*/
+ SCIReceive(&c,0);
+ }
+ SCISend(0xAA);
+ SCIReceive(&cmd,0);
+ DEB_WR_HEX(cmd,2); /*!!!*/
+ if((cmd & 7) == (((cmd >> 3) & 7) ^ 7)){
+ SCISend(cmd | 0x80);
+ cmd&=7;
+ if((cmd<=2)||(cmd==4)){
+ /* memory download/upload/erase region */
+ badr=GetAdr();
+ len=GetAdr();
+ if(cmd==0){
+ /* memory download */
+ e=0x5a;
+ i=0;
+ DEB_WR_HEX(badr,8); /*!!!*/
+ DEB_WR_HEX(len,8); /*!!!*/
+ adr=(unsigned char *)badr;
+ while(i++<len){
+ if(SCIReceive(&c,0)<0){
+ e=0xfd;
+ break;
+ }
+ *adr=c;
+ SCISend(*adr);
+ adr++;
+ }
+ SCISend(e);
+ }
+ else if (cmd==1){
+ /* flash programming */
+ /* check and erase range */
+ /*if(FlPrepBlk(badr,len)<0) e=0xfc;*/
+ i=badr-(badr & 0xffffffe0);
+ j=0;
+ e=0x5a;
+ while((i--)>0){
+ buf[j++]=0xff;
+ }
+ adr=(unsigned char *)(badr & ~(FLASH_ROW-1));
+ j=(unsigned char *)badr-adr;
+ i=0;
+ while(i++<len){
+ if(SCIReceive(&c,0)<0){
+ e=0xfd;
+ break;
+ }
+ buf[j++]=c;
+ if(j==FLASH_ROW){
+ DEB_WR_HEX((long)adr,6); /*!!!*/
+ if((j=FlProgRow(adr,buf))!=0) e=0xff;
+ DEB_BLOG(0xEA000000|(__u32)adr|((__u8)j&0x7f));
+ DEB_WR_HEX(j,2); /*!!!*/
+ adr+=FLASH_ROW;
+ j=0;
+ }
+ SCISend(c);
+ }
+ if(j/*&&!(e&0x80)*/){
+ while(j<FLASH_ROW) buf[j++]=0xff;
+ if(FlProgRow(adr,buf)!=0) e=0xff;
+ }
+ SCISend(e);
+ }else if (cmd==4){
+ /* check and erase region */
+ e=FlPrepBlk(badr,len);
+ if(!e) e=0x5a;
+ SCISend(e);
+ }else{
+ /* upload memory */
+ i=0;
+ e=0x5a;
+ DEB_WR_HEX(badr,8); /*!!!*/
+ DEB_WR_HEX(len,8); /*!!!*/
+ adr=(unsigned char *)badr;
+ while(i++<len){
+ d=*adr;
+ SCISend(d);
+ if(SCIReceive(&c,0)<0){
+ e=0xfd;
+ break;
+ }
+ if(c!=d) e=0xff;
+ adr++;
+ }
+ SCISend(e);
+ }
+ }else{
+ /* erase block */
+ if(cmd==3){
+ SCIReceive(&c,0);
+ if (c<flash_block_count){
+ if(FlErase(c)==0) SCISend(0x5A);
+ else SCISend(0xFF);
+ #ifdef WITH_EXTERNAL_FLASH
+ }else if(c==100){
+ if(ExtFlErase((__u8*)EXTERNAL_FLASH_START)==0)
+ SCISend(0x5A); else SCISend(0xFF);
+ #endif /*WITH_EXTERNAL_FLASH*/
+ }else SCISend(0xFE);
+ }
+ else if (cmd==6){
+ badr=GetAdr();
+ DEB_WR_HEX(badr,8); /*!!!*/
+ Call(badr);
+ }
+ else if (cmd==7){
+ wdg_enable(1+1);
+ }
+ else{
+ SCISend(0xFF);
+ }
+ }
+ }else{
+ SCISend(0xFE);
+ }
+ }
+}
--- /dev/null
+#ifndef _boot_fn_H
+#define _boot_fn_H
+
+#define FLASH_ROW 128
+
+volatile void FlWait(long n);
+void wdg_enable(int psel);
+void wdg_disable();
+void wdg_clear();
+int FlTest(int bl);
+int FlErase(int bl);
+int FlProgRow(__u8 *adr, __u8 *data);
+int SCIAutoBaud(void);
+int SCIInit(unsigned baud);
+volatile int SCISend(unsigned char c);
+volatile int SCIReceive(unsigned char *c,unsigned int time);
+unsigned long GetAdr();
+void ProgMode(unsigned baud);
+
+#endif /* _boot_fn_H */
--- /dev/null
+
+#if defined(__H8300H__)
+ .h8300h
+#endif
+#if defined(__H8300S__)
+ .h8300s
+#endif
+
+.text
+
+.align 2
+
+.global usrprog_start
+/*.global _exit*/
+.global _start
+
+_start :
+ mov.l #___stack_top,sp
+ mov.l #___data_lma,er5
+ mov.l #_data_start,er6
+ cmp.l er5,er6
+ beq 5f
+ mov.l #_edata,er4
+ sub.l er6,er4 /* transfer data from lma to vma */
+ beq 5f
+2: eepmov.w /* R4 * @er5 -> @er6 */
+ mov.w r4,r4 /* for interrupted transfers */
+ bne 2b
+ dec.w #1,e4
+ bpl 2b
+5: mov.l #_bss_start,er4
+ mov.l #_end,er6
+ sub.l er6,er4
+ neg.l er4
+ sub.w r5,r5
+ dec #2,er4
+ bmi 8f
+6: mov.w r5,@-er6 /* clear bss */
+7: dec #2,er4
+ bpl 6b
+8:
+
+#if 0
+ /* Zero rest of the RAM */
+ mov.l #_end,er4
+ mov.l #___heap_end+1,er6
+ and.l #-2,er6
+ sub.l er6,er4
+ neg.l er4
+ sub.w r5,r5
+ /*mov.w #0xffff,r5*/
+1: mov.w r5,@-er6 /* clear heap */
+ dec #2,er4
+ bgt 1b
+2:
+#endif
+
+ /* Run main and exit */
+ mov.l sp,fp
+ jsr _main
+ mov.w r0,@-sp
+ jsr _exit
+1: bra 1b
+
+.end
--- /dev/null
+#include <types.h>
+#include <cpu_def.h>
+#include <system_def.h>
+//#include <h8s2633h.h>
+#include <h8s2639h.h>
+#include "boot_fn.h"
+
+/* hack for start of main, should use crt0.o instead */
+__asm__ /*__volatile__*/(
+ ".global _start\n\t"
+ "_start : \n\t"
+ "mov.l #0xffdffe,sp\n\t"
+ "jsr _main\n\t"
+ );
+
+void exit(int status)
+{
+ while(1);
+}
+
+#define RS232_RXD_PIN ((*DIO_PORT3)&(1<<6))
+
+int main()
+{
+ /* Disable SCI 2 */
+ /* Off TxD2 on Port PA.1 */
+ /* Off RxD2 on Port PA.2 */
+ *SCI_SCR2=0;
+ #ifndef FULL_XRAM_ADRBUS
+ *DIO_PADR|=0x06;
+ *DIO_PADDR=0x01;
+ #endif /* FULL_XRAM_ADRBUS */
+
+ /*set power on for SCI4 module*/
+ *SYS_MSTPCRC&=~MSTPCRC_SCI4m;
+
+ /* Output TxD4 on Port P3.7 */
+ /* Input RxD4 on Port P3.6 */
+ *DIO_P3DR|=0xc0;
+ SHADDOW_REG_SET(DIO_P3DDR,0x80);
+
+ ProgMode(0);
+
+ return 0;
+};
+
+
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+SUBDIRS = defines
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ CVUT FEL.
+
+ h8s2639h.h - internal peripherals registers of H8S2630,H8S2636,
+ H8S2638,H8S2639
+ internal comment: ver 1.1
+ *******************************************************************/
+
+#ifndef _H82639H_H
+#define _H82639H_H
+
+#ifndef __ASSEMBLY__
+
+#include <types.h>
+
+#define __PORT8 (volatile __u8 * const)
+#define __PORT16 (volatile __u16 * const)
+#define __PORT32 (volatile __u32 * const)
+
+#else /* __ASSEMBLY__ */
+#define __PORT8
+#define __PORT16
+#define __PORT32
+#endif /* __ASSEMBLY__ */
+
+/* Module DTC */
+//#define DTC_MRA __PORT8 0x????? /* DTC Mode Register A */
+//#define MRA_SZm 0x01
+//#define MRA_DTSm 0x02
+//#define MRA_MD0m 0x04
+//#define MRA_MD1m 0x08
+//#define MRA_DM0m 0x10
+//#define MRA_DM1m 0x20
+//#define MRA_SM0m 0x40
+//#define MRA_SM1m 0x80
+//#define DTC_MRB __PORT8 0x???? /* DTC Mode Register B */
+//#define MRB_DISELm 0x40
+//#define MRB_CHNEm 0x80
+//#define DTC_SAR __PORT?? 0x???? /* DTC Source Address Register */
+//#define DTC_DAR __PORT?? 0x???? /* DTC Destination Address Register */
+//#define DTC_CRA __PORT16 0x???? /* DTC Transfer Count Register A */
+//#define DTC_CRB __PORT16 0x???? /* DTC Transfer Count Register B */
+
+/* Module HCAN1 and HCAN2 */
+#define HCAN0_MRC __PORT8 0xFFF800 /* HCAN0 Master Control Register */
+#define HCAN1_MCR __PORT8 0xFFFA00 /* HCAN1 Master Control Register */
+#define MCR_MCR0m 0x01
+#define MCR_MCR1m 0x02
+#define MCR_MCR2m 0x04
+#define MCR_MCR5m 0x20
+#define MCR_MCR7m 0x80
+#define HCAN0_GSR __PORT8 0xFFF801 /* HCAN0 General Status Register */
+#define HCAN1_GSR __PORT8 0xFFFA01 /* HCAN1 General Status Register */
+#define GSR_GSR0m 0x01
+#define GSR_GSR1m 0x02
+#define GSR_GSR2m 0x04
+#define GSR_GSR3m 0x08
+#define HCAN0_BCR __PORT16 0xFFF802 /* HCAN0 Bit Configuration Register */
+#define HCAN1_BCR __PORT16 0xFFFA02 /* HCAN1 Bit Configuration Register */
+#define HCAN0_MBCR __PORT16 0xFFF804 /* HCAN0 Mailbox Configuration Register */
+#define HCAN1_MBCR __PORT16 0xFFFA04 /* HCAN1 Mailbox Configuration Register */
+#define HCAN0_TXPR __PORT16 0xFFF806 /* HCAN0 Transmit Wait Register */
+#define HCAN1_TXPR __PORT16 0xFFFA06 /* HCAN1 Transmit wait register */
+#define HCAN0_TXCR __PORT16 0xFFF808 /* HCAN0 Transmit wait cancel register */
+#define HCAN1_TXCR __PORT16 0xFFFA08 /* HCAN1 Transmit wait cancel register */
+#define HCAN0_TXACK __PORT16 0xFFF80A /* HCAN0 Transmit Acknowledge Register */
+#define HCAN1_TXACK __PORT16 0xFFFA0A /* HCAN1 Transmit Acknowledge Register */
+#define HCAN0_ABACK __PORT16 0xFFF80C /* HCAN0 Abort Acknowledge Register */
+#define HCAN1_ABACK __PORT16 0xFFFA0C /* HCAN1 Abort Acknowledge Register */
+#define HCAN0_RXPR __PORT16 0xFFF80E /* HCAN0 Receive Complete Register */
+#define HCAN1_RXPR __PORT16 0xFFFA0E /* HCAN1 Receive Complete Register */
+#define HCAN0_RFPR __PORT16 0xFFF810 /* HCAN0 Remote Request Register */
+#define HCAN1_RFPR __PORT16 0xFFFA10 /* HCAN1 Remote Request Register */
+#define HCAN0_IRR __PORT16 0xFFF812 /* HCAN0 Interrupt Register */
+#define HCAN1_IRR __PORT16 0xFFFA12 /* HCAN1 Interrupt Register */
+#define HCAN0_IRRL __PORT8 0xFFF812 /* HCAN0 Interrupt Register L */
+#define HCAN1_IRRL __PORT8 0xFFFA12 /* HCAN1 Interrupt Register L */
+#define IRRL_IRR0m 0x01
+#define IRRL_IRR1m 0x02
+#define IRRL_IRR2m 0x04
+#define IRRL_IRR3m 0x08
+#define IRRL_IRR4m 0x10
+#define IRRL_IRR5m 0x20
+#define IRRL_IRR6m 0x40
+#define IRRL_IRR7m 0x80
+#define HCAN0_IRRH __PORT8 0xFFF813 /* HCAN0 Interrupt Register H */
+#define HCAN1_IRRH __PORT8 0xFFFA13 /* HCAN0 Interrupt Register H */
+#define IRRH_IRR8m 0x01
+#define IRRH_IRR9m 0x02
+#define IRRH_IRR12m 0x10
+#define HCAN0_MBIMR __PORT16 0xFFF814 /* HCAN0 Mailbox Interrupt Mask Register */
+#define HCAN1_MBIMR __PORT16 0xFFFA14 /* HCAN1 Mailbox Interrupt Mask Register */
+#define HCAN0_IMR __PORT16 0xFFF816 /* HCAN0 Interrupt Mask Register */
+#define HCAN1_IMR __PORT16 0xFFFA16 /* HCAN1 Interrupt Mask Register */
+#define HCAN0_IMRL __PORT8 0xFFF816 /* HCAN0 Interrupt Mask Register L */
+#define HCAN1_IMRL __PORT8 0xFFFA16 /* HCAN1 Interrupt Mask Register L */
+#define IMRL_IMR1m 0x02
+#define IMRL_IMR2m 0x04
+#define IMRL_IMR3m 0x08
+#define IMRL_IMR4m 0x10
+#define IMRL_IMR5m 0x20
+#define IMRL_IMR6m 0x40
+#define IMRL_IMR7m 0x80
+#define HCAN0_IMRH __PORT8 0xFFF817 /* HCAN0 Interrupt Mask Register H */
+#define HCAN1_IMRH __PORT8 0xFFFA17 /* HCAN1 Interrupt Mask Register H */
+#define IMRH_IMR8m 0x01
+#define IMRH_IMR9m 0x02
+#define IMRH_IMR12m 0x10
+#define HCAN0_REC __PORT8 0xFFF818 /* HCAN0 Receive Error Counter */
+#define HCAN1_REC __PORT8 0xFFFA18 /* HCAN1 Receive Error Counter */
+#define HCAN0_TEC __PORT8 0xFFF819 /* HCAN0 Transmit Error Counter */
+#define HCAN1_TEC __PORT8 0xFFFA19 /* HCAN1 Transmit Error Counter */
+#define HCAN0_UMSR __PORT16 0xFFF81A /* HCAN0 Unread Message Status Register */
+#define HCAN1_UMSR __PORT16 0xFFFA1A /* HCAN1 Unread Message Status Register */
+#define HCAN0_LAFML __PORT16 0xFFF81C /* HCAN0 Local Acceptance Filter Masks L */
+#define HCAN1_LAFML __PORT16 0xFFFA1C /* HCAN1 Local Acceptance Filter Masks L */
+#define HCAN0_LAFMH __PORT16 0xFFF81E /* HCAN0 Local Acceptance Filter Masks H */
+#define HCAN1_LAFMH __PORT16 0xFFFA1E /* HCAN1 Local Acceptance Filter Masks H */
+/* Motor control PWM timer 1 */
+#define PWM_PWCR1 __PORT8 0xFFFC00 /* PWM control register 1 */
+#define PWCR1_CKS0m 0x01
+#define PWCR1_CKS1m 0x02
+#define PWCR1_CKS2m 0x04
+#define PWCR1_CSTm 0x08
+#define PWCR1_CMFm 0x10
+#define PWCR1_IEm 0x20
+#define PWM_PWOCR1 __PORT8 0xFFFC02 /* PWM Output Control Register 1 */
+#define PWOCR1_OE1Am 0x01
+#define PWOCR1_OE1Bm 0x02
+#define PWOCR1_OE1Cm 0x04
+#define PWOCR1_OE1Dm 0x08
+#define PWOCR1_OE1Em 0x10
+#define PWOCR1_OE1Fm 0x20
+#define PWOCR1_OE1Gm 0x40
+#define PWOCR1_OE1Hm 0x80
+#define PWM_PWPR1 __PORT8 0xFFFC04 /* PWM Polarity Register 1 */
+#define PWPR1_OPS1Am 0x01
+#define PWPR1_OPS1Bm 0x02
+#define PWPR1_OPS1Cm 0x04
+#define PWPR1_OPS1Dm 0x08
+#define PWPR1_OPS1Em 0x10
+#define PWPR1_OPS1Fm 0x20
+#define PWPR1_OPS1Gm 0x40
+#define PWPR1_OPS1Hm 0x80
+#define PWM_PWCYR1 __PORT16 0xFFFC06 /* PWM Cycle Register 1 */
+#define PWM_PWBFR1A __PORT16 0xFFFC08 /* PWM Buffer Register 1A */
+#define PWBFR1A_DT8m 0x01
+#define PWBFR1A_DT9m 0x02
+#define PWBFR1A_OTSm 0x10
+#define PWM_PWBFR1C __PORT16 0xFFFC0A /* PWM Buffer Register 1C */
+#define PWBFR1C_DT8m 0x01
+#define PWBFR1C_DT9m 0x02
+#define PWBFR1C_OTSm 0x10
+#define PWM_PWBFR1E __PORT16 0xFFFC0C /* PWM Buffer Register 1E */
+#define PWBFR1E_DT8m 0x01
+#define PWBFR1E_DT9m 0x02
+#define PWBFR1E_OTSm 0x10
+#define PWM_PWBFR1G __PORT16 0xFFFC0E /* PWM Buffer Register 1G */
+#define PWBFR1G_DT8m 0x01
+#define PWBFR1G_DT9m 0x02
+#define PWBFR1G_OTSm 0x10
+/* Motor control PWM timer 2 */
+#define PWM_PWCR2 __PORT8 0xFFFC10 /* PWM Control Register 2 */
+#define PWCR2_CKS0m 0x01
+#define PWCR2_CKS1m 0x02
+#define PWCR2_CKS2m 0x04
+#define PWCR2_CSTm 0x08
+#define PWCR2_CMFm 0x10
+#define PWCR2_IEm 0x20
+#define PWM_PWOCR2 __PORT8 0xFFFC12 /* PWM Output Control Register 2 */
+#define PWOCR2_OE2Am 0x01
+#define PWOCR2_OE2Bm 0x02
+#define PWOCR2_OE2Cm 0x04
+#define PWOCR2_OE2Dm 0x08
+#define PWOCR2_OE2Em 0x10
+#define PWOCR2_OE2Fm 0x20
+#define PWOCR2_OE2Gm 0x40
+#define PWOCR2_OE2Hm 0x80
+#define PWM_PWPR2 __PORT8 0xFFFC14 /* PWM Polarity Register 2 */
+#define PWPR2_OPS2Am 0x01
+#define PWPR2_OPS2Bm 0x02
+#define PWPR2_OPS2Cm 0x04
+#define PWPR2_OPS2Dm 0x08
+#define PWPR2_OPS2Em 0x10
+#define PWPR2_OPS2Fm 0x20
+#define PWPR2_OPS2Gm 0x40
+#define PWPR2_OPS2Hm 0x80
+#define PWM_PWCYR2 __PORT16 0xFFFC16 /* PWM Cycle Register 2 */
+#define PWM_PWBFR2A __PORT16 0xFFFC18 /* PWM Buffer Register 2A */
+#define PWBFR2A_DT8m 0x01
+#define PWBFR2A_DT9m 0x02
+#define PWBFR2A_TDSm 0x10
+#define PWM_PWBFR2B __PORT16 0xFFFC1A /* PWM Buffer Register 2B */
+#define PWBFR2B_DT8m 0x01
+#define PWBFR2B_DT9m 0x02
+#define PWBFR2B_TDSm 0x10
+#define PWM_PWBFR2C __PORT16 0xFFFC1C /* PWM Buffer Register 2C */
+#define PWBFR2C_DT8m 0x01
+#define PWBFR2C_DT9m 0x02
+#define PWBFR2C_TDSm 0x10
+#define PWM_PWBFR2D __PORT16 0xFFFC1E /* PWM Buffer Register 2E */
+#define PWBFR2D_DT8m 0x01
+#define PWBFR2D_DT9m 0x02
+#define PWBFR2D_TDSm 0x10
+/* Port H and J Registers */
+#define DIO_PHDDR __PORT8 0xFFFC20 /* DIO H Data Direction Register */
+#define PHDDR_PH0DDRm 0x01
+#define PHDDR_PH1DDRm 0x02
+#define PHDDR_PH2DDRm 0x04
+#define PHDDR_PH3DDRm 0x08
+#define PHDDR_PH4DDRm 0x10
+#define PHDDR_PH5DDRm 0x20
+#define PHDDR_PH6DDRm 0x40
+#define PHDDR_PH7DDRm 0x80
+#define DIO_PJDDR __PORT8 0xFFFC21 /* DIO J Data Direction Register */
+#define PJDDR_PJ0DDRm 0x01
+#define PJDDR_PJ1DDRm 0x02
+#define PJDDR_PJ2DDRm 0x04
+#define PJDDR_PJ3DDRm 0x08
+#define PJDDR_PJ4DDRm 0x10
+#define PJDDR_PJ5DDRm 0x20
+#define PJDDR_PJ6DDRm 0x40
+#define PJDDR_PJ7DDRm 0x80
+#define DIO_PHDR __PORT8 0xFFFC24 /* DIO H Data Register */
+#define PHDR_PH0DRm 0x01
+#define PHDR_PH1DRm 0x02
+#define PHDR_PH2DRm 0x04
+#define PHDR_PH3DRm 0x08
+#define PHDR_PH4DRm 0x10
+#define PHDR_PH5DRm 0x20
+#define PHDR_PH6DRm 0x40
+#define PHDR_PH7DRm 0x80
+#define DIO_PJDR __PORT8 0xFFFC25 /* DIO J Data Register */
+#define PJDR_PJ0DRm 0x01
+#define PJDR_PJ1DRm 0x02
+#define PJDR_PJ2DRm 0x04
+#define PJDR_PJ3DRm 0x08
+#define PJDR_PJ4DRm 0x10
+#define PJDR_PJ5DRm 0x20
+#define PJDR_PJ6DRm 0x40
+#define PJDR_PJ7DRm 0x80
+#define DIO_PORTH __PORT8 0xFFFC28 /* DIO H Register */
+#define PORTH_PH0m 0x01
+#define PORTH_PH1m 0x02
+#define PORTH_PH2m 0x04
+#define PORTH_PH3m 0x08
+#define PORTH_PH4m 0x10
+#define PORTH_PH5m 0x20
+#define PORTH_PH6m 0x40
+#define PORTH_PH7m 0x80
+#define DIO_PORTJ __PORT8 0xFFFC29 /* DIO J Register */
+#define PORTJ_PJ0m 0x01
+#define PORTJ_PJ1m 0x02
+#define PORTJ_PJ2m 0x04
+#define PORTJ_PJ3m 0x08
+#define PORTJ_PJ4m 0x10
+#define PORTJ_PJ5m 0x20
+#define PORTJ_PJ6m 0x40
+#define PORTJ_PJ7m 0x80
+
+/* Module IIC valid in 2630,2638 and 2639 */
+#define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */
+#define SCRX_IICEm 0x10
+#define SCRX_IICX0m 0x20
+#define SCRX_IICX1m 0x40
+#define IIC_DDCSWR __PORT8 0xFFFDB5 /* DDC Switch Register */
+#define DDCSWR_CLR0m 0x01
+#define DDCSWR_CLR1m 0x02
+#define DDCSWR_CLR2m 0x04
+#define DDCSWR_CLR3m 0x08
+#define DDCSWR_IFm 0x10
+#define DDCSWR_IEm 0x20
+#define DDCSWR_SWm 0x40
+#define DDCSWR_SWEm 0x80
+/* Module System */
+#define SYS_SBYCR __PORT8 0xFFFDE4 /* Standby Control Register */
+#define SBYCR_OPEm 0x08
+#define SBYCR_STS0m 0x10
+#define SBYCR_STS1m 0x20
+#define SBYCR_STS2m 0x40
+#define SBYCR_SSBYm 0x80
+#define SYS_SYSCR __PORT8 0xFFFDE5 /* SYS Control Register */
+#define SYSCR_RAMEm 0x01
+#define SYSCR_NMIEGm 0x08
+#define SYSCR_INTM0m 0x10
+#define SYSCR_INTM1m 0x20
+#define SYSCR_MACSm 0x80
+#define SYS_SCKCR __PORT8 0xFFFDE6 /* SYS Clock Control Register */
+#define SCKCR_SCK0m 0x01 /* Bus master clock selection */
+#define SCKCR_SCK1m 0x02 /* 0=full, 1=/2, 2=/4 3=/8 */
+#define SCKCR_SCK2m 0x04 /* 4=/16, 5=/32 */
+#define SCKCR_SCKxm 0x07
+#define SCKCR_STCSm 0x08 /* 1=Immediately change, 0=at Stby */
+#define SCKCR_PSTOPm 0x80 /* 1=Clock Output Disable */
+#define SYS_MDCR __PORT8 0xFFFDE7 /* Mode Control Register */
+#define MDCR_MDS0m 0x01
+#define MDCR_MDS1m 0x02
+#define MDCR_MDS2m 0x04
+#define SYS_PFCR __PORT8 0xFFFDEB /* Pin Function Control Register */
+#define PFCR_AE0m 0x01
+#define PFCR_AE1m 0x02
+#define PFCR_AE2m 0x04
+#define PFCR_AE3m 0x08
+#define PFCR_AExm 0x0f
+#define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */
+#define LPWRCR_STC0m 0x01
+#define LPWRCR_STC1m 0x02
+#define LPWRCR_STCxm 0x03
+#define LPWRCR_RFCUTm 0x08
+#define LPWRCR_SUBSTPm 0x10
+#define LPWRCR_NESELm 0x20
+#define LPWRCR_LSONm 0x40
+#define LPWRCR_DTONm 0x80
+/* Module PC Break Controller */
+#define PBC_BARA __PORT32 0xFFFE00 /* Break Address Register A */
+#define PBC_BARB __PORT32 0xFFFE04 /* Break Address Register B */
+#define PBC_BCRA __PORT8 0xFFFE08 /* Break Control Register A */
+#define BCRA_BIEAm 0x01
+#define BCRA_CSELA0m 0x02
+#define BCRA_CSELA1m 0x04
+#define BCRA_BAMRA0m 0x08
+#define BCRA_BAMRA1m 0x10
+#define BCRA_BAMRA2m 0x20
+#define BCRA_CDAm 0x40
+#define BCRA_CMFAm 0x80
+#define PBC_BCRB __PORT8 0xFFFE09 /* Break Control Register B */
+#define BCRB_BIEAm 0x01
+#define BCRB_CSELA0m 0x02
+#define BCRB_CSELA1m 0x04
+#define BCRB_BAMRA0m 0x08
+#define BCRB_BAMRA1m 0x10
+#define BCRB_BAMRA2m 0x20
+#define BCRB_CDAm 0x40
+#define BCRB_CMFAm 0x80
+/* Module Interrupt Controller Registers */
+#define INT_ISCRH __PORT8 0xFFFE12 /* IRQ Sence Control Register H */
+#define ISCRH_IRQ4SCAm 0x01
+#define ISCRH_IRQ4SCBm 0x02
+#define ISCRH_IRQ5SCAm 0x04
+#define ISCRH_IRQ5SCBm 0x08
+#define INT_ISCRL __PORT8 0xFFFE13 /* IRQ Sence Control Register L */
+#define ISCRL_IRQ0SCAm 0x01
+#define ISCRL_IRQ0SCBm 0x02
+#define ISCRL_IRQ1SCAm 0x04
+#define ISCRL_IRQ1SCBm 0x08
+#define ISCRL_IRQ2SCAm 0x10
+#define ISCRL_IRQ2SCBm 0x20
+#define ISCRL_IRQ3SCAm 0x40
+#define ISCRL_IRQ3SCBm 0x80
+#define INT_IER __PORT8 0xFFFE14 /* IRQ Enable Register */
+#define IER_IRQ0Em 0x01
+#define IER_IRQ1Em 0x02
+#define IER_IRQ2Em 0x04
+#define IER_IRQ3Em 0x08
+#define IER_IRQ4Em 0x10
+#define IER_IRQ5Em 0x20
+#define INT_ISR __PORT8 0xFFFE15 /* IRQ Status Register */
+#define ISR_IRQ0Fm 0x01
+#define ISR_IRQ1Fm 0x02
+#define ISR_IRQ2Fm 0x04
+#define ISR_IRQ3Fm 0x08
+#define ISR_IRQ4Fm 0x10
+#define ISR_IRQ5Fm 0x20
+
+#define DTC_DTCERA __PORT8 0xFFFE16 /* DTC Enable Register A */
+#define DTCERA_DTCEA0m 0x01
+#define DTCERA_DTCEA1m 0x02
+#define DTCERA_DTCEA2m 0x04
+#define DTCERA_DTCEA3m 0x08
+#define DTCERA_DTCEA4m 0x10
+#define DTCERA_DTCEA5m 0x20
+#define DTCERA_DTCEA6m 0x40
+#define DTCERA_DTCEA7m 0x80
+#define DTC_DTCERB __PORT8 0xFFFE17 /* DTC Enable Register B */
+#define DTCERB_DTCEB0m 0x01
+#define DTCERB_DTCEB1m 0x02
+#define DTCERB_DTCEB2m 0x04
+#define DTCERB_DTCEB3m 0x08
+#define DTCERB_DTCEB4m 0x10
+#define DTCERB_DTCEB5m 0x20
+#define DTCERB_DTCEB6m 0x40
+#define DTCERB_DTCEB7m 0x80
+#define DTC_DTCERC __PORT8 0xFFFE18 /* DTC Enable Register C */
+#define DTCERC_DTCEC0m 0x01
+#define DTCERC_DTCEC1m 0x02
+#define DTCERC_DTCEC2m 0x04
+#define DTCERC_DTCEC3m 0x08
+#define DTCERC_DTCEC4m 0x10
+#define DTCERC_DTCEC5m 0x20
+#define DTCERC_DTCEC6m 0x40
+#define DTCERC_DTCEC7m 0x80
+#define DTC_DTCERD __PORT8 0xFFFE19 /* DTC Enable Register D */
+#define DTCERD_DTCED0m 0x01
+#define DTCERD_DTCED1m 0x02
+#define DTCERD_DTCED2m 0x04
+#define DTCERD_DTCED3m 0x08
+#define DTCERD_DTCED4m 0x10
+#define DTCERD_DTCED5m 0x20
+#define DTCERD_DTCED6m 0x40
+#define DTCERD_DTCED7m 0x80
+#define DTC_DTCERE __PORT8 0xFFFE1A /* DTC Enable Register E */
+#define DTCERE_DTCEE0m 0x01
+#define DTCERE_DTCEE1m 0x02
+#define DTCERE_DTCEE2m 0x04
+#define DTCERE_DTCEE3m 0x08
+#define DTCERE_DTCEE4m 0x10
+#define DTCERE_DTCEE5m 0x20
+#define DTCERE_DTCEE6m 0x40
+#define DTCERE_DTCEE7m 0x80
+#define DTC_DTCERF __PORT8 0xFFFE1B /* DTC Enable Register F */
+#define DTCERF_DTCEF0m 0x01
+#define DTCERF_DTCEF1m 0x02
+#define DTCERF_DTCEF2m 0x04
+#define DTCERF_DTCEF3m 0x08
+#define DTCERF_DTCEF4m 0x10
+#define DTCERF_DTCEF5m 0x20
+#define DTCERF_DTCEF6m 0x40
+#define DTCERF_DTCEF7m 0x80
+#define DTC_DTCERG __PORT8 0xFFFE1C /* DTC Enable Register G */
+#define DTCERG_DTCEG0m 0x01
+#define DTCERG_DTCEG1m 0x02
+#define DTCERG_DTCEG2m 0x04
+#define DTCERG_DTCEG3m 0x08
+#define DTCERG_DTCEG4m 0x10
+#define DTCERG_DTCEG5m 0x20
+#define DTCERG_DTCEG6m 0x40
+#define DTCERG_DTCEG7m 0x80
+#define DTC_DTVECR __PORT8 0xFFFE1F /* DTC Vector Register */
+#define DTVECR_DTVEC0m 0x01
+#define DTVECR_DTVEC1m 0x02
+#define DTVECR_DTVEC2m 0x04
+#define DTVECR_DTVEC3m 0x08
+#define DTVECR_DTVEC4m 0x10
+#define DTVECR_DTVEC5m 0x20
+#define DTVECR_DTVEC6m 0x40
+#define DTVECR_SWDTEm 0x80
+/* Module Programmable Pulse Generator */
+#define PPG_PCR __PORT8 0xFFFE26 /* PPG Output Control Register */
+#define PCR_G0CMS0m 0x01
+#define PCR_G0CMS1m 0x02
+#define PCR_G1CMS0m 0x04
+#define PCR_G1CMS1m 0x08
+#define PCR_G2CMS0m 0x10
+#define PCR_G2CMS1m 0x20
+#define PCR_G3CMS0m 0x40
+#define PCR_G3CMS1m 0x80
+#define PPG_PMR __PORT8 0xFFFE27 /* PPG Output Mode Register */
+#define PMR_G0NOVm 0x01
+#define PMR_G1NOVm 0x02
+#define PMR_G2NOVm 0x04
+#define PMR_G3INVm 0x08
+#define PMR_G0INVm 0x10
+#define PMR_G1INVm 0x20
+#define PMR_G2INVm 0x40
+#define PMM_G3INVm 0x80
+#define PPG_NDERH __PORT8 0xFFFE28 /* Next Data Enable Register H */
+#define NDERH_NDER8m 0x01
+#define NDERH_NDER9m 0x02
+#define NDERH_NDER10m 0x04
+#define NDERH_NDER11m 0x08
+#define NDERH_NDER12m 0x10
+#define NDERH_NDER13m 0x20
+#define NDERH_NDER14m 0x40
+#define NDERH_NDER15m 0x80
+#define PPG_NDERL __PORT8 0xFFFE29 /* Next Data Enable Register L */
+#define NDERL_NDER0m 0x01
+#define NDERL_NDER1m 0x02
+#define NDERL_NDER2m 0x04
+#define NDERL_NDER3m 0x08
+#define NDERL_NDER4m 0x10
+#define NDERL_NDER5m 0x20
+#define NDERL_NDER6m 0x40
+#define NDERL_NDER7m 0x80
+#define PPG_PODRH __PORT8 0xFFFE2A /* Output Data Register H */
+#define PODRH_POD8m 0x01
+#define PODRH_POD9m 0x02
+#define PODRH_POD10m 0x04
+#define PODRH_POD11m 0x08
+#define PODRH_POD12m 0x10
+#define PODRH_POD13m 0x20
+#define PODRH_POD14m 0x40
+#define PODRH_POD15m 0x80
+#define PPG_PODRL __PORT8 0xFFFE2B /* Output Data Register L */
+#define PODRL_POD0m 0x01
+#define PODRL_POD1m 0x02
+#define PODRL_POD2m 0x04
+#define PODRL_POD3m 0x08
+#define PODRL_POD4m 0x10
+#define PODRL_POD5m 0x20
+#define PODRL_POD6m 0x40
+#define PODRL_POD7m 0x80
+//#define PPG_NDRH __PORT8 0xFFFE2C /* Next data register H */ /* Use when group2 and group3 have the same output trigger selected */
+#define NDRH_NDR8m 0x01 /* Use for group2 if group3 have different output triger to group2 */
+#define NDRH_NDR9m 0x02
+#define NDRH_NDR10m 0x04
+#define NDRH_NDR11m 0x08
+#define NDRH_NDR12m 0x10
+#define NDRH_NDR13m 0x20
+#define NDRH_NDR14m 0x40
+#define NDRH_NDR15m 0x80
+//#define PPG_NDRL __PORT8 0xFFFE2D /* Next data register L */ /* Use when group2 and group3 have the same output trigger selected */
+#define NDRL_NDR0m 0x01 /* Use for group2 if group3 have different output triger to group2 */
+#define NDRL_NDR1m 0x02
+#define NDRL_NDR2m 0x04
+#define NDRL_NDR3m 0x08
+#define NDRL_NDR4m 0x10
+#define NDRL_NDR5m 0x20
+#define NDRL_NDR6m 0x40
+#define NDRL_NDR7m 0x80
+//#define PPG_NDRH __PORT8 0xFFFE2E /* Next Data Register H */ /* Use for group3 if group2 and group3 have different triggers */
+#define NDRH_NDR8m 0x01
+#define NDRH_NDR9m 0x02
+#define NDRH_NDR10m 0x04
+#define NDRH_NDR11m 0x08
+//#define PPG_NDRL __PORT8 0xFFFE2F /* Next Data Register L */ /* Use for group3 if group2 and group3 have different triggers */
+#define NDRL_NDR0m 0x01
+#define NDRL_NDR1m 0x02
+#define NDRL_NDR2m 0x04
+#define NDRL_NDR3m 0x08
+/* Module Port */
+#define DIO_P1DDR __PORT8 0xFFFE30 /* DIO 1 Data Direction Register */
+#define P1DDR_P10DDRm 0x01
+#define P1DDR_P11DDRm 0x02
+#define P1DDR_P12DDRm 0x04
+#define P1DDR_P13DDRm 0x08
+#define P1DDR_P14DDRm 0x10
+#define P1DDR_P15DDRm 0x20
+#define P1DDR_P16DDRm 0x40
+#define P1DDR_P17DDRm 0x80
+#define DIO_P3DDR __PORT8 0xFFFE32 /* DIO 3 Data Direction Register */
+#define P3DDR_P30DDRm 0x01
+#define P3DDR_P31DDRm 0x02
+#define P3DDR_P32DDRm 0x04
+#define P3DDR_P33DDRm 0x08
+#define P3DDR_P34DDRm 0x10
+#define P3DDR_P35DDRm 0x20
+#define DIO_PADDR __PORT8 0xFFFE39 /* DIO A Data Direction Register */
+#define PADDR_PA0DDRm 0x01
+#define PADDR_PA1DDRm 0x02
+#define PADDR_PA2DDRm 0x04
+#define PADDR_PA3DDRm 0x08
+#define DIO_PBDDR __PORT8 0xFFFE3A /* DIO B Data Direction Register */
+#define PBDDR_PB0DDRm 0x01
+#define PBDDR_PB1DDRm 0x02
+#define PBDDR_PB2DDRm 0x04
+#define PBDDR_PB3DDRm 0x08
+#define PBDDR_PB4DDRm 0x10
+#define PBDDR_PB5DDRm 0x20
+#define PBDDR_PB6DDRm 0x40
+#define PBDDR_PB7DDRm 0x80
+#define DIO_PCDDR __PORT8 0xFFFE3B /* DIO C Data Direction Register */
+#define PCDDR_PC0DDRm 0x01
+#define PCDDR_PC1DDRm 0x02
+#define PCDDR_PC2DDRm 0x04
+#define PCDDR_PC3DDRm 0x08
+#define PCDDR_PC4DDRm 0x10
+#define PCDDR_PC5DDRm 0x20
+#define PCDDR_PC6DDRm 0x40
+#define PCDDR_PC7DDRm 0x80
+#define DIO_PDDDR __PORT8 0xFFFE3C /* DIO D Data Direction Register */
+#define PDDDR_PD0DDRm 0x01
+#define PDDDR_PD1DDRm 0x02
+#define PDDDR_PD2DDRm 0x04
+#define PDDDR_PD3DDRm 0x08
+#define PDDDR_PD4DDRm 0x10
+#define PDDDR_PD5DDRm 0x20
+#define PDDDR_PD6DDRm 0x40
+#define PDDDR_PD7DDRm 0x80
+#define DIO_PEDDR __PORT8 0xFFFE3D /* DIO E Data Direction Register */
+#define PEDDR_PE0DDRm 0x01
+#define PEDDR_PE1DDRm 0x02
+#define PEDDR_PE2DDRm 0x04
+#define PEDDR_PE3DDRm 0x08
+#define PEDDR_PE4DDRm 0x10
+#define PEDDR_PE5DDRm 0x20
+#define PEDDR_PE6DDRm 0x40
+#define PEDDR_PE7DDRm 0x80
+#define DIO_PFDDR __PORT8 0xFFFE3E /* DIO F Data Direction Register */
+#define PFDDR_PF0DDRm 0x01
+#define PFDDR_PF3DDRm 0x08
+#define PFDDR_PF4DDRm 0x10
+#define PFDDR_PF5DDRm 0x20
+#define PFDDR_PF6DDRm 0x40
+#define PFDDR_PF7DDRm 0x80
+#define DIO_PAPCR __PORT8 0xFFFE40 /* DIO A MOS Pull-Up Control Register */
+#define PAPCR_PA0PCRm 0x01
+#define PAPCR_PA1PCRm 0x02
+#define PAPCR_PA2PCRm 0x04
+#define PAPCR_PA3PCRm 0x08
+#define DIO_PBPCR __PORT8 0xFFFE41 /* DIO B MOS Pull-Up Control Register */
+#define PBPCR_PB0PCRm 0x01
+#define PBPCR_PB1PCRm 0x02
+#define PBPCR_PB2PCRm 0x04
+#define PBPCR_PB3PCRm 0x08
+#define PBPCR_PB4PCRm 0x10
+#define PBPCR_PB5PCRm 0x20
+#define PBPCR_PB6PCRm 0x40
+#define PBPCR_PB7PCRm 0x80
+#define DIO_PCPCR __PORT8 0xFFFE42 /* DIO C MOS Pull-Up Control Register */
+#define PCPCR_PC0PCRm 0x01
+#define PCPCR_PC1PCRm 0x02
+#define PCPCR_PC2PCRm 0x04
+#define PCPCR_PC3PCRm 0x08
+#define PCPCR_PC4PCRm 0x10
+#define PCPCR_PC5PCRm 0x20
+#define PCPCR_PC6PCRm 0x40
+#define PCPCR_PC7PCRm 0x80
+#define DIO_PDPCR __PORT8 0xFFFE43 /* DIO D MOS Pull-Up Control Register */
+#define PDPCR_PD0PCRm 0x01
+#define PDPCR_PD1PCRm 0x02
+#define PDPCR_PD2PCRm 0x04
+#define PDPCR_PD3PCRm 0x08
+#define PDPCR_PD4PCRm 0x10
+#define PDPCR_PD5PCRm 0x20
+#define PDPCR_PD6PCRm 0x40
+#define PDPCR_PD7PCRm 0x80
+#define DIO_PEPCR __PORT8 0xFFFE44 /* DIO E MOS Pull-Up Control Register */
+#define PEPCR_PE0PCRm 0x01
+#define PEPCR_PE1PCRm 0x02
+#define PEPCR_PE2PCRm 0x04
+#define PEPCR_PE3PCRm 0x08
+#define PEPCR_PE4PCRm 0x10
+#define PEPCR_PE5PCRm 0x20
+#define PEPCR_PE6PCRm 0x40
+#define PEPCR_PE7PCRm 0x80
+#define DIO_P3ODR __PORT8 0xFFFE46 /* DIO 3 Open Drain Control Register */
+#define P3ODR_P30ODRm 0x01
+#define P3ODR_P31ODRm 0x02
+#define P3ODR_P32ODRm 0x04
+#define P3ODR_P33ODRm 0x08
+#define P3ODR_P34ODRm 0x10
+#define P3ODR_P35ODRm 0x20
+#define DIO_PAODR __PORT8 0xFFFE47 /* DIO A Open Drain Control Register */
+#define PAODR_PA0ODRm 0x01
+#define PAODR_PA1ODRm 0x02
+#define PAODR_PA2ODRm 0x04
+#define PAODR_PA3ODRm 0x08
+#define DIO_PBODR __PORT8 0xFFFE48 /* DIO B Open Drain Control Register */
+#define PBODR_PB0ODRm 0x01
+#define PBODR_PB1ODRm 0x02
+#define PBODR_PB2ODRm 0x04
+#define PBODR_PB3ODRm 0x08
+#define PBODR_PB4ODRm 0x10
+#define PBODR_PB5ODRm 0x20
+#define PBODR_PB6ODRm 0x40
+#define PBODR_PB7ODRm 0x80
+#define DIO_PCODR __PORT8 0xFFFE49 /* DIO C Open Drain Control Register */
+#define PCODR_PC0ODRm 0x01
+#define PCODR_PC1ODRm 0x02
+#define PCODR_PC2ODRm 0x04
+#define PCODR_PC3ODRm 0x08
+#define PCODR_PC4ODRm 0x10
+#define PCODR_PC5ODRm 0x20
+#define PCODR_PC6ODRm 0x40
+#define PCODR_PC7ODRm 0x80
+/* Module Time pulse unit */
+#define TPU_TCR3 __PORT8 0xFFFE80 /* Timer Control Register 3 */
+#define TCR3_TPSC0m 0x01
+#define TCR3_TPSC1m 0x02
+#define TCR3_TPSC2m 0x04
+#define TCR3_CKEG0m 0x08
+#define TCR3_CKEG1m 0x10
+#define TCR3_CCLR0m 0x20
+#define TCR3_CCLR1m 0x40
+#define TCR3_CCLR2m 0x80
+#define TPU_TMDR3 __PORT8 0xFFFE81 /* Timer Mode Register 3 */
+#define TMDR3_MD0m 0x01
+#define TMDR3_MD1m 0x02
+#define TMDR3_MD2m 0x04
+#define TMDR3_MD3m 0x08
+#define TMDR3_BFAm 0x10
+#define TMDR3_BFBm 0x20
+#define TPU_TIOR3H __PORT8 0xFFFE82 /* Timer IO Control Register 3H */
+#define TIOR3H_IOA0m 0x01
+#define TIOR3H_IOA1m 0x02
+#define TIOR3H_IOA2m 0x04
+#define TIOR3H_IOA3m 0x08
+#define TIOR3H_IOB0m 0x10
+#define TIOR3H_IOB1m 0x20
+#define TIOR3H_IOB2m 0x40
+#define TIOR3H_IOB3m 0x80
+#define TPU_TIOR3L __PORT8 0xFFFE83 /* Timer IO Control Register 3L */
+#define TIOR3L_IOC0m 0x01
+#define TIOR3L_IOC1m 0x02
+#define TIOR3L_IOC2m 0x04
+#define TIOR3L_IOC3m 0x08
+#define TIOR3L_IOD0m 0x10
+#define TIOR3L_IOD1m 0x20
+#define TIOR3L_IOD2m 0x40
+#define TIOR3L_IOD3m 0x80
+#define TPU_TIER3 __PORT8 0xFFFE84 /* -Timer INT Enable Register 3 */
+#define TIER3_TGIEAm 0x01
+#define TIER3_TGIEBm 0x02
+#define TIER3_TGIECm 0x04
+#define TIER3_TGIEDm 0x08
+#define TIER3_TCIEVm 0x10
+#define TIER3_TTGEm 0x80
+#define TPU_TSR3 __PORT8 0xFFFE85 /* Timer Status Register 3 */
+#define TSR3_TGFAm 0x01
+#define TSR3_TGFBm 0x02
+#define TSR3_TGFCm 0x04
+#define TSR3_TGFDm 0x08
+#define TSR3_TCFVm 0x10
+#define TPU_TCNT3 __PORT16 0xFFFE86 /* Timer Counter 3 */
+#define TPU_TGR3A __PORT16 0xFFFE88 /* Timer General Register 3A */
+#define TPU_TGR3B __PORT16 0xFFFE8A /* Timer General Register 3B */
+#define TPU_TGR3C __PORT16 0xFFFE8C /* Timer General Register 3C */
+#define TPU_TGR3D __PORT16 0xFFFE8E /* Timer General Register 3D */
+#define TPU_TCR4 __PORT8 0xFFFE90 /* Timer Control Register 4 */
+#define TCR4_TPSC0m 0x01
+#define TCR4_TPSC1m 0x02
+#define TCR4_TPSC2m 0x04
+#define TCR4_CKEG0m 0x08
+#define TCR4_CKEG1m 0x10
+#define TCR4_CCLR0m 0x20
+#define TCR4_CCLR1m 0x40
+#define TPU_TMDR4 __PORT8 0xFFFE91 /* Timer Mode Register 4 */
+#define TMDR4_MD0m 0x01
+#define TMDR4_MD1m 0x02
+#define TMDR4_MD2m 0x04
+#define TMDR4_MD3m 0x08
+#define TPU_TIOR4 __PORT8 0xFFFE92 /* Timer IO Control Register 4 */
+#define TIOR4_IOA0m 0x01
+#define TIOR4_IOA1m 0x02
+#define TIOR4_IOA2m 0x04
+#define TIOR4_IOA3m 0x08
+#define TIOR4_IOB0m 0x10
+#define TIOR4_IOB1m 0x20
+#define TIOR4_IOB2m 0x40
+#define TIOR4_IOB3m 0x80
+#define TPU_TIER4 __PORT8 0xFFFE94 /* Timer INT Enable Register 4 */
+#define TIER4_TGIEAm 0x01
+#define TIER4_TGIEBm 0x02
+#define TIER4_TCIEVm 0x10
+#define TIER4_TCIEUm 0x20
+#define TIER4_TTGEm 0x80
+#define TPU_TSR4 __PORT8 0xFFFE95 /* Timer Status Register 4 */
+#define TSR4_TGFAm 0x01
+#define TSR4_TGFBm 0x02
+#define TSR4_TCFVm 0x10
+#define TSR4_TCFUm 0x20
+#define TSR4_TCFDm 0x80
+#define TPU_TCNT4 __PORT16 0xFFFE96 /* Timer Counter 4 */
+#define TPU_TGR4A __PORT16 0xFFFE98 /* Timer General Register 4A */
+#define TPU_TGR4B __PORT16 0xFFFE9A /* Timer General Register 4B */
+#define TPU_TCR5 __PORT8 0xFFFEA0 /* Timer Control Register 5 */
+#define TCR5_TPSC0m 0x01
+#define TCR5_TPSC1m 0x02
+#define TCR5_TPSC2m 0x04
+#define TCR5_CKEG0m 0x08
+#define TCR5_CKEG1m 0x10
+#define TCR5_CCLR0m 0x20
+#define TCR5_CCLR1m 0x40
+#define TPU_TMDR5 __PORT8 0xFFFEA1 /* Timer Mode Register 5 */
+#define TMDR5_MD0m 0x01
+#define TMDR5_MD1m 0x02
+#define TMDR5_MD2m 0x04
+#define TMDR5_MD3m 0x08
+#define TPU_TIOR5 __PORT8 0xFFFEA2 /* Timer IO Control Register 5 */
+#define TIOR5_IOA0m 0x01
+#define TIOR5_IOA1m 0x02
+#define TIOR5_IOA2m 0x04
+#define TIOR5_IOA3m 0x08
+#define TIOR5_IOB0m 0x10
+#define TIOR5_IOB1m 0x20
+#define TIOR5_IOB2m 0x40
+#define TIOR5_IOB3m 0x80
+#define TPU_TIER5 __PORT8 0xFFFEA4 /* Timer INT Enable Register 5 */
+#define TIER5_TGIEAm 0x01
+#define TIER5_TGIEBm 0x02
+#define TIER5_TCIEVm 0x10
+#define TIER5_TCIEUm 0x20
+#define TIER5_TTGEm 0x80
+#define TPU_TSR5 __PORT8 0xFFFEA5 /* Timer Status Register 5 */
+#define TSR5_TGFAm 0x01
+#define TSR5_TGFBm 0x02
+#define TSR5_TCFVm 0x10
+#define TSR5_TCFUm 0x20
+#define TSR5_TCFDm 0x80
+#define TPU_TCNT5 __PORT16 0xFFFEA6 /* Timer Counter 5 */
+#define TPU_TGR5A __PORT16 0xFFFEA8 /* Timer General Register 5A */
+#define TPU_TGR5B __PORT16 0xFFFEAA /* Timer General Register 5B */
+#define TPU_TSTR __PORT8 0xFFFEB0 /* Timer Start Register */
+#define TSTR_CST0m 0x01
+#define TSTR_CST1m 0x02
+#define TSTR_CST2m 0x04
+#define TSTR_CST3m 0x08
+#define TSTR_CST4m 0x10
+#define TSTR_CST5m 0x20
+#define TPU_TSYR __PORT8 0xFFFEB1 /* Timer Synchro Register */
+#define TSYR_SYNC0m 0x01
+#define TSYR_SYNC1m 0x02
+#define TSYR_SYNC2m 0x04
+#define TSYR_SYNC3m 0x08
+#define TSYR_SYNC4m 0x10
+#define TSYR_SYNC5m 0x20
+/* Module Interrupt */
+#define INT_IPRA __PORT8 0xFFFEC0 /* Interrupt Priority Register A */
+#define IPRA_IPR0m 0x01
+#define IPRA_IPR1m 0x02
+#define IPRA_IPR2m 0x04
+#define IPRA_IPR4m 0x10
+#define IPRA_IPR5m 0x20
+#define IPRA_IPR6m 0x40
+#define INT_IPRB __PORT8 0xFFFEC1 /* Interrupt Priority Register B */
+#define IPRB_IPR0m 0x01
+#define IPRB_IPR1m 0x02
+#define IPRB_IPR2m 0x04
+#define IPRB_IPR4m 0x10
+#define IPRB_IPR5m 0x20
+#define IPRB_IPR6m 0x40
+#define INT_IPRC __PORT8 0xFFFEC2 /* Interrupt Priority Register C */
+#define IPRC_IPR0m 0x01
+#define IPRC_IPR1m 0x02
+#define IPRC_IPR2m 0x04
+#define INT_IPRD __PORT8 0xFFFEC3 /* Interrupt Priority Register D */
+#define IPRD_IPR4m 0x10
+#define IPRD_IPR5m 0x20
+#define IPRD_IPR6m 0x40
+#define INT_IPRE __PORT8 0xFFFEC4 /* Interrupt Priority Register E */
+#define IPRE_IPR0m 0x01
+#define IPRE_IPR1m 0x02
+#define IPRE_IPR2m 0x04
+#define IPRE_IPR4m 0x10
+#define IPRE_IPR5m 0x20
+#define IPRE_IPR6m 0x40
+#define INT_IPRF __PORT8 0xFFFEC5 /* Interrupt Priority Register F */
+#define IPRF_IPR0m 0x01
+#define IPRF_IPR1m 0x02
+#define IPRF_IPR2m 0x04
+#define IPRF_IPR4m 0x10
+#define IPRF_IPR5m 0x20
+#define IPRF_IPR6m 0x40
+#define INT_IPRG __PORT8 0xFFFEC6 /* Interrupt Priority Register G */
+#define IPRG_IPR0m 0x01
+#define IPRG_IPR1m 0x02
+#define IPRG_IPR2m 0x04
+#define IPRG_IPR4m 0x10
+#define IPRG_IPR5m 0x20
+#define IPRG_IPR6m 0x40
+#define INT_IPRH __PORT8 0xFFFEC7 /* Interrupt Priority Register H */
+#define IPRH_IPR0m 0x01
+#define IPRH_IPR1m 0x02
+#define IPRH_IPR2m 0x04
+#define IPRH_IPR4m 0x10
+#define IPRH_IPR5m 0x20
+#define IPRH_IPR6m 0x40
+#define INT_IPRJ __PORT8 0xFFFEC9 /* Interrupt Priority Register J */
+#define IPRJ_IPR0m 0x01
+#define IPRJ_IPR1m 0x02
+#define IPRJ_IPR2m 0x04
+#define INT_IPRK __PORT8 0xFFFECA /* Interrupt Priority Register K */
+#define IPRK_IPR0m 0x01
+#define IPRK_IPR1m 0x02
+#define IPRK_IPR2m 0x04
+#define IPRK_IPR4m 0x10
+#define IPRK_IPR5m 0x20
+#define IPRK_IPR6m 0x40
+#define INT_IPRM __PORT8 0xFFFECC /* Interrupt Priority Register M */
+#define IPRM_IPR0m 0x01
+#define IPRM_IPR1m 0x02
+#define IPRM_IPR2m 0x04
+#define IPRM_IPR4m 0x10
+#define IPRM_IPR5m 0x20
+#define IPRM_IPR6m 0x40
+/* Module BUS controler */
+#define BUS_ABWCR __PORT8 0xFFFED0 /* Bus Width Control Register */
+#define ABWCR_ABW0m 0x01
+#define ABWCR_ABW1m 0x02
+#define ABWCR_ABW2m 0x04
+#define ABWCR_ABW3m 0x08
+#define ABWCR_ABW4m 0x10
+#define ABWCR_ABW5m 0x20
+#define ABWCR_ABW6m 0x40
+#define ABWCR_ABW7m 0x80
+#define BUS_ASTCR __PORT8 0xFFFED1 /* Access State Control Register */
+#define ASTCR_AST0m 0x01
+#define ASTCR_AST1m 0x02
+#define ASTCR_AST2m 0x04
+#define ASTCR_AST3m 0x08
+#define ASTCR_AST4m 0x10
+#define ASTCR_AST5m 0x20
+#define ASTCR_AST6m 0x40
+#define ASTCR_AST7m 0x80
+#define BUS_WCRH __PORT8 0xFFFED2 /* Wait Control Register H */
+#define WCRH_W40m 0x01
+#define WCRH_W41m 0x02
+#define WCRH_W50m 0x04
+#define WCRH_W51m 0x08
+#define WCRH_W60m 0x10
+#define WCRH_W61m 0x20
+#define WCRH_W70m 0x40
+#define WCRH_W71m 0x80
+#define BUS_WCRL __PORT8 0xFFFED3 /* Wait Control Register L */
+#define WCRL_W00m 0x01
+#define WCRL_W01m 0x02
+#define WCRL_W10m 0x04
+#define WCRL_W11m 0x08
+#define WCRL_W20m 0x10
+#define WCRL_W21m 0x20
+#define WCRL_W30m 0x40
+#define WCRL_W31m 0x80
+#define BUS_BCRH __PORT8 0xFFFED4 /* Bus Control Register H */
+#define BCRH_BRSTS0m 0x08
+#define BCRH_BRSTS1m 0x10
+#define BCRH_BRSTRMm 0x20
+#define BCRH_ICIS0m 0x40
+#define BCRH_ICIS1m 0x80
+#define BUS_BCRL __PORT8 0xFFFED5 /* Bus Control Register L */
+#define BCRL_WDBEm 0x02
+/* Module Flash */
+#define FLM_RAMER __PORT8 0xFFFEDB /* RAM Emulation Register */
+#define RAMER_RAM0m 0x01
+#define RAMER_RAM1m 0x02
+#define RAMER_RAM2m 0x04
+#define RAMER_RAMxm 0x07
+#define RAMER_RAMSm 0x08
+
+/* Module Port */
+#define DIO_P1DR __PORT8 0xFFFF00 /* DIO 1 Data Register */
+#define P1DR_P10DRm 0x01
+#define P1DR_P11DRm 0x02
+#define P1DR_P12DRm 0x04
+#define P1DR_P13DRm 0x08
+#define P1DR_P14DRm 0x10
+#define P1DR_P15DRm 0x20
+#define P1DR_P16DRm 0x40
+#define P1DR_P17DRm 0x80
+#define DIO_P3DR __PORT8 0xFFFF02 /* DIO 3 Data Register */
+#define P3DR_P30DRm 0x01
+#define P3DR_P31DRm 0x02
+#define P3DR_P32DRm 0x04
+#define P3DR_P33DRm 0x08
+#define P3DR_P34DRm 0x10
+#define P3DR_P35DRm 0x20
+#define DIO_PADR __PORT8 0xFFFF09 /* DIO A Data Register */
+#define PADR_PA0DRm 0x01
+#define PADR_PA1DRm 0x02
+#define PADR_PA2DRm 0x04
+#define PADR_PA3DRm 0x08
+#define DIO_PBDR __PORT8 0xFFFF0A /* DIO B Data Register */
+#define PBDR_PB0DRm 0x01
+#define PBDR_PB1DRm 0x02
+#define PBDR_PB2DRm 0x04
+#define PBDR_PB3DRm 0x08
+#define PBDR_PB4DRm 0x10
+#define PBDR_PB5DRm 0x20
+#define PBDR_PB6DRm 0x40
+#define PBDR_PB7DRm 0x80
+#define DIO_PCDR __PORT8 0xFFFF0B /* DIO C Data Register */
+#define PCDR_PC0DRm 0x01
+#define PCDR_PC1DRm 0x02
+#define PCDR_PC2DRm 0x04
+#define PCDR_PC3DRm 0x08
+#define PCDR_PC4DRm 0x10
+#define PCDR_PC5DRm 0x20
+#define PCDR_PC6DRm 0x40
+#define PCDR_PC7DRm 0x80
+#define DIO_PDDR __PORT8 0xFFFF0C /* DIO D Data Register */
+#define PDDR_PD0DRm 0x01
+#define PDDR_PD1DRm 0x02
+#define PDDR_PD2DRm 0x04
+#define PDDR_PD3DRm 0x08
+#define PDDR_PD4DRm 0x10
+#define PDDR_PD5DRm 0x20
+#define PDDR_PD6DRm 0x40
+#define PDDR_PD7DRm 0x80
+#define DIO_PEDR __PORT8 0xFFFF0D /* DIO E Data Register */
+#define PEDR_PE0DRm 0x01
+#define PEDR_PE1DRm 0x02
+#define PEDR_PE2DRm 0x04
+#define PEDR_PE3DRm 0x08
+#define PEDR_PE4DRm 0x10
+#define PEDR_PE5DRm 0x20
+#define PEDR_PE6DRm 0x40
+#define PEDR_PE7DRm 0x80
+#define DIO_PFDR __PORT8 0xFFFF0E /* DIO F Data Register */
+#define PFDR_PF0DRm 0x01
+#define PFDR_PF3DRm 0x08
+#define PFDR_PF4DRm 0x10
+#define PFDR_PF5DRm 0x20
+#define PFDR_PF6DRm 0x40
+#define PFDR_PF7DRm 0x80
+/* Module Time pulse unit */
+#define TPU_TCR0 __PORT8 0xFFFF10 /* Timer Control Register 0 */
+#define TCR0_TPSC0m 0x01
+#define TCR0_TPSC1m 0x02
+#define TCR0_TPSC2m 0x04
+#define TCR0_CKEG0m 0x08
+#define TCR0_CKEG1m 0x10
+#define TCR0_CCLR0m 0x20
+#define TCR0_CCLR1m 0x40
+#define TCR0_CCLR2m 0x80
+#define TPU_TMDR0 __PORT8 0xFFFF11 /* Timer Mode Register 0 */
+#define TMDR0_MD0m 0x01
+#define TMDR0_MD1m 0x02
+#define TMDR0_MD2m 0x04
+#define TMDR0_MD3m 0x08
+#define TMDR0_BFAm 0x10
+#define TMDR0_BFBm 0x20
+#define TPU_TIOR0H __PORT8 0xFFFF12 /* Timer IO Control Register 0H */
+#define TIOR0H_IOA0m 0x01
+#define TIOR0H_IOA1m 0x02
+#define TIOR0H_IOA2m 0x04
+#define TIOR0H_IOA3m 0x08
+#define TIOR0H_IOB0m 0x10
+#define TIOR0H_IOB1m 0x20
+#define TIOR0H_IOB2m 0x40
+#define TIOR0H_IOB3m 0x80
+#define TPU_TIOR0L __PORT8 0xFFFF13 /* Timer IO Control Register 0L */
+#define TIOR0L_IOC0m 0x01
+#define TIOR0L_IOC1m 0x02
+#define TIOR0L_IOC2m 0x04
+#define TIOR0L_IOC3m 0x08
+#define TIOR0L_IOD0m 0x10
+#define TIOR0L_IOD1m 0x20
+#define TIOR0L_IOD2m 0x40
+#define TIOR0L_IOD3m 0x80
+#define TPU_TIER0 __PORT8 0xFFFF14 /* Timer INT Enable Register 0 */
+#define TIER0_TGIEAm 0x01
+#define TIER0_TGIEBm 0x02
+#define TIER0_TGIECm 0x04
+#define TIER0_TGIEDm 0x08
+#define TIER0_TCIEVm 0x10
+#define TIER0_TTGEm 0x80
+#define TPU_TSR0 __PORT8 0xFFFF15 /* Timer Status Register 0 */
+#define TSR0_TGFAm 0x01
+#define TSR0_TGFBm 0x02
+#define TSR0_TGFCm 0x04
+#define TSR0_TGFDm 0x08
+#define TSR0_TCFVm 0x10
+#define TPU_TCNT0 __PORT16 0xFFFF16 /* Timer Counter 0 */
+#define TPU_TGR0A __PORT16 0xFFFF18 /* Timer General Register 0A */
+#define TPU_TGR0B __PORT16 0xFFFF1A /* Timer General Register 0B */
+#define by_standbym 0x02
+#define data_tom 0x02
+#define data_tom 0x02
+#define to_slavem 0x02
+#define TPU_TGR0C __PORT16 0xFFFF1C /* Timer General Register 0C */
+#define TPU_TGR0D __PORT16 0xFFFF1E /* Timer General Register 0D */
+#define TPU_TCR1 __PORT8 0xFFFF20 /* Timer Control Register 1 */
+#define TCR1_TPSC0m 0x01
+#define TCR1_TPSC1m 0x02
+#define TCR1_TPSC2m 0x04
+#define TCR1_CKEG0m 0x08
+#define TCR1_CKEG1m 0x10
+#define TCR1_CCLR0m 0x20
+#define TCR1_CCLR1m 0x40
+#define TPU_TMDR1 __PORT8 0xFFFF21 /* Timer Mode Register 1 */
+#define TMDR1_MD0m 0x01
+#define TMDR1_MD1m 0x02
+#define TMDR1_MD2m 0x04
+#define TMDR1_MD3m 0x08
+#define TPU_TIOR1 __PORT8 0xFFFF22 /* Timer IO Control Register 1 */
+#define TIOR1_IOA0m 0x01
+#define TIOR1_IOA1m 0x02
+#define TIOR1_IOA2m 0x04
+#define TIOR1_IOA3m 0x08
+#define TIOR1_IOB0m 0x10
+#define TIOR1_IOB1m 0x20
+#define TIOR1_IOB2m 0x40
+#define TIOR1_IOB3m 0x80
+#define TPU_TIER1 __PORT8 0xFFFF24 /* Timer INT Enable Register 1 */
+#define TIER1_TGIEAm 0x01
+#define TIER1_TGIEBm 0x02
+#define TIER1_TCIEVm 0x10
+#define TIER1_TCIEUm 0x20
+#define TIER1_TTGEm 0x80
+#define TPU_TSR1 __PORT8 0xFFFF25 /* Timer Status Register 1 */
+#define TSR1_TGFAm 0x01
+#define TSR1_TGFBm 0x02
+#define TSR1_TCFVm 0x10
+#define TSR1_TCFUm 0x20
+#define TSR1_TCFDm 0x80
+#define TPU_TCNT1 __PORT16 0xFFFF26 /* Timer Counter 1 */
+#define TPU_TGR1A __PORT16 0xFFFF28 /* Timer General Register 1A */
+#define TPU_TGR1B __PORT16 0xFFFF2A /* Timer General Register 1B */
+#define TPU_TCR2 __PORT8 0xFFFF30 /* Timer Control Register 2 */
+#define TCR2_TPSC0m 0x01
+#define TCR2_TPSC1m 0x02
+#define TCR2_TPSC2m 0x04
+#define TCR2_CKEG0m 0x08
+#define TCR2_CKEG1m 0x10
+#define TCR2_CCLR0m 0x20
+#define TCR2_CCLR1m 0x40
+#define TPU_TMDR2 __PORT8 0xFFFF31 /* Timer Mode Register 2 */
+#define TMDR2_MD0m 0x01
+#define TMDR2_MD1m 0x02
+#define TMDR2_MD2m 0x04
+#define TMDR2_MD3m 0x08
+#define TPU_TIOR2 __PORT8 0xFFFF32 /* Timer IO Control Register 2 */
+#define TIOR2_IOA0m 0x01
+#define TIOR2_IOA1m 0x02
+#define TIOR2_IOA2m 0x04
+#define TIOR2_IOA3m 0x08
+#define TIOR2_IOB0m 0x10
+#define TIOR2_IOB1m 0x20
+#define TIOR2_IOB2m 0x40
+#define TIOR2_IOB3m 0x80
+#define TPU_TIER2 __PORT8 0xFFFF34 /* Timer INT Enable Register 2 */
+#define TIER2_TGIEAm 0x01
+#define TIER2_TGIEBm 0x02
+#define TIER2_TCIEVm 0x10
+#define TIER2_TCIEUm 0x20
+#define TIER2_TTGEm 0x80
+#define TPU_TSR2 __PORT8 0xFFFF35 /* Timer Status Register 2 */
+#define TSR2_TGFAm 0x01
+#define TSR2_TGFBm 0x02
+#define TSR2_TCFVm 0x10
+#define TSR2_TCFUm 0x20
+#define TSR2_TCFDm 0x80
+#define TPU_TCNT2 __PORT16 0xFFFF36 /* Timer Counter 2 */
+#define TPU_TGR2A __PORT16 0xFFFF38 /* Timer General Register 2A */
+#define TPU_TGR2B __PORT16 0xFFFF3A /* Timer General Register 2B */
+
+/* Module Watchdog timer */
+/* WDT0 register definitions start */
+#define WDT_WTCSR0r __PORT8 0xFFFF74 /* Timer ControlStatus Register 0 (RD/WC7) */
+#define WDT_WTCSR0w __PORT16 0xFFFF74 /* writte address - password 0xa500 */
+#define WTCSR0_CKS0m 0x01
+#define WTCSR0_CKS1m 0x02
+#define WTCSR0_CKS2m 0x04
+#define WTCSR0_CKSxm 0x07
+#define WTCSR0_TMEm 0x20
+#define WTCSR0_WTITm 0x40
+#define WTCSR0_WOVFm 0x80
+#define WDT_WTCNT0r __PORT8 0xFFFF75 /* Timer Counter 0 (RD) */
+#define WDT_WTCNT0w __PORT16 0xFFFF74 /* writte address - password 0x5a00 */
+#define WDT_WRSTCSRr __PORT8 0xFFFF77 /* Reset ControlStatus Register (RD/WC7) */
+#define WDT_WRSTCSRw __PORT16 0xFFFF76 /* clear WOVF - password 0xa500 */
+ /* set bits - password 0x5a00 */
+#define WRSTCSR_RSTSm 0x20
+#define WRSTCSR_RSTEm 0x40
+#define WRSTCSR_WOVFm 0x80
+/* WDT0 register definitions end */
+
+/* SCI common registers and bits start */
+
+/* Receive Data Register (RDR) */
+/* Transmit Data Register (TDR) */
+/* Serial Mode Register (SMR) */
+#define SMR_CKS0m 0x01
+#define SMR_CKS1m 0x02
+#define SMR_CKSxm 0x03 /* Clock 3=/64, 2=/16, 1=/4, 0=/1 */
+#define SMR_MPm 0x04 /* 1=Multiprocessor format selected */
+#define SMR_STOPm 0x08 /* 1=2 stop bits, 0=1 stop bit */
+#define SMR_OEm 0x10 /* 1=Odd parity, 0=Even */
+#define SMR_PEm 0x20 /* 1=Parity addition and checking enabled */
+#define SMR_CHRm 0x40 /* 1=7-bit data, 0=8-bit */
+#define SMR_CAm 0x80 /* 1=Clocked, 0=Asynchronous */
+#define SCI_SMR_8N1 (0|0|0)
+#define SCI_SMR_7N1 (SMR_CHRm|0|0)
+#define SCI_SMR_8N2 (0 |0|SMR_STOPm)
+#define SCI_SMR_7N2 (SMR_CHRm|0|SMR_STOPm)
+#define SCI_SMR_8E1 (0 |SMR_PEm|0)
+#define SCI_SMR_7E1 (SMR_CHRm|SMR_PEm|0)
+#define SCI_SMR_8O1 (0 |SMR_PEm|SMR_OEm)
+#define SCI_SMR_7O1 (SMR_CHRm|SMR_PEm|SMR_OEm)
+/* Serial Control Register (SCR) */
+#define SCR_CKE0m 0x01 /* Clock Enable */
+#define SCR_CKE1m 0x02 /* */
+#define SCR_TEIEm 0x04 /* Transmit end interrupt (TEI) */
+#define SCR_MPIEm 0x08 /* Only multiprocessor RXI interrupt enabled */
+#define SCR_REm 0x10 /* Reception enabled */
+#define SCR_TEm 0x20 /* Transmission enabled* */
+#define SCR_RIEm 0x40 /* RXI interrupt requests enabled */
+#define SCR_TIEm 0x80 /* TXI interrupt requests enabled */
+/* Serial Status Register (SSR) */
+#define SSR_MPBTm 0x01 /* Value to send as bit 8 */
+#define SSR_MPBm 0x02 /* MP Bit 8 received value */
+#define SSR_TENDm 0x04 /* Transmit End */
+#define SSR_PERm 0x08 /* Parity error */
+#define SSR_FERm 0x10 /* Framing error */
+#define SSR_ORERm 0x20 /* Receive overflow */
+#define SSR_RDRFm 0x40 /* Set when reception ends normally */
+#define SSR_TDREm 0x80 /* Set when TDR empty or SCR_TE=0 */
+/* Bit Rate Register (BRR) */
+/* for async set to N=Fsys/(32*2^(2n)*baud)-1 where n=SMR_CKS */
+/* for sync set to N=Fsys/(4*2^(2n)*baud)-1 */
+/* Smart Card Mode Register (SCMR) */
+#define SCMR_SMIFm 0x01 /* 1=Smart card interface enabled */
+#define SCMR_SINVm 0x04 /* 1=TDR contents inverted */
+#define SCMR_SDIRm 0x08 /* 1=MSB-first, 0=LSB-first */
+/* I2C Bus Mode / Slave Address Register (ICMR/SAR)*/
+/* only for SCI0 and SCI1 */
+#define ICMR_BC0m 0x01 /* Bit Counter */
+#define ICMR_BC1m 0x02
+#define ICMR_BC2m 0x04
+#define ICMR_BCm (ICMR_BC0m|ICMR_BC1m|ICMR_BC2m)
+#define ICMR_CKS0m 0x08 /* Serial Clock Select */
+#define ICMR_CKS1m 0x10
+#define ICMR_CKS2m 0x20
+#define ICMR_CKSm (ICMR_CKS0m|ICMR_CKS1m|ICMR_CKS2m)
+#define ICMR_WAITm 0x40 /* 1 .. Wait between data and acknowledge */
+#define ICMR_MLSm 0x80 /* 0 .. MSB-first / 1 .. LSB-first */
+/* I2C Bus Control Register (ICCR) */
+#define ICCR_SCPm 0x01 /* Write 0 with BBSY to start/stop */
+#define ICCR_IRICm 0x02 /* 1 => interrupt requested */
+#define ICCR_BBSYm 0x04 /* 1 => bus is busy */
+#define ICCR_ACKEm 0x08 /* 1 => stop when no ACK detected */
+#define ICCR_TRSm 0x10 /* 1 .. transmit / 0 .. receive */
+#define ICCR_MSTm 0x20 /* 1 .. master mode / 0 .. slave mode */
+#define ICCR_IEICm 0x40 /* Interrupts enabled */
+#define ICCR_ICEm 0x80 /* 1 .. IIC enabled (ICMR,ICDR accessible) */
+ /* 0 .. IIC disabled (SAR,SARX accessible) */
+/* IIC Bus Status Register (ICSR) */
+#define ICSR_ACKBm 0x01 /* Acknowledge Bit */
+#define ICSR_ADZm 0x02 /* General Call Address Recognition */
+#define ICSR_AASm 0x04 /* Slave Address Recognition */
+#define ICSR_ALm 0x08 /* Arbitration Lost */
+#define ICSR_AASXm 0x10 /* Second Slave Address Recognition */
+#define ICSR_IRTRm 0x20 /* Continuous Transmission/Reception Interrupt */
+#define ICSR_STOPm 0x40 /* Normal Stop Condition Detection Flag */
+#define ICSR_ESTPm 0x80 /* Error Stop Condition Detection Flag */
+
+/* SCI common registers and bits end */
+
+
+#define SCI_SMR0 __PORT8 0xFFFF78 /* Serial Mode Register 0 */
+#define SMR0_CKS0m 0x01
+#define SMR0_CKS1m 0x02
+#define SMR0_MPm 0x04
+#define SMR0_STOPm 0x08
+#define SMR0_OEm 0x10
+#define SMR0_PEm 0x20
+#define SMR0_CHRm 0x40
+#define SMR0_CAm 0x80
+#define Smart_SMR0 __PORT8 0xFFFF78 /* Smart Card Mode Register 0 */
+#define IIC_ICCR0 __PORT8 0xFFFF78 /* I2C Bus Control Register */
+#define SCI_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */
+#define Smart_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */
+#define IIC_ICSR0 __PORT8 0xFFFF79 /* I2C Bus Status Register */
+#define SCI_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */
+#define Smart_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */
+#define SCR0_CKE0m 0x01
+#define SCR0_CKE1m 0x02
+#define SCR0_TEIEm 0x04
+#define SCR0_MPIEm 0x08
+#define SCR0_REm 0x10
+#define SCR0_TEm 0x20
+#define SCR0_RIEm 0x40
+#define SCR0_TIEm 0x80
+#define SCI_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */
+#define Smart_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */
+#define SCI_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */
+#define SSR0_MPBTm 0x01
+#define SSR0_MPBm 0x02
+#define SSR0_TENDm 0x04
+#define SSR0_PERm 0x08
+#define SSR0_FERm 0x10
+#define SSR0_ORERm 0x20
+#define SSR0_RDRFm 0x40
+#define SSR0_TDREm 0x80
+#define Smart_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */
+#define SCI_RDR0 __PORT8 0xFFFF7D /* Receive Data Register 0 */
+#define SCI_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */
+#define SCMR0_SMIFm 0x01
+#define SCMR0_SINVm 0x04
+#define SCMR0_SDIRm 0x08
+#define Smart_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */
+#define IIC_ICDR0 __PORT8 0xFFFF7E /* I2C Bus Data Register */
+#define IIC_SARX0 __PORT8 0xFFFF7E /* 2nd Slave Address Register */
+#define IIC_ICMR0 __PORT8 0xFFFF7F /* I2C Bus Mode Register */
+#define ICMR0_BC0FSm 0x01
+#define ICMR0_BC1m 0x02
+#define ICMR0_BC2m 0x04
+#define ICMR0_CKS0m 0x08
+#define ICMR0_CKS1m 0x10
+#define ICMR0_CKS2m 0x20
+#define ICMR0_WAITm 0x40
+#define ICMR0_MLSm 0x80
+#define IIC_SAR0 __PORT8 0xFFFF7F /* Slave Address Register */
+#define SCI_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
+#define SMR1_CKS0m 0x01
+#define SMR1_CKS1m 0x02
+#define SMR1_MPm 0x04
+#define SMR1_STOPm 0x08
+#define SMR1_OEm 0x10
+#define SMR1_PEm 0x20
+#define SMR1_CHRm 0x40
+#define SMR1_CAm 0x80
+#define IIC_ICCR1 __PORT8 0xFFFF80 /* I2C Bus Control Register */
+#define Smart_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
+#define SCI_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */
+#define Smart_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */
+#define IIC_ICSR1 __PORT8 0xFFFF81 /* I2C Bus Status Register */
+#define SCI_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */
+#define SCR1_CKE0m 0x01
+#define SCR1_CKE1m 0x02
+#define SCR1_TEIEm 0x04
+#define SCR1_MPIEm 0x08
+#define SCR1_REm 0x10
+#define SCR1_TEm 0x20
+#define SCR1_RIEm 0x40
+#define SCR1_TIEm 0x80
+#define Smart_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */
+#define SCI_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */
+#define Smart_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */
+#define SCI_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */
+#define SSR1_MPBTm 0x01
+#define SSR1_MPBm 0x02
+#define SSR1_TENDm 0x04
+#define SSR1_PERm 0x08
+#define SSR1_FERm 0x10
+#define SSR1_ORERm 0x20
+#define SSR1_RDRFm 0x40
+#define SSR1_TDREm 0x80
+#define Smart_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */
+#define SCI_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */
+#define Smart_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */
+#define SCI_SCMR1 __PORT8 0xFFFF86 /* Smart Card Mode Register 1 */
+#define SCMR1_SMIFm 0x01
+#define SCMR1_SINVm 0x04
+#define SCMR1_SDIRm 0x08
+#define IIC_ICDR1 __PORT8 0xFFFF86 /* I2C Bus Data Register */
+#define IIC_SARX1 __PORT8 0xFFFF86 /* 2nd Slave Address Register */
+#define IIC_ICMR1 __PORT8 0xFFFF87 /* -I2C Bus Mode Register */
+#define ICMR1_BC0FSm 0x01
+#define ICMR1_BC1m 0x02
+#define ICMR1_BC2m 0x04
+#define ICMR1_CKS0m 0x08
+#define ICMR1_CKS1m 0x10
+#define ICMR1_CKS2m 0x20
+#define ICMR1_WAITm 0x40
+#define ICMR1_MLSm 0x80
+#define IIC_SAR1 __PORT8 0xFFFF87 /* Slave Address Register */
+#define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
+#define SMR2_CKS0m 0x01
+#define SMR2_CKS1m 0x02
+#define SMR2_MPm 0x04
+#define SMR2_STOPm 0x08
+#define SMR2_OEm 0x10
+#define SMR2_PEm 0x20
+#define SMR2_CHRm 0x40
+#define SMR2_CAm 0x80
+#define Smart_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
+#define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
+#define Smart_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
+#define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
+#define SCR2_CKE0m 0x01
+#define SCR2_CKE1m 0x02
+#define SCR2_TEIEm 0x04
+#define SCR2_MPIEm 0x08
+#define SCR2_REm 0x10
+#define SCR2_TEm 0x20
+#define SCR2_RIEm 0x40
+#define SCR2_TIEm 0x80
+#define Smart_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
+#define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
+#define Smart_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
+#define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
+#define SSR2_MPBTm 0x01
+#define SSR2_MPBm 0x02
+#define SSR2_TENDm 0x04
+#define SSR2_PERm 0x08
+#define SSR2_FERm 0x10
+#define SSR2_ORERm 0x20
+#define SSR2_RDRFm 0x40
+#define SSR2_TDREm 0x80
+#define Smart_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
+#define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */
+#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
+#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
+#define SCMR2_SMIFm 0x01
+#define SCMR2_SINVm 0x04
+#define SCMR2_SDIRm 0x08
+
+/* Module A/D Converter */
+#define AD_ADDRAH __PORT8 0xFFFF90 /* AD Data Register AH */
+#define ADDRAH_AD2m 0x01
+#define ADDRAH_AD3m 0x02
+#define ADDRAH_AD4m 0x04
+#define ADDRAH_AD5m 0x08
+#define ADDRAH_AD6m 0x10
+#define ADDRAH_AD7m 0x20
+#define ADDRAH_AD8m 0x40
+#define ADDRAH_AD9m 0x80
+#define AD_ADDRAL __PORT8 0xFFFF91 /* AD Data Register AL*/
+#define ADDRAL_AD0m 0x40
+#define ADDRAL_AD1m 0x80
+#define AD_ADDRBH __PORT8 0xFFFF92 /* AD Data Register BH*/
+#define ADDRBH_AD2m 0x01
+#define ADDRBH_AD3m 0x02
+#define ADDRBH_AD4m 0x04
+#define ADDRBH_AD5m 0x08
+#define ADDRBH_AD6m 0x10
+#define ADDRBH_AD7m 0x20
+#define ADDRBH_AD8m 0x40
+#define ADDRBH_AD9m 0x80
+#define AD_ADDRBL __PORT8 0xFFFF93 /* AD Data Register BL*/
+#define ADDRBL_AD0m 0x40
+#define ADDRBL_AD1m 0x80
+#define AD_ADDRCH __PORT8 0xFFFF94 /* AD Data Register CH */
+#define ADDRCH_AD2m 0x01
+#define ADDRCH_AD3m 0x02
+#define ADDRCH_AD4m 0x04
+#define ADDRCH_AD5m 0x08
+#define ADDRCH_AD6m 0x10
+#define ADDRCH_AD7m 0x20
+#define ADDRCH_AD8m 0x40
+#define ADDRCH_AD9m 0x80
+#define AD_ADDRCL __PORT8 0xFFFF95 /* AD Data Register CH */
+#define ADDRCL_AD0m 0x40
+#define ADDRCL_AD1m 0x80
+#define AD_ADDRDH __PORT8 0xFFFF96 /* AD Data Register DH */
+#define ADDRDH_AD2m 0x01
+#define ADDRDH_AD3m 0x02
+#define ADDRDH_AD4m 0x04
+#define ADDRDH_AD5m 0x08
+#define ADDRDH_AD6m 0x10
+#define ADDRDH_AD7m 0x20
+#define ADDRDH_AD8m 0x40
+#define ADDRDH_AD9m 0x80
+#define AD_ADDRDL __PORT8 0xFFFF97 /* AD Data Register DL */
+#define ADDRDL_AD0m 0x40
+#define ADDRDL_AD1m 0x80
+#define AD_ADCSR __PORT8 0xFFFF98 /* AD ControlStatus Register */
+#define ADCSR_CH0m 0x01
+#define ADCSR_CH1m 0x02
+#define ADCSR_CH2m 0x04
+#define ADCSR_CH3m 0x08
+#define ADCSR_SCANm 0x10
+#define ADCSR_ADSTm 0x20
+#define ADCSR_ADIEm 0x40
+#define ADCSR_ADFm 0x80
+#define AD_ADCR __PORT8 0xFFFF99 /* AD Control Register */
+#define ADCR_CKS0m 0x04
+#define ADCR_CKS1m 0x08
+#define ADCR_TRGS0m 0x40
+#define ADCR_TRGS1m 0x80
+/* Module Timer*/
+#define TMR_TCSR1 __PORT8 0xFFFFA2 /* (R/W) Timer ControlStatus Register 1 */
+#define TCSR1_CKS0m 0x01
+#define TCSR1_CKS1m 0x02
+#define TCSR1_CKS2m 0x04
+#define TCSR1_OVFm 0x80
+#define TMR_TCNT1 __PORT8 0xFFFFA3 /* (R) Timer Counter 1 */
+/* Module A/D Converter */
+#define DA_DADR0 __PORT8 0xFFFFA4 /* DA Data Register 0 */
+#define DA_DADR1 __PORT8 0xFFFFA5 /* DA Data Register 1 */
+#define DA_DACR01 __PORT8 0xFFFFA6 /* DA Control Register 01 */
+#define DACR01_DAEm 0x20
+#define DACR01_DAOE0m 0x40
+#define DACR01_DAOE1m 0x80
+/* Module Flash Memory */
+#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */
+#define FLMCR1_Pm 0x01 /* Transition to program mode */
+#define FLMCR1_Em 0x02 /* Transition to erase mode */
+#define FLMCR1_PVm 0x04 /* Transition to program-verify mode */
+#define FLMCR1_EVm 0x08 /* Transition to erase-verify mode */
+#define FLMCR1_PSUm 0x10 /* Program setup when FWE = 1 and SWE1 = 1*/
+#define FLMCR1_ESUm 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */
+#define FLMCR1_SWEm 0x40 /* 1= enable writes when FWE=1 */
+#define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */
+#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */
+#define FLMCR2_FLERm 0x80 /* Flash memory modification error */
+#define FLM_EBR1 __PORT8 0xFFFFAA /* Erase Block Register 1 */
+#define EBR1_EB0m 0x01 /* Selects block to erase */
+#define EBR1_EB1m 0x02
+#define EBR1_EB2m 0x04
+#define EBR1_EB3m 0x08
+#define EBR1_EB4m 0x10
+#define EBR1_EB5m 0x20
+#define EBR1_EB6m 0x40
+#define EBR1_EB7m 0x80
+#define FLM_EBR2 __PORT8 0xFFFFAB /* Erase Block Register 2 */
+#define EBR2_EB8m 0x01
+#define EBR2_EB9m 0x02
+#define EBR2_EB10m 0x04
+#define EBR2_EB11m 0x08
+#define EBR2_EB12m 0x10 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */
+#define EBR2_EB13m 0x20 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */
+#define FLM_FLPWCR __PORT8 0xFFFFAC /* Flash Memory Power Control Register */
+#define FLPWCR_PDWNDm 0x80
+/* Module Port */
+#define DIO_PORT1 __PORT8 0xFFFFB0 /* DIO 1 Register */
+#define PORT1_P10m 0x01
+#define PORT1_P11m 0x02
+#define PORT1_P12m 0x04
+#define PORT1_P13m 0x08
+#define PORT1_P14m 0x10
+#define PORT1_P15m 0x20
+#define PORT1_P16m 0x40
+#define PORT1_P17m 0x80
+#define DIO_PORT3 __PORT8 0xFFFFB2 /* DIO 3 Register */
+#define PORT3_P30m 0x01
+#define PORT3_P31m 0x02
+#define PORT3_P32m 0x04
+#define PORT3_P33m 0x08
+#define PORT3_P34m 0x10
+#define PORT3_P35m 0x20
+#define DIO_PORT4 __PORT8 0xFFFFB3 /* DIO 4 Register */
+#define PORT4_P40m 0x01
+#define PORT4_P41m 0x02
+#define PORT4_P42m 0x04
+#define PORT4_P43m 0x08
+#define PORT4_P44m 0x10
+#define PORT4_P45m 0x20
+#define PORT4_P46m 0x40
+#define PORT4_P47m 0x80
+#define DIO_PORT9 __PORT8 0xFFFFB8 /* DIO 9 Register */
+#define PORT9_P90m 0x01
+#define PORT9_P91m 0x02
+#define PORT9_P92m 0x04
+#define PORT9_P93m 0x08
+#define DIO_PORTA __PORT8 0xFFFFB9 /* DIO A Register */
+#define PORTA_PA0m 0x01
+#define PORTA_PA1m 0x02
+#define PORTA_PA2m 0x04
+#define PORTA_PA3m 0x08
+#define DIO_PORTB __PORT8 0xFFFFBA /* DIO B Register */
+#define PORTB_PB0m 0x01
+#define PORTB_PB1m 0x02
+#define PORTB_PB2m 0x04
+#define PORTB_PB3m 0x08
+#define PORTB_PB4m 0x10
+#define PORTB_PB5m 0x20
+#define PORTB_PB6m 0x40
+#define PORTB_PB7m 0x80
+#define DIO_PORTC __PORT8 0xFFFFBB /* DIO C Register */
+#define PORTC_PC0m 0x01
+#define PORTC_PC1m 0x02
+#define PORTC_PC2m 0x04
+#define PORTC_PC3m 0x08
+#define PORTC_PC4m 0x10
+#define PORTC_PC5m 0x20
+#define PORTC_PC6m 0x40
+#define PORTC_PC7m 0x80
+#define DIO_PORTD __PORT8 0xFFFFBC /* DIO D Register */
+#define PORTD_PD0m 0x01
+#define PORTD_PD1m 0x02
+#define PORTD_PD2m 0x04
+#define PORTD_PD3m 0x08
+#define PORTD_PD4m 0x10
+#define PORTD_PD5m 0x20
+#define PORTD_PD6m 0x40
+#define PORTD_PD7m 0x80
+#define DIO_PORTE __PORT8 0xFFFFBD /* DIO E Register */
+#define PORTE_PE0m 0x01
+#define PORTE_PE1m 0x02
+#define PORTE_PE2m 0x04
+#define PORTE_PE3m 0x08
+#define PORTE_PE4m 0x10
+#define PORTE_PE5m 0x20
+#define PORTE_PE6m 0x40
+#define PORTE_PE7m 0x80
+#define DIO_PORTF __PORT8 0xFFFFBE /* DIO F Register */
+#define PORTF_PF0m 0x01
+#define PORTF_PF3m 0x08
+#define PORTF_PF4m 0x10
+#define PORTF_PF5m 0x20
+#define PORTF_PF6m 0x40
+#define PORTF_PF7m 0x80
+
+// aditional definition
+
+
+#define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */
+#define SCRX_FLSHEm 0x08
+#define SCRX_IICEm 0x10
+#define SCRX_IICX0m 0x20
+#define SCRX_IICX1m 0x40
+
+
+#define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */
+#define LPWRCR_STC0m 0x01 /* */
+#define LPWRCR_STC1m 0x02
+#define LPWRCR_STCxm 0x03
+#define LPWRCR_RFCUTm 0x08
+#define LPWRCR_SUBSTPm 0x10
+#define LPWRCR_NESELm 0x20
+#define LPWRCR_LSONm 0x40
+#define LPWRCR_DTONm 0x80
+
+
+
+/* define serial control registers */
+#define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
+#define SMR2_CKS0m 0x01
+#define SMR2_CKS1m 0x02
+#define SMR2_MPm 0x04
+#define SMR2_STOPm 0x08
+#define SMR2_OEm 0x10
+#define SMR2_PEm 0x20
+#define SMR2_CHRm 0x40
+#define SMR2_CAm 0x80
+#define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
+#define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
+#define SCR2_CKE0m 0x01
+#define SCR2_CKE1m 0x02
+#define SCR2_TEIEm 0x04
+#define SCR2_MPIEm 0x08
+#define SCR2_REm 0x10
+#define SCR2_TEm 0x20
+#define SCR2_RIEm 0x40
+#define SCR2_TIEm 0x80
+#define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
+#define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
+#define SSR2_MPBTm 0x01
+#define SSR2_MPBm 0x02
+#define SSR2_TENDm 0x04
+#define SSR2_PERm 0x08
+#define SSR2_FERm 0x10
+#define SSR2_ORERm 0x20
+#define SSR2_RDRFm 0x40
+#define SSR2_TDREm 0x80
+#define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */
+#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
+#define SCMR2_SMIFm 0x01
+#define SCMR2_SINVm 0x04
+#define SCMR2_SDIRm 0x08
+/* END define serial control registers */
+
+
+/* Module Stop Control Register */
+#define SYS_MSTPCRA __PORT8 0xFFFDE8 /* Module Stop Control Register A */
+#define MSTPCRA_MSTPA0m 0x01
+#define MSTPCRA_MSTPA1m 0x02
+#define MSTPCRA_ADCm 0x02
+#define MSTPCRA_MSTPA2m 0x04
+#define MSTPCRA_DA01m 0x04
+#define MSTPCRA_MSTPA3m 0x08
+#define MSTPCRA_PPGm 0x08
+#define MSTPCRA_MSTPA4m 0x10
+#define MSTPCRA_MSTPA5m 0x20
+#define MSTPCRA_TPUm 0x20
+#define MSTPCRA_MSTPA6m 0x40
+#define MSTPCRA_DTCm 0x40
+#define MSTPCRA_MSTPA7m 0x80
+#define SYS_MSTPCRB __PORT8 0xFFFDE9 /* Module Stop Control Register B */
+#define MSTPCRB_MSTPB0m 0x01
+#define MSTPCRB_MSTPB1m 0x02
+#define MSTPCRB_MSTPB2m 0x04
+#define MSTPCRB_MSTPB3m 0x08
+#define MSTPCRB_IIC1m 0x08
+#define MSTPCRB_MSTPB4m 0x10
+#define MSTPCRB_IIC0m 0x10
+#define MSTPCRB_MSTPB5m 0x20
+#define MSTPCRB_SCI2m 0x20
+#define MSTPCRB_MSTPB6m 0x40
+#define MSTPCRB_SCI1m 0x40
+#define MSTPCRB_MSTPB7m 0x80
+#define MSTPCRB_SCI0m 0x80
+#define SYS_MSTPCRC __PORT8 0xFFFDEA /* Module Stop Control Register C */
+#define MSTPCRC_MSTPC0m 0x01
+#define MSTPCRC_MSTPC1m 0x02
+#define MSTPCRC_MSTPC2m 0x04
+#define MSTPCRC_HCAN1m 0x04
+#define MSTPCRC_MSTPC3m 0x08
+#define MSTPCRC_HCAN0m 0x08
+#define MSTPCRC_MSTPC4m 0x10
+#define MSTPCRC_PBCm 0x10
+#define MSTPCRC_MSTPC5m 0x20
+#define MSTPCRC_MSTPC6m 0x40
+#define MSTPCRC_SCI4m 0x40
+#define MSTPCRC_MSTPC7m 0x80
+#define MSTPCRC_SCI3m 0x80
+#define SYS_MSTPCRD __PORT8 0xFFFC60 /* Module Stop Control Register D */
+#define MSTPCRD_MSTPD7m 0x80
+#define MSTPCRD_PWMm 0x80
+ /* END Module Stop Control Register */
+
+ /* start Flash register compatibility with 2633 programs (only different names of existing FLMCR1 bits)*/ /* // comented are the same */
+//#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */
+#define FLMCR1_P1m 0x01 /* Transition to program mode */
+#define FLMCR1_E1m 0x02 /* Transition to erase mode */
+#define FLMCR1_PV1m 0x04 /* Transition to program-verify mode */
+#define FLMCR1_EV1m 0x08 /* Transition to erase-verify mode */
+#define FLMCR1_PSU1m 0x10 /* Program setup when FWE = 1 and SWE1 = 1*/
+#define FLMCR1_ESU1m 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */
+#define FLMCR1_SWE1m 0x40 /* 1= enable writes when FWE=1 */
+//#define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */
+//#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */
+//#define FLMCR2_FLERm 0x80 /* Flash memory modification error */
+ /* end Flash register compatibility with 2633 (only different names of FLMCR1 bits)*/
+
+/* exception vectors numbers */ // nechat schvalit !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+#define EXCPTVEC_POWRES 0
+#define EXCPTVEC_MANRES 1
+#define EXCPTVEC_TRACE 5
+#define EXCPTVEC_DIRTRANS 6
+#define EXCPTVEC_NMI 7
+#define EXCPTVEC_TRAP0 8
+#define EXCPTVEC_TRAP1 9
+#define EXCPTVEC_TRAP2 10
+#define EXCPTVEC_TRAP3 11
+#define EXCPTVEC_IRQ0 16
+#define EXCPTVEC_IRQ1 17
+#define EXCPTVEC_IRQ2 18
+#define EXCPTVEC_IRQ3 19
+#define EXCPTVEC_IRQ4 20
+#define EXCPTVEC_IRQ5 21
+#define EXCPTVEC_IRQ6 22
+#define EXCPTVEC_IRQ7 23
+#define EXCPTVEC_SWDEND 24
+#define EXCPTVEC_WOVI0 25
+#define EXCPTVEC_CMI 26
+#define EXCPTVEC_PBC 27
+#define EXCPTVEC_ADI 28
+#define EXCPTVEC_WOVI1 29
+#define EXCPTVEC_TGI0A 32 /* TPU 0 */
+#define EXCPTVEC_TGI0B 33
+#define EXCPTVEC_TGI0C 34
+#define EXCPTVEC_TGI0D 35
+#define EXCPTVEC_TCI0V 36
+#define EXCPTVEC_TGI1A 40 /* TPU 1 */
+#define EXCPTVEC_TGI1B 41
+#define EXCPTVEC_TCI1V 42
+#define EXCPTVEC_TCI1U 43
+#define EXCPTVEC_TGI2A 44 /* TPU 2 */
+#define EXCPTVEC_TGI2B 45
+#define EXCPTVEC_TCI2V 46
+#define EXCPTVEC_TCI2U 47
+#define EXCPTVEC_TGI3A 48 /* TPU 3 */
+#define EXCPTVEC_TGI3B 49
+#define EXCPTVEC_TGI3C 50
+#define EXCPTVEC_TGI3D 51
+#define EXCPTVEC_TCI3V 52
+#define EXCPTVEC_TGI4A 56 /* TPU 4 */
+#define EXCPTVEC_TGI4B 57
+#define EXCPTVEC_TCI4V 58
+#define EXCPTVEC_TCI4U 59
+#define EXCPTVEC_TGI5A 60 /* TPU 5 */
+#define EXCPTVEC_TGI5B 61
+#define EXCPTVEC_TCI5V 62
+#define EXCPTVEC_TCI5U 63
+#define EXCPTVEC_CMIA0 64 /* 8 bit tim 0 */
+#define EXCPTVEC_CMIB0 65
+#define EXCPTVEC_OVI0 66
+#define EXCPTVEC_CMIA1 68 /* 8 bit tim 1 */
+#define EXCPTVEC_CMIB1 69
+#define EXCPTVEC_OVI1 70
+#define EXCPTVEC_DEND0A 72 /* DMAC */
+#define EXCPTVEC_DEND0B 73
+#define EXCPTVEC_DEND1A 74
+#define EXCPTVEC_DEND1B 75
+#define EXCPTVEC_ERI0 80 /* SCI 0 */
+#define EXCPTVEC_RXI0 81
+#define EXCPTVEC_TXI0 82
+#define EXCPTVEC_TEI0 83
+#define EXCPTVEC_ERI1 84 /* SCI 1 */
+#define EXCPTVEC_RXI1 85
+#define EXCPTVEC_TXI1 86
+#define EXCPTVEC_TEI1 87
+#define EXCPTVEC_ERI2 88 /* SCI 2 */
+#define EXCPTVEC_RXI2 89
+#define EXCPTVEC_TXI2 90
+#define EXCPTVEC_TEI2 91
+#define EXCPTVEC_CMIA2 92 /* 8 bit tim 2 */
+#define EXCPTVEC_CMIB2 93
+#define EXCPTVEC_OVI2 94
+#define EXCPTVEC_CMIA3 96 /* 8 bit tim 3 */
+#define EXCPTVEC_CMIB3 97
+#define EXCPTVEC_OVI3 98
+#define EXCPTVEC_IICI0 100 /* IIC 0 */
+#define EXCPTVEC_DDCSW1 101
+#define EXCPTVEC_IICI1 102 /* IIC 1 */
+#define EXCPTVEC_ERI3 120 /* SCI 3 */
+#define EXCPTVEC_RXI3 121
+#define EXCPTVEC_TXI3 122
+#define EXCPTVEC_TEI3 123
+#define EXCPTVEC_ERI4 124 /* SCI 4 */
+#define EXCPTVEC_RXI4 125
+#define EXCPTVEC_TXI4 126
+#define EXCPTVEC_TEI4 127
+
+
+#endif /* _H82639H_H */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = $(BOARD)
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = defines libs
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ system_def.h - common cover for definition of hardware adresses,
+ registers, timing and other hardware dependant
+ parts of embedded hardware
+
+ Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#ifndef _SYSTEM_DEF_H_
+#define _SYSTEM_DEF_H_
+
+#include <types.h>
+
+#define WITH_SFI_SEL
+
+#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
+/* Software version */
+#define SW_VER_ID "H8CANUSB"
+#define SW_VER_MAJOR 0
+#define SW_VER_MINOR 1
+#define SW_VER_PATCH 0
+#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
+/* Hardware version */
+#define HW_VER_ID "H8CANUSB"
+#define HW_VER_MAJOR 1
+#define HW_VER_MINOR 0
+#define HW_VER_PATCH 0
+#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
+/* Version of mechanical */
+#define MECH_VER_ID "H8CANUSB"
+#define MECH_VER_MAJOR 0
+#define MECH_VER_MINOR 0
+#define MECH_VER_PATCH 0
+#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
+
+/*#include <system_def_jt_usb1.h>*/
+#include <system_def_h8canusb.h>
+
+#endif /* _SYSTEM_DEF_H_ */
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ .h - definition of hardware adresses and registers
+ of the second prototype version of syringe
+ infussion pump
+
+ Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#ifndef _SYSTEM_DEF_HW01_H_
+#define _SYSTEM_DEF_HW01_H_
+
+//#define CPU_REF_HZ 11059200l /* reference clock frequency */
+//#define CPU_SYS_HZ 11059200l /* default system clock frequency */
+
+#define CPU_REF_HZ 18423000l /* reference clock frequency */
+//#define CPU_SYS_HZ 24000000l /* default system clock frequency */
+#define CPU_SYS_HZ 18423000l /* default system clock frequency */
+
+
+unsigned long cpu_ref_hz; /* actual external XTAL reference */
+unsigned long cpu_sys_hz; /* actual system clock frequency */
+
+volatile unsigned long msec_time;
+
+/* Keyboard KL41 (CS6) */
+#define KL41_LCD_INST (volatile __u8 * const)(0xc00000)
+#define KL41_LCD_STAT (volatile __u8 * const)(0xc00001)
+#define KL41_LCD_WDATA (volatile __u8 * const)(0xc00002)
+#define KL41_LCD_RDATA (volatile __u8 * const)(0xc00003)
+#define KL41_LED_WR (volatile __u8 * const)(0xc00001)
+#define KL41_KBD_WR (volatile __u8 * const)(0xc00003)
+#define KL41_KBD_RD (volatile __u8 * const)(0xc00004)
+
+#define KL41_SUPPORT_ENABLED
+
+
+
+/* SGM Small graphics module (CS2) */
+#define SGM_LCD_DATA (volatile __u8 * const)(0x400000)
+#define SGM_LCD_CMD (volatile __u8 * const)(0x400001)
+#define SGM_LCD_STAT (volatile __u8 * const)(0x400001)
+
+#define SGM_SUPPORT_ENABLED
+
+
+
+/* XRAM 1 MB (CS1) */
+#define XRAM_START (volatile __u8 * const)(0x200000)
+
+#define XRAM_SUPPORT_ENABLED
+
+
+
+/* LED color mask LED1 msb .. LED2 lsb*/
+#define SGM_LED_G_MASK 0x9249
+#define SGM_LED_Y_MASK 0x4924
+#define SGM_LED_R_MASK 0x2492
+
+/* Peripherals (CS3) decoded from A13 to A15 */
+#define SGM_LED (volatile __u8 * const)(0x600000)
+#define SGM_LED1 (volatile __u8 * const)(0x600000)
+#define SGM_LED2 (volatile __u8 * const)(0x602000)
+#define SGM_KBDI (volatile __u8 * const)(0x604000)
+#define SGM_KBDO (volatile __u8 * const)(0x606000)
+#define STPM_OUT STPM_OUT_not_defined
+ /* 2x 4 bit current, SGN P1.0, P1.1 */
+ /* DA2 current multiplier, P1.3 enable */
+ /* TCLKC and TCLKD for incremental encoder */
+ /* PWM outputs P1.0=TIOCA0, P1.1=TIOCB0 */
+ /* End of motion PF.7 */
+/*#define PWRCTRL_OUT (volatile __u8 * const)(0x???) */
+#define PWRCTRL_SYROPm 0x01 /* 1 - open syringe by selenoid */
+#define PWRCTRL_SYROPLm 0x02 /* 1 - open syringe by selenoid */
+#define PWRCTRL_BEEPENm 0x04 /* 1 - switch beep on */
+/*#define PWRCTRL_BEEPVOLm 0x0c*/ /* beep volume */
+#define PWRCTRL_BACKLm 0x10 /* 1 - enable backlight */
+ /* DA3 - brightness */
+ /* DA0 - contrast */
+#define PWRCTRL_STMOFFm 0x40 /* 1 - switch off motor */
+#define PWRCTRL_BATLEDm 0x80 /* 1 - switch on battery LED */
+/*#define PWRCTRL_THUMBPWRm P1.7*/ /* 1 - power for thumb sensors */
+
+/* Mechanical limit reached - P1.4 */
+#define MECH_LIMT_SW_a DIO_PORT1
+#define MECH_LIMT_SW_m 0x10
+
+/* Buffer stransferred to second board power control register */
+volatile short scch_pwrctrl_buf;
+
+/* SRAM 32 kB (CS3) */
+#define SRAM_START (volatile __u8 * const)(0x610000)
+
+
+#if 1
+#define ISR_USB_INTV EXCPTVEC_IRQ6 /* pin IRQ6 on PG.0 */
+#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x600000)
+#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x600000)
+#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x600001)
+
+/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
+#undef PDIUSB_WITH_ADD_IRQ_HANDLER
+#define PDIUSB_WITH_EXCPTVECT_SET
+#define PDIUSB_SUPPORT_ENABLED
+#endif
+
+
+
+/* IDE (CS4) (CS5) powered by PF2 */
+#define SIDE_START1 (volatile __u8 * const)(0x800000)
+#define SIDE_START2 (volatile __u8 * const)(0xA00000)
+#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
+#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
+#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
+#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
+#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
+#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
+#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
+#define IDE0_STATUS (SIDE_START1+14) /* Status */
+#define IDE0_SELECT IDE0_CURRENT
+#define IDE0_FEATURE IDE0_ERROR
+#define IDE0_COMMAND IDE0_STATUS /* Command */
+
+#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
+#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
+
+#define IDE0_SETPWR(pwr) do{ \
+ if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
+ else atomic_set_mask_b1(4,DIO_PFDR); \
+ }while(0)
+
+#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
+
+#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
+ #define IDE_SWAP_BYTES
+#endif
+
+#define IDE0_SUPPORT_ENABLED
+
+
+
+/* IRAM 16 kB of on-chip memory */
+/* 0xffb000-0xffcfff .. 8 kB free */
+/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
+/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
+/* 0xffffc0-0xffffff .. 64 B free*/
+#define IRAM_START (volatile __u8 * const)(0xffb000)
+#define IRAM_START1 (volatile __u8 * const)(0xffe000)
+#define FRAM_START (volatile __u8 * const)(0xffffc0)
+
+/* SCI0 - IrDA */
+/* SCI1 - IIC0 (P34, P35) */
+/* SCI2 - Boot */
+/* SCI3 - SPI */
+/* SCI4 - RS232/485 */
+
+/* IRQ0 - RTC */
+/* IRQ1 - Index mark */
+/* IRQ6 - IDE */
+
+/* Some registers are read only on H8S processors */
+/* We use shaddow registers for some of them */
+#define SHADDOW_REG_ALT(_reg,_mask,_xor) \
+ (*(_reg)=_reg##_shaddow=(_reg##_shaddow&~(_mask))^(_xor))
+
+#define SHADDOW_REG_SET(_reg,_mask) \
+ (*(_reg)=_reg##_shaddow|=(_mask))
+
+#define SHADDOW_REG_CLR(_reg,_mask) \
+ (*(_reg)=_reg##_shaddow&=~(_mask))
+
+#define SHADDOW_REG_RD(_reg) \
+ (_reg##_shaddow)
+
+#define SHADDOW_REG_WR(_reg,_val) \
+ (*(_reg)=_reg##_shaddow=(_val))
+
+__u8 DIO_P1DDR_shaddow;
+__u8 DIO_P3DDR_shaddow;
+__u8 DIO_PFDDR_shaddow;
+__u8 PWRCTRL_OUT_shaddow;
+
+#endif /* _SYSTEM_DEF_HW01_H_ */
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ system_def_h8canusb.h - definition of hardware adresses and registers
+
+ Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#ifndef _SYSTEM_DEF_HW01_H_
+#define _SYSTEM_DEF_HW01_H_
+
+//#define CPU_REF_HZ 11059200l /* reference clock frequency */
+//#define CPU_SYS_HZ 11059200l /* default system clock frequency */
+
+//#define CPU_REF_HZ 18423000l /* reference clock for EDK2638 */
+//#define CPU_SYS_HZ 18423000l /* default system for EDK2638 */
+
+#define CPU_REF_HZ 5000000l /* reference clock for H8CANUSB */
+#define CPU_SYS_HZ 20000000l /* default system for H8CANUSB */
+
+
+unsigned long cpu_ref_hz; /* actual external XTAL reference */
+unsigned long cpu_sys_hz; /* actual system clock frequency */
+
+volatile unsigned long msec_time;
+
+/* Keyboard KL41 (CS3) */
+#define KL41_LCD_INST (volatile __u8 * const)(0x700000)
+#define KL41_LCD_STAT (volatile __u8 * const)(0x700001)
+#define KL41_LCD_WDATA (volatile __u8 * const)(0x700002)
+#define KL41_LCD_RDATA (volatile __u8 * const)(0x700003)
+#define KL41_LED_WR (volatile __u8 * const)(0x700001)
+#define KL41_KBD_WR (volatile __u8 * const)(0x700003)
+#define KL41_KBD_RD (volatile __u8 * const)(0x700004)
+
+#define KL41_SUPPORT_ENABLED
+
+
+
+/* SGM Small graphics LCD module 240x64 (CS3) */
+#define SGM_LCD_DATA (volatile __u8 * const)(0x700000)
+#define SGM_LCD_CMD (volatile __u8 * const)(0x700001)
+#define SGM_LCD_STAT (volatile __u8 * const)(0x700001)
+/* Keyboard on MO_KBD1 */
+#define SGM_KBDI (volatile __u8 * const)(0x700002)
+#define SGM_KBDO (volatile __u8 * const)(0x700002)
+
+//#define SGM_SUPPORT_ENABLED
+
+/* XRAM 1 MB (CS1) */
+#define XRAM_START (volatile __u8 * const)(0x200000)
+
+#define XRAM_SUPPORT_ENABLED
+
+
+/* Buffer stransferred to second board power control register */
+volatile short scch_pwrctrl_buf;
+
+/* SRAM 32 kB (CS3) */
+//#define SRAM_START (volatile __u8 * const)(0x610000)
+
+
+#if 1
+#define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
+#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
+#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
+#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
+
+/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
+#undef PDIUSB_WITH_ADD_IRQ_HANDLER
+#define PDIUSB_WITH_EXCPTVECT_SET
+#define PDIUSB_SUPPORT_ENABLED
+#endif
+
+
+
+/* IDE (CS4) (CS5) powered by PF2 */
+#define SIDE_START1 (volatile __u8 * const)(0x800000)
+#define SIDE_START2 (volatile __u8 * const)(0xA00000)
+#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
+#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
+#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
+#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
+#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
+#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
+#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
+#define IDE0_STATUS (SIDE_START1+14) /* Status */
+#define IDE0_SELECT IDE0_CURRENT
+#define IDE0_FEATURE IDE0_ERROR
+#define IDE0_COMMAND IDE0_STATUS /* Command */
+
+#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
+#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
+
+#define IDE0_SETPWR(pwr) do{ \
+ if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
+ else atomic_set_mask_b1(4,DIO_PFDR); \
+ }while(0)
+
+#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
+
+#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
+ #define IDE_SWAP_BYTES
+#endif
+
+#define IDE0_SUPPORT_ENABLED
+
+
+
+/* IRAM 16 kB of on-chip memory */
+/* 0xffb000-0xffcfff .. 8 kB free */
+/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
+/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
+/* 0xffffc0-0xffffff .. 64 B free*/
+#define IRAM_START (volatile __u8 * const)(0xffb000)
+#define IRAM_START1 (volatile __u8 * const)(0xffe000)
+#define FRAM_START (volatile __u8 * const)(0xffffc0)
+
+/* SCI0 - IrDA */
+/* SCI1 - IIC0 (P34, P35) */
+/* SCI2 - Boot */
+/* SCI3 - SPI */
+/* SCI4 - RS232/485 */
+
+/* IRQ0 - RTC */
+/* IRQ1 - Index mark */
+/* IRQ6 - IDE */
+
+/* Some registers are read only on H8S processors */
+/* We use shaddow registers for some of them */
+#define SHADDOW_REG_ALT(_reg,_mask,_xor) \
+ (*(_reg)=_reg##_shaddow=(_reg##_shaddow&~(_mask))^(_xor))
+
+#define SHADDOW_REG_SET(_reg,_mask) \
+ (*(_reg)=_reg##_shaddow|=(_mask))
+
+#define SHADDOW_REG_CLR(_reg,_mask) \
+ (*(_reg)=_reg##_shaddow&=~(_mask))
+
+#define SHADDOW_REG_RD(_reg) \
+ (_reg##_shaddow)
+
+#define SHADDOW_REG_WR(_reg,_val) \
+ (*(_reg)=_reg##_shaddow=(_val))
+
+__u8 DIO_P1DDR_shaddow;
+__u8 DIO_P3DDR_shaddow;
+__u8 DIO_PFDDR_shaddow;
+__u8 DIO_PJDDR_shaddow;
+__u8 PWRCTRL_OUT_shaddow;
+
+#endif /* _SYSTEM_DEF_HW01_H_ */
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ system_def_jt_usb1.h - definition of hardware adresses and registers
+ of the second prototype version of syringe
+ infussion pump
+
+ Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#ifndef _SYSTEM_DEF_HW01_H_
+#define _SYSTEM_DEF_HW01_H_
+
+//#define CPU_REF_HZ 11059200l /* reference clock frequency */
+//#define CPU_SYS_HZ 11059200l /* default system clock frequency */
+
+#define CPU_REF_HZ 4000000l /* reference clock frequency */
+//#define CPU_SYS_HZ 24000000l /* default system clock frequency */
+#define CPU_SYS_HZ 16000000l /* default system clock frequency */
+
+
+unsigned long cpu_ref_hz; /* actual external XTAL reference */
+unsigned long cpu_sys_hz; /* actual system clock frequency */
+
+volatile unsigned long msec_time;
+#if 0
+/* Keyboard KL41 (CS6) */
+#define KL41_LCD_INST (volatile __u8 * const)(0xc00000)
+#define KL41_LCD_STAT (volatile __u8 * const)(0xc00001)
+#define KL41_LCD_WDATA (volatile __u8 * const)(0xc00002)
+#define KL41_LCD_RDATA (volatile __u8 * const)(0xc00003)
+#define KL41_LED_WR (volatile __u8 * const)(0xc00001)
+#define KL41_KBD_WR (volatile __u8 * const)(0xc00003)
+#define KL41_KBD_RD (volatile __u8 * const)(0xc00004)
+
+#define KL41_SUPPORT_ENABLED
+#endif
+
+#if 0
+/* SGM Small graphics module (CS2) */
+#define SGM_LCD_DATA (volatile __u8 * const)(0x400000)
+#define SGM_LCD_CMD (volatile __u8 * const)(0x400001)
+#define SGM_LCD_STAT (volatile __u8 * const)(0x400001)
+
+#define SGM_SUPPORT_ENABLED
+#endif
+
+#if 0
+/* XRAM 1 MB (CS1) */
+#define XRAM_START (volatile __u8 * const)(0x200000)
+
+#define XRAM_SUPPORT_ENABLED
+#endif
+
+#if 0
+/* LED color mask LED1 msb .. LED2 lsb*/
+#define SGM_LED_G_MASK 0x9249
+#define SGM_LED_Y_MASK 0x4924
+#define SGM_LED_R_MASK 0x2492
+
+/* Peripherals (CS3) decoded from A13 to A15 */
+#define SGM_LED (volatile __u8 * const)(0x600000)
+#define SGM_LED1 (volatile __u8 * const)(0x600000)
+#define SGM_LED2 (volatile __u8 * const)(0x602000)
+#define SGM_KBDI (volatile __u8 * const)(0x604000)
+#define SGM_KBDO (volatile __u8 * const)(0x606000)
+#define STPM_OUT STPM_OUT_not_defined
+ /* 2x 4 bit current, SGN P1.0, P1.1 */
+ /* DA2 current multiplier, P1.3 enable */
+ /* TCLKC and TCLKD for incremental encoder */
+ /* PWM outputs P1.0=TIOCA0, P1.1=TIOCB0 */
+ /* End of motion PF.7 */
+/*#define PWRCTRL_OUT (volatile __u8 * const)(0x???) */
+#define PWRCTRL_SYROPm 0x01 /* 1 - open syringe by selenoid */
+#define PWRCTRL_SYROPLm 0x02 /* 1 - open syringe by selenoid */
+#define PWRCTRL_BEEPENm 0x04 /* 1 - switch beep on */
+/*#define PWRCTRL_BEEPVOLm 0x0c*/ /* beep volume */
+#define PWRCTRL_BACKLm 0x10 /* 1 - enable backlight */
+ /* DA3 - brightness */
+ /* DA0 - contrast */
+#define PWRCTRL_STMOFFm 0x40 /* 1 - switch off motor */
+#define PWRCTRL_BATLEDm 0x80 /* 1 - switch on battery LED */
+/*#define PWRCTRL_THUMBPWRm P1.7*/ /* 1 - power for thumb sensors */
+
+/* Mechanical limit reached - P1.4 */
+#define MECH_LIMT_SW_a DIO_PORT1
+#define MECH_LIMT_SW_m 0x10
+
+/* Buffer stransferred to second board power control register */
+volatile short scch_pwrctrl_buf;
+
+/* SRAM 32 kB (CS3) */
+#define SRAM_START (volatile __u8 * const)(0x610000)
+#endif
+
+#if 1
+#define ISR_USB_INTV EXCPTVEC_IRQ6 /* pin IRQ6 on PG.0 */
+#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x600000)
+#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x600000)
+#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x600001)
+
+/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
+#undef PDIUSB_WITH_ADD_IRQ_HANDLER
+#define PDIUSB_WITH_EXCPTVECT_SET
+#define PDIUSB_SUPPORT_ENABLED
+#endif
+
+
+#if 0
+/* IDE (CS4) (CS5) powered by PF2 */
+#define SIDE_START1 (volatile __u8 * const)(0x800000)
+#define SIDE_START2 (volatile __u8 * const)(0xA00000)
+#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
+#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
+#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
+#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
+#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
+#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
+#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
+#define IDE0_STATUS (SIDE_START1+14) /* Status */
+#define IDE0_SELECT IDE0_CURRENT
+#define IDE0_FEATURE IDE0_ERROR
+#define IDE0_COMMAND IDE0_STATUS /* Command */
+
+#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
+#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
+
+#define IDE0_SETPWR(pwr) do{ \
+ if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
+ else atomic_set_mask_b1(4,DIO_PFDR); \
+ }while(0)
+
+#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
+
+#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
+ #define IDE_SWAP_BYTES
+#endif
+
+#define IDE0_SUPPORT_ENABLED
+#endif
+
+
+/* IRAM 16 kB of on-chip memory */
+/* 0xffb000-0xffcfff .. 8 kB free */
+/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
+/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
+/* 0xffffc0-0xffffff .. 64 B free*/
+#define IRAM_START (volatile __u8 * const)(0xffb000)
+#define IRAM_START1 (volatile __u8 * const)(0xffe000)
+#define FRAM_START (volatile __u8 * const)(0xffffc0)
+
+/* SCI0 - IrDA */
+/* SCI1 - IIC0 (P34, P35) */
+/* SCI2 - Boot */
+/* SCI3 - SPI */
+/* SCI4 - RS232/485 */
+
+/* IRQ0 - RTC */
+/* IRQ1 - Index mark */
+/* IRQ6 - IDE */
+
+/* Some registers are read only on H8S processors */
+/* We use shaddow registers for some of them */
+#define SHADDOW_REG_ALT(_reg,_mask,_xor) \
+ (*(_reg)=_reg##_shaddow=(_reg##_shaddow&~(_mask))^(_xor))
+
+#define SHADDOW_REG_SET(_reg,_mask) \
+ (*(_reg)=_reg##_shaddow|=(_mask))
+
+#define SHADDOW_REG_CLR(_reg,_mask) \
+ (*(_reg)=_reg##_shaddow&=~(_mask))
+
+#define SHADDOW_REG_RD(_reg) \
+ (_reg##_shaddow)
+
+#define SHADDOW_REG_WR(_reg,_val) \
+ (*(_reg)=_reg##_shaddow=(_val))
+
+__u8 DIO_P1DDR_shaddow;
+__u8 DIO_P3DDR_shaddow;
+__u8 DIO_P7DDR_shaddow;
+__u8 DIO_PFDDR_shaddow;
+__u8 DIO_PGDDR_shaddow;
+__u8 PWRCTRL_OUT_shaddow;
+
+#endif /* _SYSTEM_DEF_HW01_H_ */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+lib_LDSCRIPT = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "edk2638.ld-cfg"
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ *(EXCLUDE_FILE(*boot_fn.o) .text)
+ *(EXCLUDE_FILE(*boot_fn.o) .rodata)
+ *(.strings)
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .data :
+ {
+ ___data_lma = . ;
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .bss :
+ {
+ . = ALIGN( 0x4 ) ;
+ _bss_start = ALIGN( 0x4 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ; ;
+ } > bloader
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "edk2638.ld-cfg"
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .fvector :
+ {
+ ___flashbb_vector = . ;
+ LONG( ABSOLUTE( _start ) )
+ *(.fvector)
+ } > flashvec
+
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ *(.strings)
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > flashbb
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ ___data_lma = ALIGN( 0x4 ) ;
+ } > flashbb /*at> flashusr*/
+
+ .data :
+ AT ( ADDR( .tors ) + SIZEOF( .tors ) )
+ {
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > iram1
+
+ /* ___data_lma = LOADADDR(.data) ; */
+
+ .bss :
+ {
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = . ;
+ } > iram0
+
+ .flashusr :
+ {
+ _usrprog_start = . ;
+ } > flashusr
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* memory ranges configuration for EDK2638 board */
+
+OUTPUT_FORMAT("coff-h8300")
+OUTPUT_ARCH(h8300s)
+
+ __flash_base = 0x000000 ;
+ __flash_size = 0x040000 ;
+ __flashbb_size = 0x002000 ;
+ __flashpb_size = 0x001000 ;
+ __ram_base = 0x040000 ;
+ __ram_end = 0x07ffff ;
+ __iram0_base = 0xffb000 ;
+ __iram0_end = 0xffcfff ;
+
+
+ __flashpb_base = __flash_base + __flashbb_size ;
+
+MEMORY
+ {
+ iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
+ flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
+ iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
+ flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
+ iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
+ flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
+ flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
+ flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
+ flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
+ ram (w) : ORIGIN = 0x040000, LENGTH = 0x040000
+ /* ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000 */
+ iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
+ bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
+ iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
+ eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
+ }
+
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "edk2638.ld-cfg"
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+PROVIDE( ___heap_end = __ram_end );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ _etext = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x10 ) ;
+ ___data_lma = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .data :
+ AT ( ADDR( .tors ) + SIZEOF( .tors ) )
+ {
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > ram /*at> flashusr*/
+
+ /* ___data_lma = LOADADDR(.data) ; */
+
+ .bss :
+ {
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > ram
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "edk2638.ld-cfg"
+
+/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+PROVIDE( ___heap_end = __ram_end );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > ram
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ } > ram
+
+ .data :
+ {
+ ___data_lma = . ;
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > ram
+
+ .bss :
+ {
+ . = ALIGN( 0x10 ) ;
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > ram
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "id_cpu1.ld-cfg"
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ *(EXCLUDE_FILE(*boot_fn.o) .text)
+ *(EXCLUDE_FILE(*boot_fn.o) .rodata)
+ *(.strings)
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .data :
+ {
+ ___data_lma = . ;
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .bss :
+ {
+ . = ALIGN( 0x4 ) ;
+ _bss_start = ALIGN( 0x4 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ; ;
+ } > bloader
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "id_cpu1.ld-cfg"
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .fvector :
+ {
+ ___flashbb_vector = . ;
+ LONG( ABSOLUTE( _start ) )
+ *(.fvector)
+ } > flashvec
+
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ *(.strings)
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > flashbb
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ ___data_lma = ALIGN( 0x4 ) ;
+ } > flashbb /*at> flashusr*/
+
+ .data :
+ AT ( ADDR( .tors ) + SIZEOF( .tors ) )
+ {
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > iram1
+
+ /* ___data_lma = LOADADDR(.data) ; */
+
+ .bss :
+ {
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = . ;
+ } > iram0
+
+ .flashusr :
+ {
+ _usrprog_start = . ;
+ } > flashusr
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* memory ranges configuration for ID_CPU1 board */
+
+OUTPUT_FORMAT("coff-h8300")
+OUTPUT_ARCH(h8300s)
+
+ __flash_base = 0x000000 ;
+ __flash_size = 0x040000 ;
+ __flashbb_size = 0x002000 ;
+ __flashpb_size = 0x001000 ;
+ __ram_base = 0x200000 ;
+ __ram_end = 0x2fffff ;
+ __iram0_base = 0xffb000 ;
+ __iram0_end = 0xffcfff ;
+
+ __flashpb_base = __flash_base + __flashbb_size ;
+
+MEMORY
+ {
+ iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
+ flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
+ iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
+ flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
+ iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
+ flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
+ flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
+ flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
+ flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
+ ram (w) : ORIGIN = 0x200000, LENGTH = 0x100000
+ ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
+ iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
+ bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
+ iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
+ eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
+ }
+
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "id_cpu1.ld-cfg"
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+PROVIDE( ___heap_end = __ram_end );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ _etext = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x10 ) ;
+ ___data_lma = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .data :
+ AT ( ADDR( .tors ) + SIZEOF( .tors ) )
+ {
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > ram /*at> flashusr*/
+
+ /* ___data_lma = LOADADDR(.data) ; */
+
+ .bss :
+ {
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > ram
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "id_cpu1.ld-cfg"
+
+/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+PROVIDE( ___heap_end = __ram_end );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > ram
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ } > ram
+
+ .data :
+ {
+ ___data_lma = . ;
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > ram
+
+ .bss :
+ {
+ . = ALIGN( 0x10 ) ;
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > ram
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "id_cpu1.ld-cfg"
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+PROVIDE( ___heap_end = __iram0_end - 0x200 );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ _etext = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x10 ) ;
+ ___data_lma = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .data :
+ AT ( ADDR( .tors ) + SIZEOF( .tors ) )
+ {
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > iram0 /*at> flashusr*/
+
+ /* ___data_lma = LOADADDR(.data) ; */
+
+ .bss :
+ {
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block */
+
+INCLUDE "id_cpu1.ld-cfg"
+
+/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+PROVIDE( ___heap_end = __iram0_end - 0x200 );
+
+/* STARTUP(crt0.o) */
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0*(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .data :
+ {
+ ___data_lma = . ;
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .bss :
+ {
+ . = ALIGN( 0x10 ) ;
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+Copy (or create simlink to) one of the files here to ../config.target
--- /dev/null
+# -*- makefile -*-
+
+ARCH=h8300
+MACH=2638
+BOARD=h8canusb
+
+CC = h8300-coff-gcc
+LINK = h8300-coff-ld
+OBJCOPY = h8300-coff-objcopy
+
+TARGET_ARCH = -ms
+
+# This selects linker script
+BOARD_LAYOUT=id_cpu1
+LINK_VARIANT=ram
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE article PUBLIC "-//OASIS//DTD DocBook XML V4.3//EN"
+"http://www.oasis-open.org/docbook/xml/4.3/docbookx.dtd">
+<article>
+ <title>H8S/2638 Software Documentation</title>
+
+ <section>
+ <title>Linking</title>
+
+ <para>Linking of an application is done depending on the linker script.
+ There are several variants of the linker script:</para>
+
+ <variablelist>
+ <varlistentry>
+ <term>bload</term>
+
+ <listitem>
+ <para></para>
+ </listitem>
+ </varlistentry>
+
+ <varlistentry>
+ <term>boot</term>
+
+ <listitem>
+ <para></para>
+ </listitem>
+ </varlistentry>
+
+ <varlistentry>
+ <term>flash</term>
+
+ <listitem>
+ <para></para>
+ </listitem>
+ </varlistentry>
+
+ <varlistentry>
+ <term>ram</term>
+
+ <listitem>
+ <para></para>
+ </listitem>
+ </varlistentry>
+ </variablelist>
+ </section>
+
+ <section>
+ <title>Booting</title>
+
+ <para></para>
+
+ <section>
+ <title>Bloader</title>
+
+ <para></para>
+ </section>
+ </section>
+
+ <section>
+ <title>Utilities</title>
+
+ <para></para>
+
+ <section>
+ <title>tohit</title>
+
+ <para></para>
+ </section>
+ </section>
+</article>
\ No newline at end of file
projects / sysless.git / commitdiff