Corrected Cortex-M3 interrupt state saving.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

diff --git a/arch/arm/generic/defines/cpu_def.h b/arch/arm/generic/defines/cpu_def.h
index 19295dfb44427b6402a805b03e72fb4b96a42754..73aacd7408dbd4f8971d5c8393768f9ce28802a6 100644 (file)
--- a/arch/arm/generic/defines/cpu_def.h
+++ b/arch/arm/generic/defines/cpu_def.h
@@ -189,7 +189,7 @@ void irq_redirect2vector(int vectno,struct pt_regs *regs);
                 unsigned long temp;                             \
                 (void) (&temp == &flags);                       \
         __asm__ __volatile__(                                   \
-        "mrs    %0, psr                 @ save_and_cli\n"       \
+        "mrs    %0, primask             @ save_and_cli\n"       \
 "       cpsid  i\n"                                             \
         : "=r" (flags)                                          \
         :                                                       \
@@ -201,7 +201,7 @@ void irq_redirect2vector(int vectno,struct pt_regs *regs);
                 unsigned long temp;                             \
                 (void) (&temp == &flags);                       \
         __asm__ __volatile__(                                   \
-        "mrs    %0, psr                 @ save_and_cli\n"       \
+        "mrs    %0, primask             @ save_flags\n"         \
         : "=r" (flags)                                          \
         :                                                       \
         : "memory", "cc");                                      \
@@ -210,7 +210,7 @@ void irq_redirect2vector(int vectno,struct pt_regs *regs);
 #define restore_flags(flags)                                    \
         ({                                                      \
         __asm__ __volatile__(                                   \
-        "msr    ipsr, %0               @ restore_flags\n"       \
+        "msr    primask, %0            @ restore_flags\n"       \
         :                                                       \
         : "r" (flags)                                           \
         : "memory", "cc");                                      \
@@ -296,9 +296,20 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
         return r&m?1:0;
 }
 
+#if defined(__thumb2__) || defined (__ARM_ARCH_6M__)
+
+/* DMB, DSB, ISB */
+
+#define __memory_barrier() \
+ __asm__ __volatile__("dmb": : : "memory")
+
+#else /* old plain ARM architecture */
+
 #define __memory_barrier() \
  __asm__ __volatile__("": : : "memory")
 
+#endif
+
 /*masked fields macros*/
 
 #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
@@ -313,15 +324,3 @@ static inline unsigned char inb(unsigned int port) {
 }
 
 #endif /* _ARM_CPU_DEF_H */
-
-
-
-
-
-
-
-
-
-
-
-