GCC and AS do not like to generate aa:8 or aaaa:16, stay with save register indirect...

darcs-hash:20050810140918-a67a6-6c939df5973639e03c225b333dc2fb19953c2f7c.gz

diff --git a/arch/h8300/generic/defines/cpu_def.h b/arch/h8300/generic/defines/cpu_def.h
index f413394a8bc0a55ac89514de956bfc3440b212d6..24ab58cb13dfe694d5db5096dff65c673fd7e177 100644 (file)
--- a/arch/h8300/generic/defines/cpu_def.h
+++ b/arch/h8300/generic/defines/cpu_def.h
@@ -17,10 +17,14 @@
 
 /* atomic access routines */
 
+/* There should be possible to generate more optimized code
+   if %0 changed to %U0 and "r" to "rn", but GCC nor assembler
+   wants to switch to aa:8 or aaaa:16 instruction version */
+
 #define __CONST_DATA_XOP_BIT(__nr,__pb,__aln) \
        case __nr: \
-          __asm__ __volatile__ ( __aln " %1,@%2 /*mybit 1*/\n" : \
-                 "=m" (*__pb) : "i" (__nr), "r" (__pb)); \
+          __asm__ __volatile__ ( __aln " %1,%0 /*mybit 1*/\n" : \
+                 "+m" (*__pb) : "i" (__nr), "r" (__pb)); \
          break;
 
 #define __xop_bit(nr,v,__aln) \
@@ -41,8 +45,8 @@
               __CONST_DATA_XOP_BIT(7,__pb,__aln); \
             } \
           else \
-            __asm__ __volatile__ ( __aln " %w1,@%2 /*mybit 2*/\n" : \
-                 "=m" (*__pb) : "r" (__nr), "r" (__pb)); \
+            __asm__ __volatile__ ( __aln " %w1,%0 /*mybit 2*/\n" : \
+                 "+m" (*__pb) : "r" (__nr), "r" (__pb)); \
           })
 
 #define set_bit(nr,v) (__xop_bit((nr),(v),"bset"))