--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
+# DO NOT DELETE
--- /dev/null
+SUBDIRS = defines libs
--- /dev/null
+/**************************************************************************//**
+ * @file LPC13xx.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * for the NXP LPC13xx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC13xx_H__
+#define __LPC13xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+// Keyval
+#define KVPB_CHUNK_SIZE 16
+
+///////////////////////////////////////////////////////////////////////////////
+// ISP_RAM2FLASH_BLOCK_SIZE for 17xx CPU
+#ifndef ISP_RAM2FLASH_BLOCK_SIZE
+ #define ISP_RAM2FLASH_BLOCK_SIZE 256
+#endif /* ISP_RAM2FLASH_BLOCK_SIZE */
+
+
+/** @addtogroup LPC13xx_Definitions LPC13xx Definitions
+ This file defines all structures and symbols for LPC13xx:
+ - Registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup LPC13xx_CMSIS LPC13xx CMSIS Definitions
+ Configuration of the Cortex-M3 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC13xx Specific Interrupt Numbers *******************************************************/
+ WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
+ WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */
+ WAKEUP2_IRQn = 2,
+ WAKEUP3_IRQn = 3,
+ WAKEUP4_IRQn = 4,
+ WAKEUP5_IRQn = 5,
+ WAKEUP6_IRQn = 6,
+ WAKEUP7_IRQn = 7,
+ WAKEUP8_IRQn = 8,
+ WAKEUP9_IRQn = 9,
+ WAKEUP10_IRQn = 10,
+ WAKEUP11_IRQn = 11,
+ WAKEUP12_IRQn = 12,
+ WAKEUP13_IRQn = 13,
+ WAKEUP14_IRQn = 14,
+ WAKEUP15_IRQn = 15,
+ WAKEUP16_IRQn = 16,
+ WAKEUP17_IRQn = 17,
+ WAKEUP18_IRQn = 18,
+ WAKEUP19_IRQn = 19,
+ WAKEUP20_IRQn = 20,
+ WAKEUP21_IRQn = 21,
+ WAKEUP22_IRQn = 22,
+ WAKEUP23_IRQn = 23,
+ WAKEUP24_IRQn = 24,
+ WAKEUP25_IRQn = 25,
+ WAKEUP26_IRQn = 26,
+ WAKEUP27_IRQn = 27,
+ WAKEUP28_IRQn = 28,
+ WAKEUP29_IRQn = 29,
+ WAKEUP30_IRQn = 30,
+ WAKEUP31_IRQn = 31,
+ WAKEUP32_IRQn = 32,
+ WAKEUP33_IRQn = 33,
+ WAKEUP34_IRQn = 34,
+ WAKEUP35_IRQn = 35,
+ WAKEUP36_IRQn = 36,
+ WAKEUP37_IRQn = 37,
+ WAKEUP38_IRQn = 38,
+ WAKEUP39_IRQn = 39,
+ I2C_IRQn = 40, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */
+ SSP_IRQn = 45, /*!< SSP Interrupt */
+ UART_IRQn = 46, /*!< UART Interrupt */
+ USB_IRQn = 47, /*!< USB Regular Interrupt */
+ USB_FIQn = 48, /*!< USB Fast Interrupt */
+ ADC_IRQn = 49, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 50, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */
+ EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */
+ EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */
+ EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */
+ EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */
+} IRQn_Type;
+
+
+//definition for CLK enabling masks
+#define SAHBCCTRL_SYS (1<<0)
+#define SAHBCCTRL_ROM (1<<1)
+#define SAHBCCTRL_RAM (1<<2)
+#define SAHBCCTRL_FLASHREG (1<<3)
+#define SAHBCCTRL_FLASHARR (1<<4)
+#define SAHBCCTRL_I2C (1<<5)
+#define SAHBCCTRL_GPIO (1<<6)
+#define SAHBCCTRL_CT16B0 (1<<7)
+#define SAHBCCTRL_CT16B1 (1<<8)
+#define SAHBCCTRL_CT32B0 (1<<9)
+#define SAHBCCTRL_CT32B1 (1<<10)
+#define SAHBCCTRL_SSP (1<<11)
+#define SAHBCCTRL_UART (1<<12)
+#define SAHBCCTRL_ADC (1<<13)
+#define SAHBCCTRL_USBREG (1<<14)
+#define SAHBCCTRL_WDT (1<<15)
+#define SAHBCCTRL_IOCON (1<<16)
+
+
+#define PDRUNCFG_IRCOUT_PD (1<<0)
+#define PDRUNCFG_IRC_PD (1<<1)
+#define PDRUNCFG_FLASH_PD (1<<2)
+#define PDRUNCFG_BOD_PD (1<<3)
+#define PDRUNCFG_ADC_PD (1<<4)
+#define PDRUNCFG_SYSOSC_PD (1<<5)
+#define PDRUNCFG_WDTOSC_PD (1<<6)
+#define PDRUNCFG_SYSPLL_PD (1<<7)
+#define PDRUNCFG_USBPLL_PD (1<<8)
+#define PDRUNCFG_USBPAD_PD (1<<10)
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*@}*/ /* end of group LPC13xx_CMSIS */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+//#include "system_LPC13xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC13xx_SYSCON LPC13xx System Control Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 (R/W) System memory remap Register */
+ __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 (R/W) Peripheral reset control Register */
+ __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 (R/W) System PLL control Register */
+ __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C (R/ ) System PLL status Register */
+ __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */
+ __IO uint32_t USBPLLSTAT;
+ uint32_t RESERVED0[2];
+
+ __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 (R/W) System oscillator control Register */
+ __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 (R/W) Watchdog oscillator control Register */
+ __IO uint32_t IRCCTRL; /*!< Offset: 0x028 (R/W) IRC control Register */
+ uint32_t RESERVED1[1];
+ __I uint32_t SYSRESSTAT; /*!< Offset: 0x030 (R/ ) System reset status Register */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 (R/W) System PLL clock source select Register */
+ __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 (R/W) System PLL clock source update enable Register */
+ __IO uint32_t USBPLLCLKSEL;
+ __IO uint32_t USBPLLCLKUEN;
+ uint32_t RESERVED3[8];
+
+ __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 (R/W) Main clock source select Register */
+ __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 (R/W) Main clock source update enable Register */
+ __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 (R/W) System AHB clock divider Register */
+ uint32_t RESERVED4[1];
+
+ __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 (R/W) System AHB clock control Register */
+ uint32_t RESERVED5[4];
+ __IO uint32_t SSPCLKDIV;
+ __IO uint32_t UARTCLKDIV;
+ uint32_t RESERVED6[4];
+ __IO uint32_t TRACECLKDIV;
+
+ __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */
+ uint32_t RESERVED7[3];
+
+ __IO uint32_t USBCLKSEL; /* Offset 0xC0 */
+ __IO uint32_t USBCLKUEN;
+ __IO uint32_t USBCLKDIV;
+ uint32_t RESERVED8[1];
+ __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 (R/W) WDT clock source select Register */
+ __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 (R/W) WDT clock source update enable Register */
+ __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 (R/W) WDT clock divider Register */
+ uint32_t RESERVED9[1];
+
+ __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 (R/W) CLKOUT clock source select Register */
+ __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 (R/W) CLKOUT clock source update enable Register */
+ __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 (R/W) CLKOUT clock divider Register */
+ uint32_t RESERVED10[5];
+
+ __I uint32_t PIOPORCAP0; /*!< Offset: 0x100 (R/ ) POR captured PIO status 0 Register */
+ __I uint32_t PIOPORCAP1; /*!< Offset: 0x104 (R/ ) POR captured PIO status 1 Register */
+ uint32_t RESERVED11[11];
+ uint32_t RESERVED12[7];
+ __IO uint32_t BODCTRL; /*!< Offset: 0x150 (R/W) BOD control Register */
+ uint32_t RESERVED13[1];
+ __IO uint32_t SYSTCKCAL; /*!< Offset: 0x158 (R/W) System tick counter calibration Register */
+ uint32_t RESERVED14[41];
+
+ __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 (R/W) Start logic edge control Register 0 */
+ __IO uint32_t STARTERP0; /*!< Offset: 0x204 (R/W) Start logic signal enable Register 0 */
+ __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 ( /W) Start logic reset Register 0 */
+ __I uint32_t STARTSRP0; /*!< Offset: 0x20C (R/ ) Start logic status Register 0 */
+ __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 (R/W) Start logic edge control Register 1 (LPC11UXX only) */
+ __IO uint32_t STARTERP1; /*!< Offset: 0x214 (R/W) Start logic signal enable Register 1 (LPC11UXX only) */
+ __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 ( /W) Start logic reset Register 1 (LPC11UXX only) */
+ __I uint32_t STARTSRP1; /*!< Offset: 0x21C (R/ ) Start logic status Register 1 (LPC11UXX only) */
+ uint32_t RESERVED17[4];
+
+ __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 (R/W) Power-down states in Deep-sleep mode Register */
+ __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 (R/W) Power-down states after wake-up from Deep-sleep mode Register*/
+ __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 (R/W) Power-down configuration Register*/
+ uint32_t RESERVED18[110];
+ __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 (R/ ) Device ID Register */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC13xx_SYSCON */
+
+
+/*------------- Pin Connect Block (IOCON) --------------------------------*/
+/** @addtogroup LPC13xx_IOCON LPC13xx I/O Configuration Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PIO2_6; /*!< Offset: 0x000 (R/W) I/O configuration for pin PIO2_6 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t PIO2_0; /*!< Offset: 0x008 (R/W) I/O configuration for pin PIO2_0/DTR/SSEL1 */
+ __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C (R/W) I/O configuration for pin RESET/PIO0_0 */
+ __IO uint32_t PIO0_1; /*!< Offset: 0x010 (R/W) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 */
+ __IO uint32_t PIO1_8; /*!< Offset: 0x014 (R/W) I/O configuration for pin PIO1_8/CT16B1_CAP0 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t PIO0_2; /*!< Offset: 0x01C (R/W) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+
+ __IO uint32_t PIO2_7; /*!< Offset: 0x020 (R/W) I/O configuration for pin PIO2_7 */
+ __IO uint32_t PIO2_8; /*!< Offset: 0x024 (R/W) I/O configuration for pin PIO2_8 */
+ __IO uint32_t PIO2_1; /*!< Offset: 0x028 (R/W) I/O configuration for pin PIO2_1/nDSR/SCK1 */
+ __IO uint32_t PIO0_3; /*!< Offset: 0x02C (R/W) I/O configuration for pin PIO0_3 */
+ __IO uint32_t PIO0_4; /*!< Offset: 0x030 (R/W) I/O configuration for pin PIO0_4/SCL */
+ __IO uint32_t PIO0_5; /*!< Offset: 0x034 (R/W) I/O configuration for pin PIO0_5/SDA */
+ __IO uint32_t PIO1_9; /*!< Offset: 0x038 (R/W) I/O configuration for pin PIO1_9/CT16B1_MAT0 */
+ __IO uint32_t PIO3_4; /*!< Offset: 0x03C (R/W) I/O configuration for pin PIO3_4 */
+
+ __IO uint32_t PIO2_4; /*!< Offset: 0x040 (R/W) I/O configuration for pin PIO2_4 */
+ __IO uint32_t PIO2_5; /*!< Offset: 0x044 (R/W) I/O configuration for pin PIO2_5 */
+ __IO uint32_t PIO3_5; /*!< Offset: 0x048 (R/W) I/O configuration for pin PIO3_5 */
+ __IO uint32_t PIO0_6; /*!< Offset: 0x04C (R/W) I/O configuration for pin PIO0_6/SCK0 */
+ __IO uint32_t PIO0_7; /*!< Offset: 0x050 (R/W) I/O configuration for pin PIO0_7/nCTS */
+ __IO uint32_t PIO2_9; /*!< Offset: 0x054 (R/W) I/O configuration for pin PIO2_9 */
+ __IO uint32_t PIO2_10; /*!< Offset: 0x058 (R/W) I/O configuration for pin PIO2_10 */
+ __IO uint32_t PIO2_2; /*!< Offset: 0x05C (R/W) I/O configuration for pin PIO2_2/DCD/MISO1 */
+
+ __IO uint32_t PIO0_8; /*!< Offset: 0x060 (R/W) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
+ __IO uint32_t PIO0_9; /*!< Offset: 0x064 (R/W) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
+ __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 (R/W) I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 */
+ __IO uint32_t PIO1_10; /*!< Offset: 0x06C (R/W) I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 */
+ __IO uint32_t PIO2_11; /*!< Offset: 0x070 (R/W) I/O configuration for pin PIO2_11/SCK0 */
+ __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 (R/W) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+ __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 (R/W) I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 */
+ __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C (R/W) I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 */
+
+ __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 (R/W) I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 */
+ __IO uint32_t PIO3_0; /*!< Offset: 0x084 (R/W) I/O configuration for pin PIO3_0/nDTR */
+ __IO uint32_t PIO3_1; /*!< Offset: 0x088 (R/W) I/O configuration for pin PIO3_1/nDSR */
+ __IO uint32_t PIO2_3; /*!< Offset: 0x08C (R/W) I/O configuration for pin PIO2_3/RI/MOSI1 */
+ __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 (R/W) I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 */
+ __IO uint32_t PIO1_4; /*!< Offset: 0x094 (R/W) I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 */
+ __IO uint32_t PIO1_11; /*!< Offset: 0x098 (R/W) I/O configuration for pin PIO1_11/AD7 */
+ __IO uint32_t PIO3_2; /*!< Offset: 0x09C (R/W) I/O configuration for pin PIO3_2/nDCD */
+
+ __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 (R/W) I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 */
+ __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 (R/W) I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 */
+ __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 (R/W) I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 */
+ __IO uint32_t PIO3_3; /*!< Offset: 0x0AC (R/W) I/O configuration for pin PIO3_3/nRI */
+ __IO uint32_t SCKLOC; /*!< Offset: 0x0B0 (R/W) SCK pin location select Register */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC13xx_IOCON */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC13xx_PMU LPC13xx Power Management Unit
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PCON; /*!< Offset: 0x000 (R/W) Power control Register */
+ __IO uint32_t GPREG0; /*!< Offset: 0x004 (R/W) General purpose Register 0 */
+ __IO uint32_t GPREG1; /*!< Offset: 0x008 (R/W) General purpose Register 1 */
+ __IO uint32_t GPREG2; /*!< Offset: 0x00C (R/W) General purpose Register 2 */
+ __IO uint32_t GPREG3; /*!< Offset: 0x010 (R/W) General purpose Register 3 */
+ __IO uint32_t GPREG4; /*!< Offset: 0x014 (R/W) General purpose Register 4 */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC13xx_PMU */
+
+
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+/** @addtogroup LPC13xx_GPIO LPC13xx General Purpose Input/Output
+ @{
+*/
+#if 0
+typedef struct
+{
+ union {
+ __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 (R/W) Port data Register for pins PIOn_0 to PIOn_11 */
+ struct {
+ uint32_t RESERVED0[4095];
+ __IO uint32_t DATA; /*!< Offset: 0x3FFC (R/W) Port data Register */
+ };
+ };
+ uint32_t RESERVED1[4096];
+ __IO uint32_t DIR; /*!< Offset: 0x8000 (R/W) Data direction Register */
+ __IO uint32_t IS; /*!< Offset: 0x8004 (R/W) Interrupt sense Register */
+ __IO uint32_t IBE; /*!< Offset: 0x8008 (R/W) Interrupt both edges Register */
+ __IO uint32_t IEV; /*!< Offset: 0x800C (R/W) Interrupt event Register */
+ __IO uint32_t IE; /*!< Offset: 0x8010 (R/W) Interrupt mask Register */
+ __I uint32_t RIS; /*!< Offset: 0x8014 (R/ ) Raw interrupt status Register */
+ __I uint32_t MIS; /*!< Offset: 0x8018 (R/ ) Masked interrupt status Register */
+ __O uint32_t IC; /*!< Offset: 0x801C ( /W) Interrupt clear Register */
+} LPC_GPIO_TypeDef;
+#else
+//predchozi union v GCC nechodi
+#define GPIO_FULL_MASK 4095
+typedef struct
+{
+ __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 (R/W) Port data Register for pins PIOn_0 to PIOn_11 */
+ uint32_t RESERVED1[4096];
+ __IO uint32_t DIR; /*!< Offset: 0x8000 (R/W) Data direction Register */
+ __IO uint32_t IS; /*!< Offset: 0x8004 (R/W) Interrupt sense Register */
+ __IO uint32_t IBE; /*!< Offset: 0x8008 (R/W) Interrupt both edges Register */
+ __IO uint32_t IEV; /*!< Offset: 0x800C (R/W) Interrupt event Register */
+ __IO uint32_t IE; /*!< Offset: 0x8010 (R/W) Interrupt mask Register */
+ __I uint32_t RIS; /*!< Offset: 0x8014 (R/ ) Raw interrupt status Register */
+ __I uint32_t MIS; /*!< Offset: 0x8018 (R/ ) Masked interrupt status Register */
+ __O uint32_t IC; /*!< Offset: 0x801C ( /W) Interrupt clear Register */
+} LPC_GPIO_TypeDef;
+#endif
+
+/*@}*/ /* end of group LPC13xx_GPIO */
+
+
+/*------------- Timer (TMR) --------------------------------------------------*/
+/** @addtogroup LPC13xx_TMR LPC13xx 16/32-bit Counter/Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */
+ __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */
+ __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */
+ __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */
+ __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */
+ __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */
+ __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */
+ __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */
+ __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */
+ __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */
+ __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */
+ __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */
+ uint32_t RESERVED1[3];
+ __IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */
+ uint32_t RESERVED2[12];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */
+ __IO uint32_t PWMC; /*!< Offset: 0x074 (R/W) PWM Control Register */
+} LPC_TMR_TypeDef;
+/*@}*/ /* end of group LPC13xx_TMR */
+
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @addtogroup LPC13xx_UART LPC13xx Universal Asynchronous Receiver/Transmitter
+ @{
+*/
+typedef struct
+{
+ union {
+ __I uint32_t RBR; /*!< Offset: 0x000 (R/ ) Receiver Buffer Register */
+ __O uint32_t THR; /*!< Offset: 0x000 ( /W) Transmit Holding Register */
+ __IO uint32_t DLL; /*!< Offset: 0x000 (R/W) Divisor Latch LSB */
+ };
+ union {
+ __IO uint32_t DLM; /*!< Offset: 0x004 (R/W) Divisor Latch MSB */
+ __IO uint32_t IER; /*!< Offset: 0x000 (R/W) Interrupt Enable Register */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 (R/ ) Interrupt ID Register */
+ __O uint32_t FCR; /*!< Offset: 0x008 ( /W) FIFO Control Register */
+ };
+ __IO uint32_t LCR; /*!< Offset: 0x00C (R/W) Line Control Register */
+ __IO uint32_t MCR; /*!< Offset: 0x010 (R/W) Modem control Register */
+ __I uint32_t LSR; /*!< Offset: 0x014 (R/ ) Line Status Register */
+ __I uint32_t MSR; /*!< Offset: 0x018 (R/ ) Modem status Register */
+ __IO uint32_t SCR; /*!< Offset: 0x01C (R/W) Scratch Pad Register */
+ __IO uint32_t ACR; /*!< Offset: 0x020 (R/W) Auto-baud Control Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t FDR; /*!< Offset: 0x028 (R/W) Fractional Divider Register */
+ uint32_t RESERVED1[1];
+ __IO uint32_t TER; /*!< Offset: 0x030 (R/W) Transmit Enable Register */
+ uint32_t RESERVED2[6];
+ __IO uint32_t RS485CTRL; /*!< Offset: 0x04C (R/W) RS-485/EIA-485 Control Register */
+ __IO uint32_t ADRMATCH; /*!< Offset: 0x050 (R/W) RS-485/EIA-485 address match Register */
+ __IO uint32_t RS485DLY; /*!< Offset: 0x054 (R/W) RS-485/EIA-485 direction control delay Register */
+
+} LPC_UART_TypeDef;
+/*@}*/ /* end of group LPC13xx_UART */
+
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+/** @addtogroup LPC13xx_SSP LPC13xx Synchronous Serial Port
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR0; /*!< Offset: 0x000 (R/W) Control Register 0 */
+ __IO uint32_t CR1; /*!< Offset: 0x004 (R/W) Control Register 1 */
+ __IO uint32_t DR; /*!< Offset: 0x008 (R/W) Data Register */
+ __I uint32_t SR; /*!< Offset: 0x00C (R/ ) Status Register */
+ __IO uint32_t CPSR; /*!< Offset: 0x010 (R/W) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< Offset: 0x018 (R/ ) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< Offset: 0x01C (R/ ) Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< Offset: 0x020 ( /W) SSPICR Interrupt Clear Register */
+} LPC_SSP_TypeDef;
+/*@}*/ /* end of group LPC13xx_SSP */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC13xx_I2C LPC13xx I2C-Bus Interface
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CONSET; /*!< Offset: 0x000 (R/W) I2C Control Set Register */
+ __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) I2C Status Register */
+ __IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C Data Register */
+ __IO uint32_t ADR0; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */
+ __IO uint32_t SCLH; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */
+ __IO uint32_t SCLL; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */
+ __O uint32_t CONCLR; /*!< Offset: 0x018 ( /W) I2C Control Clear Register */
+ __IO uint32_t MMCTRL; /*!< Offset: 0x01C (R/W) Monitor mode control register */
+ __IO uint32_t ADR1; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */
+ __IO uint32_t ADR2; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */
+ __IO uint32_t ADR3; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */
+ __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C (R/ ) Data buffer Register */
+ __IO uint32_t MASK0; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */
+ __IO uint32_t MASK2; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */
+ __IO uint32_t MASK3; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */
+} LPC_I2C_TypeDef;
+/*@}*/ /* end of group LPC13xx_I2C */
+
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+/** @addtogroup LPC13xx_WDT LPC13xx WatchDog Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) Watchdog mode Register */
+ __IO uint32_t TC; /*!< Offset: 0x004 (R/W) Watchdog timer constant Register */
+ __O uint32_t FEED; /*!< Offset: 0x008 ( /W) Watchdog feed sequence Register */
+ __I uint32_t TV; /*!< Offset: 0x00C (R/ ) Watchdog timer value Register */
+} LPC_WDT_TypeDef;
+/*@}*/ /* end of group LPC13xx_WDT */
+
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+/** @addtogroup LPC13xx_ADC LPC13xx Analog-to-Digital Converter
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR; /*!< Offset: 0x000 (R/W) A/D Control Register */
+ __IO uint32_t GDR; /*!< Offset: 0x004 (R/W) A/D Global Data Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t INTEN; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */
+ __IO uint32_t DR[8]; /*!< Offset: 0x010 (R/W) A/D Channel 0..7 Data Register */
+ __I uint32_t STAT; /*!< Offset: 0x030 (R/ ) A/D Status Register */
+} LPC_ADC_TypeDef;
+/*@}*/ /* end of group LPC13xx_ADC */
+
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+/** @addtogroup LPC13xx_USB LPC13xx Universal Serial Bus
+ @{
+*/
+typedef struct
+{
+ __I uint32_t DevIntSt; /*!< Offset: 0x000 (R/ ) USB Device Interrupt Status Register */
+ __IO uint32_t DevIntEn; /*!< Offset: 0x004 (R/W) USB Device Interrupt Enable Register */
+ __O uint32_t DevIntClr; /*!< Offset: 0x008 ( /W) USB Device Interrupt Clear Register */
+ __O uint32_t DevIntSet; /*!< Offset: 0x00C ( /W) USB Device Interrupt Set Register */
+
+ __O uint32_t CmdCode; /*!< Offset: 0x010 ( /W) USB Command Code Register */
+ __I uint32_t CmdData; /*!< Offset: 0x014 (R/ ) USB Command Data Register */
+
+ __I uint32_t RxData; /*!< Offset: 0x018 (R/ ) USB Receive Data Register */
+ __O uint32_t TxData; /*!< Offset: 0x01C ( /W) USB Transmit Data Register */
+ __I uint32_t RxPLen; /*!< Offset: 0x020 (R/ ) USB Receive Packet Length Register */
+ __O uint32_t TxPLen; /*!< Offset: 0x024 ( /W) USB Transmit Packet Length Register */
+ __IO uint32_t Ctrl; /*!< Offset: 0x028 (R/ ) USB Control Register */
+ __O uint32_t DevFIQSel; /*!< Offset: 0x02C ( /W) USB Device FIQ select Register */
+} LPC_USB_TypeDef;
+/*@}*/ /* end of group LPC13xx_USB */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
+#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
+
+/* AHB peripherals */
+#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
+#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
+#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
+#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
+#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
+#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
+#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
+#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC13xx_H__ */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+include_HEADERS = core_cm3.h LPC13xx.h
--- /dev/null
+../../mach-lpc17xx/defines/core_cm3.h
\ No newline at end of file
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
+# DO NOT DELETE
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = hal iap
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+lib_LIBRARIES = mach_hal
+
+include_HEADERS = hal_machperiph.h
+
+mach_hal_SOURCES = hal.c startup.c hal_machperiph.c
+
+
+
+
+
--- /dev/null
+#include <stdio.h>
+#include <cpu_def.h>
+#include <LPC13xx.h>
+
+#define IRQ_TABLE_SIZE (16+55)
+
+__attribute__ ((section(".irqarea")))
+irq_handler_t *irq_handler_table_start[IRQ_TABLE_SIZE];
+void *irq_context_table_start[IRQ_TABLE_SIZE];
+
+void **irq_context_table = irq_context_table_start;
+irq_handler_t **irq_handler_table = irq_handler_table_start;
+unsigned int irq_table_size = IRQ_TABLE_SIZE;
+
+void disable_irq(unsigned int irqnum)
+{
+ NVIC_DisableIRQ(irqnum);
+}
+void enable_irq(unsigned int irqnum)
+{
+ NVIC_EnableIRQ(irqnum);
+}
+
+int
+request_irq(unsigned int irqnum, irq_handler_t *handler, unsigned long flags,
+ const char *name, void *context)
+{
+ unsigned int irqidx=irq_irqnum2irqidx(irqnum);
+
+ if (irqidx>=irq_table_size)
+ return -1;
+
+ disable_irq(irqnum);
+ irq_handler_table[irqidx]=handler;
+ irq_context_table[irqidx]=context;
+ enable_irq(irqnum);
+
+ return 0;
+}
+
+void free_irq(unsigned int irqnum, void *context)
+{
+ unsigned int irqidx=irq_irqnum2irqidx(irqnum);
+
+ if (irqidx>=irq_table_size)
+ return;
+
+ disable_irq(irqnum);
+ irq_handler_table[irqidx]=NULL;
+ irq_context_table[irqidx]=NULL;
+}
\ No newline at end of file
--- /dev/null
+#include <system_def.h>
+#include <cpu_def.h>
+#include <hal_machperiph.h>
+
+//#include <stdint.h>
+#include "LPC13xx.h"
+
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+ #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
+ #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((USBPLLUEN_Val), ~0x00000001))
+ #error "USBPLLUEN: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF))
+ #error "AHBCLKCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003))
+ #error "SYSMEMREMAP: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+unsigned int system_frequency = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock) */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void system_core_clock_update (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 400000; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ system_frequency = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ system_frequency = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ system_frequency = __SYS_OSC_CLK;
+ break;
+ case 2: /* WDT Oscillator */
+ system_frequency = wdt_osc;
+ break;
+ case 3: /* Reserved */
+ system_frequency = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ system_frequency = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ system_frequency = __IRC_OSC_CLK;
+ } else {
+ system_frequency = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 1: /* System oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ system_frequency = __SYS_OSC_CLK;
+ } else {
+ system_frequency = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ system_frequency = wdt_osc;
+ } else {
+ system_frequency = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 3: /* Reserved */
+ system_frequency = 0;
+ break;
+ }
+ break;
+ }
+
+ system_frequency /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+void system_clock_init(void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+#if (SYSCLK_SETUP) /* System Clock Setup */
+
+#if (SYSOSC_SETUP) /* System Oscillator Setup */
+ uint32_t i;
+
+ LPC_SYSCON->PDRUNCFG &= ~PDRUNCFG_SYSOSC_PD; /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif /* SYSOSC_SETUP */
+
+#if (SYSPLL_SETUP) /* System PLL Setup */
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~PDRUNCFG_SYSPLL_PD; /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#else
+ LPC_SYSCON->PDRUNCFG |= PDRUNCFG_SYSPLL_PD; /* if PLL is not used, power-down PLL */
+#endif /* SYSPLL_SETUP */
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+#endif /* SYSCLK_SETUP */
+
+#if (USBCLK_SETUP) /* USB Clock Setup */
+ LPC_SYSCON->PDRUNCFG &= ~PDRUNCFG_USBPAD_PD; /* Power-up USB PHY */
+
+ #if (USBPLL_SETUP) /* USB PLL Setup */
+ LPC_SYSCON->PDRUNCFG &= ~PDRUNCFG_USBPLL_PD; /* Power-up USB PLL */
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+ LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
+#else /* USBPLL_SETUP */
+ LPC_SYSCON->USBCLKSEL = 0x01; /* Select Main Clock */
+#endif /* USBPLL_SETUP */
+
+#else /* USBCLK_SETUP */
+ LPC_SYSCON->PDRUNCFG |= PDRUNCFG_USBPAD_PD; /* Power-down USB PHY */
+ LPC_SYSCON->PDRUNCFG |= PDRUNCFG_USBPLL_PD; /* Power-down USB PLL */
+#endif /* USBCLK_SETUP */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif /* CLOCK_SETUP */
+
+ LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
+ LPC_SYSCON->PDRUNCFG |= PDRUNCFG_WDTOSC_PD; /* Power down WDT, if it will be used, it should be enabled egain*/
+}
+
+//TODO: check WDT settings
+void lpc_watchdog_feed()
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ LPC_WDT->FEED = 0xAA;
+ LPC_WDT->FEED = 0x55;
+ restore_flags(flags);
+}
+
+void lpc_watchdog_init(int on,int timeout_ms)
+{
+ if (!on) return;
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->WDTCLKDIV = 1; //preddelic musi byt >0 (0 je disable, 1= deleni 1 atd.)
+ LPC_SYSCON->PDRUNCFG &= ~PDRUNCFG_WDTOSC_PD; // Power-up WDT Clock (kdyby byl nahodou vyputy, vychozi je ale zapnuto)
+ LPC_SYSCON->SYSAHBCLKCTRL |= SAHBCCTRL_WDT; // je nutne povolit hodiny WDT v SYSAHBCLKCTRL
+
+ LPC_SYSCON->WDTCLKSEL = 2; //zdroj hodin bude WDT oscilator
+ LPC_SYSCON->WDTCLKUEN = 1;
+ LPC_SYSCON->WDTCLKUEN = 0;
+ LPC_SYSCON->WDTCLKUEN = 1;
+ while(!(LPC_SYSCON->WDTCLKUEN & 1));//prechozi 4 radky jsou nutne, aby se zmenil zdroj hodin
+ LPC_WDT->TC = (((__WDT_OSC_CLK) / 1000) * (timeout_ms / 4));
+ //LPC_WDT->TC = 1000;//(__WDT_OSC_CLK/4)*(1000/timeout_ms);
+ LPC_WDT->MOD = 0x03; /* Enable watchdog timer and reset */
+}
+
+void power_down_unused_periph(void)
+{
+ if ((LPC_SYSCON->MAINCLKSEL > 0) && (LPC_SYSCON->WDTCLKSEL > 0) && ((LPC_SYSCON->SYSPLLCLKSEL > 0) || (LPC_SYSCON->PDAWAKECFG & PDRUNCFG_SYSPLL_PD)))
+ LPC_SYSCON->PDRUNCFG |= PDRUNCFG_IRCOUT_PD | PDRUNCFG_IRC_PD; /* if IRC is not used, power-down IRC */
+
+ //vypnu nepotrebne periferie, pokud je budu potrebovat, zapnou se v initu dane periferie
+ LPC_SYSCON->PDRUNCFG |= PDRUNCFG_ADC_PD; /* power-down ADC */
+}
--- /dev/null
+#ifndef _HAL_MACHPERIPH_H
+#define _HAL_MACHPERIPH_H
+
+#include <system_def.h>
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+
+#define WDTOSCCTRL_Val 0x000000A0 //frekvence WDT oscilatoru 1,6MHz, delicka 2, vysledna frekvence 0.8MHz
+
+#ifndef __SYS_OSC_CLK
+ #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#endif
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#ifdef WATCHDOG_ENABLED /* Watchdog Oscillator Setup*/
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 400000 / __DIVSEL)
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+#else
+ #define __WDT_OSC_CLK (1600000 / 2)
+#endif // WATCHDOG_ENABLED
+
+
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (SYSCLK_SETUP) /* System Clock Setup */
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 2)
+ #define __SYS_PLLCLKIN (__WDT_OSC_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #if (SYSPLL_SETUP) /* System PLL Setup */
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+ #else
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1))
+ #endif // SYSPLL_SETUP
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+ #else // SYSCLK_SETUP
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #if (SYSAHBCLKDIV_Val == 0)
+ #define __SYSTEM_CLOCK (0)
+ #else
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+ #endif
+ #endif // SYSCLK_SETUP
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+extern unsigned int system_frequency; //Tahle promenna ma smysl,jen pokud by se za chodu menilo nastaveni hodin a bylo by treba upravit aktualni hodnotu.
+ //Jinak plati CCLK
+#define CCLK __SYSTEM_CLOCK
+#define PCLK CCLK /* na LPC13xx se hodiny pousti do periferii primo povolenim prislusnych bitu v SYSAHBCLKCTRL */
+#define PCLK2 __MAIN_CLOCK /* UART, SPI atd. ma zdroj hodin pred delickou SYSAHBCLKDIV */
+
+void system_clock_init(void);
+void system_core_clock_update (void);
+void power_down_unused_periph(void);
+
+void lpc_watchdog_init(int on,int timeout_ms);
+void lpc_watchdog_feed();
+
+#endif /* _HAL_MACHPERIPH_H */
+
--- /dev/null
+/****************************************************************************//**
+ * @file : startup_LPC17xx.c
+ * @brief : CMSIS Cortex-M3 Core Device Startup File
+ * @version : V1.01
+ * @date : 4. Feb. 2009
+ *
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+// Mod by nio for the .fastcode part
+
+#include "LPC13xx.h"
+
+#define WEAK __attribute__ ((weak))
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+/* System exception vector handler */
+void WEAK Reset_Handler(void); /* Reset Handler */
+void WEAK NMI_Handler(void); /* NMI Handler */
+void WEAK HardFault_Handler(void); /* Hard Fault Handler */
+void WEAK MemManage_Handler(void); /* MPU Fault Handler */
+void WEAK BusFault_Handler(void); /* Bus Fault Handler */
+void WEAK UsageFault_Handler(void); /* Usage Fault Handler */
+void WEAK SVC_Handler(void); /* SVCall Handler */
+void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */
+void WEAK PendSV_Handler(void); /* PendSV Handler */
+void WEAK SysTick_Handler(void); /* SysTick Handler */
+
+
+void WEAK WAKEUP0_IRQHandler(void);
+void WEAK WAKEUP1_IRQHandler(void);
+void WEAK WAKEUP2_IRQHandler(void);
+void WEAK WAKEUP3_IRQHandler(void);
+void WEAK WAKEUP4_IRQHandler(void);
+void WEAK WAKEUP5_IRQHandler(void);
+void WEAK WAKEUP6_IRQHandler(void);
+void WEAK WAKEUP7_IRQHandler(void);
+void WEAK WAKEUP8_IRQHandler(void);
+void WEAK WAKEUP9_IRQHandler(void);
+void WEAK WAKEUP10_IRQHandler(void);
+void WEAK WAKEUP11_IRQHandler(void);
+void WEAK WAKEUP12_IRQHandler(void);
+void WEAK WAKEUP13_IRQHandler(void);
+void WEAK WAKEUP14_IRQHandler(void);
+void WEAK WAKEUP15_IRQHandler(void);
+void WEAK WAKEUP16_IRQHandler(void);
+void WEAK WAKEUP17_IRQHandler(void);
+void WEAK WAKEUP18_IRQHandler(void);
+void WEAK WAKEUP19_IRQHandler(void);
+void WEAK WAKEUP20_IRQHandler(void);
+void WEAK WAKEUP21_IRQHandler(void);
+void WEAK WAKEUP22_IRQHandler(void);
+void WEAK WAKEUP23_IRQHandler(void);
+void WEAK WAKEUP24_IRQHandler(void);
+void WEAK WAKEUP25_IRQHandler(void);
+void WEAK WAKEUP26_IRQHandler(void);
+void WEAK WAKEUP27_IRQHandler(void);
+void WEAK WAKEUP28_IRQHandler(void);
+void WEAK WAKEUP29_IRQHandler(void);
+void WEAK WAKEUP30_IRQHandler(void);
+void WEAK WAKEUP31_IRQHandler(void);
+void WEAK WAKEUP32_IRQHandler(void);
+void WEAK WAKEUP33_IRQHandler(void);
+void WEAK WAKEUP34_IRQHandler(void);
+void WEAK WAKEUP35_IRQHandler(void);
+void WEAK WAKEUP36_IRQHandler(void);
+void WEAK WAKEUP37_IRQHandler(void);
+void WEAK WAKEUP38_IRQHandler(void);
+void WEAK WAKEUP39_IRQHandler(void);
+void WEAK I2C_IRQHandler(void);
+void WEAK TIMER_16_0_IRQHandler(void);
+void WEAK TIMER_16_1_IRQHandler(void);
+void WEAK TIMER_32_0_IRQHandler(void);
+void WEAK TIMER_32_1_IRQHandler(void);
+void WEAK SSP_IRQHandler(void);
+void WEAK UART_IRQHandler(void);
+void WEAK USB_IRQHandler(void);
+void WEAK USB_FIQHandler(void);
+void WEAK ADC_IRQHandler(void);
+void WEAK WDT_IRQHandler(void);
+void WEAK BOD_IRQHandler(void);
+void WEAK EINT3_IRQHandler(void);
+void WEAK EINT2_IRQHandler(void);
+void WEAK EINT1_IRQHandler(void);
+void WEAK EINT0_IRQHandler(void);
+
+
+/* Exported types --------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+extern unsigned long _etext;
+extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */
+extern unsigned long _sdata; /* start address for the .data section. defined in linker script */
+extern unsigned long _edata; /* end address for the .data section. defined in linker script */
+
+extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */
+extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */
+extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */
+
+extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */
+extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */
+
+extern void _estack; /* init value for the stack pointer. defined in linker script */
+
+extern void (_setup_board)(void); /* setup_board adress function */
+extern unsigned long _mem_app_start;
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* function prototypes ------------------------------------------------------*/
+void Reset_Handler(void) __attribute__((__interrupt__));
+//void Reset_Handler(void);
+extern int main(void);
+
+typedef void (*FNC)(void);
+FNC fnc_entry;
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+
+extern unsigned long _stack;
+
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) =
+{
+ (void (*)(void))&_stack, /* The initial stack pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ // External Interrupts
+ WAKEUP0_IRQHandler,
+ WAKEUP1_IRQHandler,
+ WAKEUP2_IRQHandler,
+ WAKEUP3_IRQHandler,
+ WAKEUP4_IRQHandler,
+ WAKEUP5_IRQHandler,
+ WAKEUP6_IRQHandler,
+ WAKEUP7_IRQHandler,
+ WAKEUP8_IRQHandler,
+ WAKEUP9_IRQHandler,
+ WAKEUP10_IRQHandler,
+ WAKEUP11_IRQHandler,
+ WAKEUP12_IRQHandler,
+ WAKEUP13_IRQHandler,
+ WAKEUP14_IRQHandler,
+ WAKEUP15_IRQHandler,
+ WAKEUP16_IRQHandler,
+ WAKEUP17_IRQHandler,
+ WAKEUP18_IRQHandler,
+ WAKEUP19_IRQHandler,
+ WAKEUP20_IRQHandler,
+ WAKEUP21_IRQHandler,
+ WAKEUP22_IRQHandler,
+ WAKEUP23_IRQHandler,
+ WAKEUP24_IRQHandler,
+ WAKEUP25_IRQHandler,
+ WAKEUP26_IRQHandler,
+ WAKEUP27_IRQHandler,
+ WAKEUP28_IRQHandler,
+ WAKEUP29_IRQHandler,
+ WAKEUP30_IRQHandler,
+ WAKEUP31_IRQHandler,
+ WAKEUP32_IRQHandler,
+ WAKEUP33_IRQHandler,
+ WAKEUP34_IRQHandler,
+ WAKEUP35_IRQHandler,
+ WAKEUP36_IRQHandler,
+ WAKEUP37_IRQHandler,
+ WAKEUP38_IRQHandler,
+ WAKEUP39_IRQHandler,
+ I2C_IRQHandler,
+ TIMER_16_0_IRQHandler,
+ TIMER_16_1_IRQHandler,
+ TIMER_32_0_IRQHandler,
+ TIMER_32_1_IRQHandler,
+ SSP_IRQHandler,
+ UART_IRQHandler,
+ USB_IRQHandler,
+ USB_FIQHandler,
+ ADC_IRQHandler,
+ WDT_IRQHandler,
+ BOD_IRQHandler,
+ EINT3_IRQHandler,
+ EINT2_IRQHandler,
+ EINT1_IRQHandler,
+ EINT0_IRQHandler
+};
+
+/*******************************************************************************
+* Function Name : Reset_Handler
+* Description : This is the code that gets called when the processor first starts execution
+* following a reset event. Only the absolutely necessary set is performed,
+* after which the application supplied main() routine is called.
+* Input :
+* Output :
+* Return :
+*******************************************************************************/
+
+void Reset_Handler(void)
+{
+ unsigned long *pulDest;
+ unsigned long *pulSrc;
+
+ //
+ // Copy the data segment initializers from flash to SRAM in ROM mode
+ //
+
+ if (&_sidata != &_sdata) { // only if needed
+ pulSrc = &_sidata;
+ for(pulDest = &_sdata; pulDest < &_edata; ) {
+ *(pulDest++) = *(pulSrc++);
+ }
+ }
+
+ // Copy the .fastcode code from ROM to SRAM
+
+ if (&_sifastcode != &_sfastcode) { // only if needed
+ pulSrc = &_sifastcode;
+ for(pulDest = &_sfastcode; pulDest < &_efastcode; ) {
+ *(pulDest++) = *(pulSrc++);
+ }
+ }
+
+ //
+ // Zero fill the bss segment.
+ //
+ for(pulDest = &_sbss; pulDest < &_ebss; )
+ {
+ *(pulDest++) = 0;
+ }
+
+ // set irq table
+ SCB->VTOR=0x10000000;
+ //
+ // remap IRQ vector or not, depending on their RAM/ROM location
+ //
+ LPC_SYSCON->SYSMEMREMAP = 1 + ((&g_pfnVectors == (void*)0x0)?0:1);
+
+
+ _setup_board();
+
+
+
+ //
+ // Call the application's entry point.
+ //
+ main();
+
+ /* disable interrupts */
+ NVIC->ICER[0] = 0xffffffff;
+ NVIC->ICER[1] = 0x00000007;
+ __set_MSP(*(unsigned long *)(&_mem_app_start)); /* Stack pointer */
+ fnc_entry = (FNC)*(unsigned long *)(&_mem_app_start+1); /* Reset handler */
+ fnc_entry();
+}
+
+//*****************************************************************************
+//
+// Provide weak aliases for each Exception handler to the Default_Handler.
+// As they are weak aliases, any function with the same name will override
+// this definition.
+//
+//*****************************************************************************
+#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */
+#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */
+#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */
+#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */
+#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */
+#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */
+#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */
+
+
+/* External interrupt vector handler */
+#pragma weak WAKEUP0_IRQHandler = Default_Handler
+#pragma weak WAKEUP1_IRQHandler = Default_Handler
+#pragma weak WAKEUP2_IRQHandler = Default_Handler
+#pragma weak WAKEUP3_IRQHandler = Default_Handler
+#pragma weak WAKEUP4_IRQHandler = Default_Handler
+#pragma weak WAKEUP5_IRQHandler = Default_Handler
+#pragma weak WAKEUP6_IRQHandler = Default_Handler
+#pragma weak WAKEUP7_IRQHandler = Default_Handler
+#pragma weak WAKEUP8_IRQHandler = Default_Handler
+#pragma weak WAKEUP9_IRQHandler = Default_Handler
+#pragma weak WAKEUP10_IRQHandler = Default_Handler
+#pragma weak WAKEUP11_IRQHandler = Default_Handler
+#pragma weak WAKEUP12_IRQHandler = Default_Handler
+#pragma weak WAKEUP13_IRQHandler = Default_Handler
+#pragma weak WAKEUP14_IRQHandler = Default_Handler
+#pragma weak WAKEUP15_IRQHandler = Default_Handler
+#pragma weak WAKEUP16_IRQHandler = Default_Handler
+#pragma weak WAKEUP17_IRQHandler = Default_Handler
+#pragma weak WAKEUP18_IRQHandler = Default_Handler
+#pragma weak WAKEUP19_IRQHandler = Default_Handler
+#pragma weak WAKEUP20_IRQHandler = Default_Handler
+#pragma weak WAKEUP21_IRQHandler = Default_Handler
+#pragma weak WAKEUP22_IRQHandler = Default_Handler
+#pragma weak WAKEUP23_IRQHandler = Default_Handler
+#pragma weak WAKEUP24_IRQHandler = Default_Handler
+#pragma weak WAKEUP25_IRQHandler = Default_Handler
+#pragma weak WAKEUP26_IRQHandler = Default_Handler
+#pragma weak WAKEUP27_IRQHandler = Default_Handler
+#pragma weak WAKEUP28_IRQHandler = Default_Handler
+#pragma weak WAKEUP29_IRQHandler = Default_Handler
+#pragma weak WAKEUP30_IRQHandler = Default_Handler
+#pragma weak WAKEUP31_IRQHandler = Default_Handler
+#pragma weak WAKEUP32_IRQHandler = Default_Handler
+#pragma weak WAKEUP33_IRQHandler = Default_Handler
+#pragma weak WAKEUP34_IRQHandler = Default_Handler
+#pragma weak WAKEUP35_IRQHandler = Default_Handler
+#pragma weak WAKEUP36_IRQHandler = Default_Handler
+#pragma weak WAKEUP37_IRQHandler = Default_Handler
+#pragma weak WAKEUP38_IRQHandler = Default_Handler
+#pragma weak WAKEUP39_IRQHandler = Default_Handler
+#pragma weak I2C_IRQHandler = Default_Handler
+#pragma weak TIMER16_0_IRQHandler = Default_Handler
+#pragma weak TIMER16_1_IRQHandler = Default_Handler
+#pragma weak TIMER32_0_IRQHandler = Default_Handler
+#pragma weak TIMER32_1_IRQHandler = Default_Handler
+#pragma weak SSP_IRQHandler = Default_Handler
+#pragma weak UART_IRQHandler = Default_Handler
+#pragma weak USB_IRQHandler = Default_Handler
+#pragma weak USB_FIQHandler = Default_Handler
+#pragma weak ADC_IRQHandler = Default_Handler
+#pragma weak WDT_IRQHandler = Default_Handler
+#pragma weak BOD_IRQHandler = Default_Handler
+#pragma weak FMC_IRQHandler = Default_Handler
+#pragma weak PIOINT3_IRQHandler = Default_Handler
+#pragma weak PIOINT2_IRQHandler = Default_Handler
+#pragma weak PIOINT1_IRQHandler = Default_Handler
+#pragma weak PIOINT0_IRQHandler = Default_Handler
+
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+void Default_Handler(void) {
+ // Go into an infinite loop.
+ //
+ while (1) {
+ }
+}
--- /dev/null
+../../mach-lpc17xx/libs/iap
\ No newline at end of file
projects / sysless.git / commitdiff