--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = defines libs
--- /dev/null
+# -*- makefile -*-
+
+ARCH=h8300
+MACH=2638
+BOARD=h8heli
+
+#PREFIX_DIR=$(BOARD)
+
+
+CROSS_COMPILE = h8300-coff-
+TARGET_ARCH = -ms -D SCI_RS232_PORT_NUM=0
+
+# Set default C flags. If theese are set elsewhere (e.g. on a command
+# line), these default flags are not used.
+DEBUG ?= -g
+OPTIMIZE ?= -O2
+
+-include $(MAKERULES_DIR)/config.tohit
+HIT_BAUD ?= 57600
+HIT_DEV ?= /dev/ttyS0
+TOHIT = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tohit --baud $(HIT_BAUD) --sdev $(HIT_DEV)
+LOAD_CMD-boot = \
+ $(TOHIT) --erase --start 0x000000 --length 0x1600; \
+ $(TOHIT) --command 1 --blockmode 32 --start 0x000000
+LOAD_CMD-bload = $(TOHIT) --command B --blockmode 128 --baud 4800
+LOAD_CMD-flash = \
+ $(TOHIT) --erase --start 0x004000 --length 0x03C000; \
+ $(TOHIT) --command 1 --blockmode 32 --start 0x004000
+
+RUN_CMD-ram = $(TOHIT) --go 0x200000
+RUN_CMD-flash = $(TOHIT) --go 0x004000
+
+# This selects linker script
+LD_SCRIPT = h8heli
+DEFAULT_LD_SCRIPT_VARIANT = flash
+
+OUTPUT_FORMATS = bin
+
+
+CONFIG_USB_BASE=n
+CONFIG_USB_PDIUSB=n
+CONFIG_USB_MORE=n
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ system_def.h - common cover for definition of hardware adresses,
+ registers, timing and other hardware dependant
+ parts of embedded hardware
+
+ Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#ifndef _SYSTEM_DEF_H_
+#define _SYSTEM_DEF_H_
+
+#include <types.h>
+
+#define WITH_SFI_SEL
+
+#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
+/* Software version */
+#define SW_VER_ID "H8HELI"
+#define SW_VER_MAJOR 0
+#define SW_VER_MINOR 1
+#define SW_VER_PATCH 0
+#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
+/* Hardware version */
+#define HW_VER_ID "H8HELI"
+#define HW_VER_MAJOR 1
+#define HW_VER_MINOR 0
+#define HW_VER_PATCH 0
+#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
+/* Version of mechanical */
+#define MECH_VER_ID "H8HELI"
+#define MECH_VER_MAJOR 0
+#define MECH_VER_MINOR 0
+#define MECH_VER_PATCH 0
+#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
+
+#define CPU_REF_HZ 10000000l /* reference clock for H8HELI */
+#define CPU_SYS_HZ 20000000l /* default system for H8HELI */
+
+
+unsigned long cpu_ref_hz; /* actual external XTAL reference */
+unsigned long cpu_sys_hz; /* actual system clock frequency */
+
+volatile unsigned long msec_time;
+
+/* Buffer stransferred to second board power control register */
+/* SRAM 32 kB (CS3) */
+//#define SRAM_START (volatile __u8 * const)(0x610000)
+
+#if 0
+#define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
+#define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
+#define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
+#define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
+
+/* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
+#undef PDIUSB_WITH_ADD_IRQ_HANDLER
+#define PDIUSB_WITH_EXCPTVECT_SET
+#define PDIUSB_SUPPORT_ENABLED
+#endif
+
+
+#if 0
+/* IDE (CS4) (CS5) powered by PF2 */
+#define SIDE_START1 (volatile __u8 * const)(0x800000)
+#define SIDE_START2 (volatile __u8 * const)(0xA00000)
+#define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
+#define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
+#define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
+#define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
+#define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
+#define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
+#define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
+#define IDE0_STATUS (SIDE_START1+14) /* Status */
+#define IDE0_SELECT IDE0_CURRENT
+#define IDE0_FEATURE IDE0_ERROR
+#define IDE0_COMMAND IDE0_STATUS /* Command */
+
+#define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
+#define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
+
+#define IDE0_SETPWR(pwr) do{ \
+ if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
+ else atomic_set_mask_b1(4,DIO_PFDR); \
+ }while(0)
+
+#define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
+
+#if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
+ #define IDE_SWAP_BYTES
+#endif
+
+#define IDE0_SUPPORT_ENABLED
+#endif
+
+
+/* IRAM 16 kB of on-chip memory */
+/* 0xffb000-0xffcfff .. 8 kB free */
+/* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
+/* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
+/* 0xffffc0-0xffffff .. 64 B free*/
+#define IRAM_START (volatile __u8 * const)(0xffb000)
+#define IRAM_START1 (volatile __u8 * const)(0xffe000)
+#define FRAM_START (volatile __u8 * const)(0xffffc0)
+
+/* SCI0 - IrDA */
+/* SCI1 - IIC0 (P34, P35) */
+/* SCI2 - Boot */
+/* SCI3 - SPI */
+/* SCI4 - RS232/485 */
+
+/* IRQ0 - RTC */
+/* IRQ1 - Index mark */
+/* IRQ6 - IDE */
+
+/* Some registers are read only on H8S processors */
+/* We use shadow registers for some of them */
+#define SHADOW_REG_ALT(_reg,_mask,_xor) \
+ (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
+
+#define SHADOW_REG_SET(_reg,_mask) \
+ (*(_reg)=_reg##_shadow|=(_mask))
+
+#define SHADOW_REG_CLR(_reg,_mask) \
+ (*(_reg)=_reg##_shadow&=~(_mask))
+
+#define SHADOW_REG_RD(_reg) \
+ (_reg##_shadow)
+
+#define SHADOW_REG_WR(_reg,_val) \
+ (*(_reg)=_reg##_shadow=(_val))
+
+extern __u8 DIO_P1DDR_shadow;
+extern __u8 DIO_P3DDR_shadow;
+extern __u8 DIO_PCDDR_shadow;
+extern __u8 DIO_PEDDR_shadow;
+extern __u8 DIO_PFDDR_shadow;
+extern __u8 DIO_PJDDR_shadow;
+
+#define DEB_LED_INIT() \
+ do {\
+ *DIO_PCDR=0x00;\
+ SHADOW_REG_SET(DIO_PEDDR,0x0f); /* set LED as output */ \
+ } while (0)
+
+#define DEB_LED_OFF(num) \
+ (*DIO_PCDR |= PCDR_PC0DRm << (num))
+#define DEB_LED_ON(num) \
+ (*DIO_PCDR &=~(PCDR_PC0DRm << (num)))
+
+#endif /* _SYSTEM_DEF_H_ */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
+
+SUBDIRS = bspbase
+
+# ldscript_ADD_PREFIX_PATH = crt0\.o
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+lib_LIBRARIES = bspbase
+
+bspbase_SOURCES = bsp0hwinit.c setup_board.S
+
+lib_obj_SOURCES = bsp0common.c bsp0hwinit.c setup_board.S
--- /dev/null
+/* procesor H8S/2638 ver 1.1 */
+#include <types.h>
+#include <cpu_def.h>
+#include <h8s2638h.h>
+#include <system_def.h>
+
+#define SHADOW_SECT __attribute((section (".shadreg")))
+
+__u8 DIO_P1DDR_shadow SHADOW_SECT;
+__u8 DIO_P3DDR_shadow SHADOW_SECT;
+__u8 DIO_PCDDR_shadow SHADOW_SECT;
+__u8 DIO_PEDDR_shadow SHADOW_SECT;
+__u8 DIO_PFDDR_shadow SHADOW_SECT;
+__u8 DIO_PJDDR_shadow SHADOW_SECT;
--- /dev/null
+/* procesor H8S/2638 ver 1.1 */
+#include <types.h>
+#include <cpu_def.h>
+#include <h8s2638h.h>
+#include <system_def.h>
+#include <string.h>
+#include <boot_fn.h>
+
+#ifdef XRAM_SUPPORT_ENABLED
+#define FULL_XRAM_ADRBUS
+#endif /*XRAM_SUPPORT_ENABLED*/
+#define SMALL_ADRBUS 8
+
+static void deb_led_out(char val)
+{
+ if (val&1)
+ DEB_LED_ON(0);
+ else
+ DEB_LED_OFF(0);
+ if (val&2)
+ DEB_LED_ON(1);
+ else
+ DEB_LED_OFF(1);
+ if (val&4)
+ DEB_LED_ON(2);
+ else
+ DEB_LED_OFF(2);
+ if (val&8)
+ DEB_LED_ON(3);
+ else
+ DEB_LED_OFF(3);
+}
+
+void _setup_board()
+{
+ //int i, j;// POE-100
+
+#if 1 /* registers setup */
+ /* Internal RAM enabled, advanced interrupt mode */
+ /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
+
+ /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
+ /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
+ /* Sideefect - sets Flash software protection */
+
+ /* Enables access to flash control registers */
+ *IIC_SCRX |= SCRX_FLSHEm;
+
+ /* set shadow registers */
+ DIO_P1DDR_shadow=0;
+ DIO_P3DDR_shadow=0;
+ DIO_PCDDR_shadow=0;
+ DIO_PFDDR_shadow=0;
+ DIO_PJDDR_shadow=0;
+
+ DEB_LED_INIT();
+
+ /* show something on debug leds */
+ deb_led_out(0);
+ FlWait(1*100000);
+
+ SHADOW_REG_SET(DIO_P1DDR,0x03); /* A20 and A21 are outputs */
+
+ *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
+ SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
+
+ /* Setup system clock oscilator */
+ /* PLL mode x4, */
+ /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
+ /* PLL mode x2, */
+ /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
+ {
+ const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
+ *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
+ clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
+ }
+ deb_led_out(1);
+ FlWait(1*100000);
+
+ /* No clock disable, immediate change, busmaster high-speed */
+ *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
+ // POE-100
+#if 0
+ /* Setup chipselect outputs CS4 CS5 CS6 */
+ *DIO_P7DR |=1|2|4;
+ SHADOW_REG_SET(DIO_P7DDR,1|2|4);
+#else
+ // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
+#endif
+
+ /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
+ // *DIO_PGDR |=2|4|8|0x10; no on 2638
+#if 0
+ SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
+#else
+ // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
+#endif
+
+#if 1
+ /* setup chipselect 0 - FLASH */
+ *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
+ *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
+ //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
+ *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
+
+ /* setup chipselect 1 - XRAM */
+ *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
+ *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
+ *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
+
+ /* setup chipselect 2 - USB */
+ *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
+ *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
+ *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
+
+ /* setup chipselect 3 - KBD */
+ *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
+ *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
+#endif
+
+#if 0
+ /* setup chipselect 4 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
+
+ /* setup chipselect 5 - IDE */
+ *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
+ *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
+ *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
+
+ /* setup chipselect 6 - KL41 */
+ *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
+ *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
+ *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
+#endif
+
+ deb_led_out(2);
+ FlWait(1*100000);
+
+#if 1
+ /* cross cs wait| rd/wr wait | no burst and DRAM */
+ *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
+ /* release | no DMAC buffer | no external wait */
+ *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
+ *DIO_PCDDR=0xff; /* A0-A7 are outputs */
+#ifndef SMALL_ADRBUS
+ *DIO_PBDDR=0xff; /* A8-A15 are outputs */
+#endif /*SMALL_ADRBUS*/
+#ifndef FULL_XRAM_ADRBUS
+#ifndef SMALL_ADRBUS
+ *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
+#else /*SMALL_ADRBUS*/
+ *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
+#endif /*SMALL_ADRBUS*/
+#endif /* FULL_XRAM_ADRBUS */
+
+#endif /* registers setup */
+
+ FlWait(1*100000);
+
+#ifdef FULL_XRAM_ADRBUS
+ /* Setup full 22 address lines */
+ *DIO_PADR|=0x0f;
+ *DIO_PADDR=0x0f; /* A16-A19 are outputs */
+ /* number of address output signals */
+ *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
+#endif /*FULL_XRAM_ADRBUS*/
+#endif
+
+}
+
--- /dev/null
+
+#if defined(__H8300H__)
+ .h8300h
+#endif
+#if defined(__H8300S__)
+ .h8300s
+#endif
+
+.text
+
+.align 2
+
+.global ___setup_board
+
+___setup_board :
+ mov.l #__iram0_end,sp
+ jsr __setup_board
+ jmp _start
+
+.end
--- /dev/null
+/* memory ranges configuration for ID_CPU1 board */
+
+OUTPUT_FORMAT("coff-h8300")
+OUTPUT_ARCH(h8300s)
+
+ __flash_base = 0x000000 ;
+ __flash_size = 0x040000 ;
+ __flashbb_size = 0x002000 ;
+ __flashpb_size = 0x001000 ;
+ __ram_base = 0x200000 ;
+ __ram_end = 0x2fffff ;
+ __iram0_base = 0xffb000 ;
+ __iram0_end = 0xffcfff ;
+
+ __flashpb_base = __flash_base + __flashbb_size ;
+
+MEMORY
+ {
+ iramvec (w) : ORIGIN = 0x000000, LENGTH = 0x400
+ flashvec (rx) : ORIGIN = 0x000000, LENGTH = 0x400
+ iramdtc (w) : ORIGIN = 0x000400, LENGTH = 0x100
+ flashdtc (rx) : ORIGIN = 0x000400, LENGTH = 0x100
+ iramlow (w) : ORIGIN = 0x000500, LENGTH = 0x1000-0x500
+ flashbb (rx) : ORIGIN = 0x000500, LENGTH = 0x2000-0x500
+ flashpb1 (rx) : ORIGIN = 0x002000, LENGTH = 0x1000
+ flashpb2 (rx) : ORIGIN = 0x003000, LENGTH = 0x1000
+ flashusr (rx) : ORIGIN = 0x004000, LENGTH = 0x40000-0x4000
+ ram (w) : ORIGIN = 0x200000, LENGTH = 0x100000
+ ramstby (w) : ORIGIN = 0x610000, LENGTH = 0x8000
+ iram0 (w) : ORIGIN = 0xffb000, LENGTH = 0x2000
+ bloader (w) : ORIGIN = 0xffc000, LENGTH = 0x2000
+ iram1 (w) : ORIGIN = 0xffe000, LENGTH = 0x1000-0x40
+ eight (w) : ORIGIN = 0xffffc0, LENGTH = 0x40
+ }
+
--- /dev/null
+/* linker script for inteligent boot block (hardwired boot mode) */
+
+INCLUDE "h8canusb.ld-cfg"
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+
+INPUT(bsp0common.o)
+
+SECTIONS
+{
+ .text :
+ {
+ text_start = . ;
+/* KEEP (crt0.o(.text))*/
+ *(EXCLUDE_FILE(*boot_fn.o) .text)
+ *(EXCLUDE_FILE(*boot_fn.o) .rodata)
+ *(.strings)
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .shadreg (NOLOAD) :
+ {
+ *(.shadreg)
+ . = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .data :
+ {
+ ___data_lma = . ;
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > bloader
+
+ .bss :
+ {
+ . = ALIGN( 0x4 ) ;
+ _bss_start = ALIGN( 0x4 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ; ;
+ } > bloader
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for inteligent boot block (for user-program-mode boot-loader in flash) */
+
+INCLUDE "h8canusb.ld-cfg"
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+/*PROVIDE( ___setup_board = _start);*/
+
+STARTUP(crt0.o)
+INPUT(bsp0common.o)
+INPUT(bsp0hwinit.o setup_board.o)
+
+SECTIONS
+{
+ .fvector :
+ {
+ ___flashbb_vector = . ;
+ LONG( ABSOLUTE( ___setup_board ) )
+ *(.fvector)
+ } > flashvec
+
+ .shadreg (NOLOAD) :
+ {
+ *(.shadreg)
+ . = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .text :
+ {
+ text_start = . ;
+ KEEP (crt0.o(.text))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ *(.strings)
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > flashbb
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ ___data_lma = ALIGN( 0x4 ) ;
+ } > flashbb /*at> flashusr*/
+
+ .data :
+ AT ( ADDR( .tors ) + SIZEOF( .tors ) )
+ {
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > iram1
+
+ /* ___data_lma = LOADADDR(.data) ; */
+
+ .bss :
+ {
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = . ;
+ } > iram0
+
+ .flashusr :
+ {
+ _usrprog_start = . ;
+ } > flashusr
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for applications running from FLASH */
+
+INCLUDE "h8canusb.ld-cfg"
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+/*PROVIDE( ___heap_end = __ram_end );*/
+PROVIDE( ___heap_end = __iram0_end - 0x200 );
+
+STARTUP(crt0.o)
+INPUT(bsp0common.o)
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN( 4 ) ;
+ text_start = . ;
+ LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
+/* KEEP (crt0.o(.text)) */
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ _etext = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .shadreg (NOLOAD) :
+ {
+ *(.shadreg)
+ . = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x10 ) ;
+ ___data_lma = ALIGN( 0x10 ) ;
+ } > flashusr
+
+ .data :
+ AT ( ADDR( .tors ) + SIZEOF( .tors ) )
+ {
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > iram0 /*at> flashusr*/
+
+ /* ___data_lma = LOADADDR(.data) ; */
+
+ .bss :
+ {
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
--- /dev/null
+/* linker script for applications running from RAM */
+
+INCLUDE "h8canusb.ld-cfg"
+
+/* SEARCH_DIR(/HDA8/root/h8300/id_cpu1/test1/../lib); */
+
+/* PROVIDE ( sym = val ); */
+
+PROVIDE( ___stack_top = ( __iram0_end & ~ 3 ) - 4 );
+PROVIDE( ___heap_end = __ram_end );
+
+STARTUP(crt0.o)
+INPUT(bsp0common.o)
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN( 4 ) ;
+ text_start = . ;
+ LONG( ABSOLUTE( _start ) + 0x5a000000 ) /* JMP _start */
+/* KEEP (crt0.o(.text)) */
+ . = ALIGN( 4 ) ;
+ ___boot_fn_start = ALIGN( 0x4 ) ;
+ KEEP (*boot_fn.o(.text))
+ KEEP (*boot_fn.o(.rodata))
+ . = ALIGN( 4 ) ;
+ ___boot_fn_end = ALIGN( 0x4 ) ;
+ *(.text)
+ *(.rodata)
+ . = ALIGN( 4 ) ;
+ ___nls_str_start = ALIGN( 0x4 ) ;
+ *(.nls_str)
+ ___nls_str_end = ALIGN( 0x4 ) ;
+ *(.strings)
+ . = ALIGN( 0x4 ) ;
+ _etext = ALIGN( 0x4 ) ;
+ } > ram
+
+ .shadreg (NOLOAD) :
+ {
+ *(.shadreg)
+ . = ALIGN( 0x4 ) ;
+ } > iram0
+
+ .tors :
+ {
+ ___ctors = . ;
+ *(.ctors)
+ ___ctors_end = . ;
+ ___dtors = . ;
+ *(.dtors)
+ ___dtors_end = . ;
+ . = ALIGN( 0x4 ) ;
+ } > ram
+
+ .data :
+ {
+ ___data_lma = . ;
+ _data_start = . ;
+ *(.data)
+ . = ALIGN( 0x4 ) ;
+ _edata = ALIGN( 0x4 ) ;
+ } > ram
+
+ .bss :
+ {
+ . = ALIGN( 0x10 ) ;
+ _bss_start = ALIGN( 0x10 ) ;
+ *(.bss)
+ *(COMMON)
+ . = ALIGN( 0x4 ) ;
+ _end = ALIGN( 0x4 ) ;
+ } > ram
+
+ .tiny :
+ {
+ *(.tiny)
+ } > iram0
+
+ .eight :
+ {
+ *(.eight)
+ } > eight
+
+ .stab 0 (NOLOAD) :
+ {
+ [ .stab ]
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ [ .stabstr ]
+ }
+}
projects / sysless.git / commitdiff